Although we wanted mainly to discuss real, marketable systems and no experimental, special purpose, or even speculative machines, we want to include a section on systems that are in a far stage of development and have a fair chance of reaching the market. For inclusion in section 3 we set the rule that the system described there should be on the market within a period of 6 months from announcement. The systems described in this section will in all probability appear within one year from the publication of this report. However, there are vendors who do not want to disclose any specific data on their new machines until they are actually beginning to ship them (an example is the SGI Origin 2000). We recognise the wishes of such vendors (it is generally wise not to stretch the expectation of potential customers too long) and will not disclose such information.
Below we discuss systems that may lead to commercial systems to be introduced on the market between somewhat more than half a year to a year from now. The commercial systems that result from it will sometimes deviate significantly from the original research models depending on the way the development is done (the approaches in Japan and the USA differ considerably in this respect) and the user group with is targeted.
Although no details are publicly known, a new system Hitachi is expected in the first half of 1998. This machine should replace the S3600/S3800 series of vector processors and at the same time be scalable to a considerable number of processors. In all probability, the structure of the system will be much like the NEC SX-4, clustering the a modest amount of vector processors in an SMP fashion and connecting the clusters by a crossbar network. As said, no details of individual processor speed, connection type, or connection capacity are known at this stage.
Of a successor for the Hitachi SR2201 massively parallel processor product line, presently nothing is known.
NEC has, like Hitachi, a massively parallel processor product line and a vector processor line. The former, the Cenju-3, is not very actively marketed and information is scarce. Still a successor is planned featuring the MIPS R10000 a its basic processor. This would speed up the speed per node with a factor of about 10, as a 500 Mflop/s R10000 will be available soon. Presently, no details, like the number of processors, and the network capacity are disclosed. However, one can assume that the machine structure largely will be retained.
This year a successor, the SX-5, of the reasonably successful NEC SX-4 system is expected. The structure is believed to be almost identical to the that of the SX-4. Probably, no models with the expensive static RAM memories will be offerred anymore as was the case with the SX-4 models. It may be assumed that the processor speed will grow four-fold to about 8 Gflop/s when keeping in line with the general growth in speed over time. As the clustered shared-memory systems have worked well for NEC, the SX-5 undoubtly will have the same structure as the SX-4 systems.
It is not sure when a new SGI/Cray will come out, only that this will be in 1998. In view of the success and the cost/performance of the Fujitsu VPP300/700and the NEC SX-4 it stands to reason that SGI/Cray will offer a similar machine based on CMOS technology and with vector processors. SGI/Cray has already experience with such systems, the Cray Y-MP EL and the Cray J90, be it that the per processor speed is lower than that of the Japanese systems which are targeted to the top of the market while the J90 is a typical midrange system. To be interesting, the new system should be at least in the 1 Gflop/s per processor range as present-day RISC processors are also approaching this speed. Also the maximum number of processors will have to be higher than what now is offerred in the Cray vector systems (32 max.) but a definite number of processors is not known to the author yet.
For the T3E product line it is not expected that 1998 will bring a new system. With the T3E-1200 that was announced in November 1997 SGI/Cray probably has enough leeway to defer the presentation of a really different system in this sector for at least a year. When such a system is announced, it will contain almost certainly MIPS-built processors instead of the DEC Alhpa processors that are used now. As such a new system would be on the market by 1999/2000, the per processor peak performance should be at least be in the 2 \gfl range or higher.