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Performance Data (cont.)
ãI/D
cache misses for different levels
ãBranch
mispredictions
ãTLB misses
ãPipeline
stalls due to memory subsystem
ãPipeline
stalls due to resource conflicts
ãCache
invalidations
ãTLB invalidations
ãLoad/store count
ãInstruction count
ãCycle count
ãFloating point instruction count
ãInteger instruction count
ãBranch taken / not taken count