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The Parsytec GC/Power Plus.

Machine type RISC-based distributed-memory multi-processor
Models Parsytec GC/Power Plus
Operating system Unix on host processor, Parix (GC OS, transparent to the user)
Connection structure 2-D grid
Compilers Fortran 77, ANSI C, Pascal, Modula-2
Vendors information Web page

System parameters:

Model GC/Power Plus
Clock cycle 7.5 ns
Theor. peak performance
Per proc. (64-bits) 266 Mflop/s
Maximum (64-bits) ... Gflop/s
Main memory ... GB
Memory/node 16-128 MB
Communication bandwidth
Point-to-point 8.8 MB/s
No. of processors 8-...


The Parsytec GC Power Plus system (GC standing for Grand Challenge) is based on the IBM/Motorola MC604 processor. Initially, the CG series was planned to be built around the T9000 transputer. However, the T9000 is still not available in sufficient quantity and quality. Therefore, the MC601 was chosen to replace the T9000. It is not clear what is the maximum configuration for the Power Plus system. Therefore we could not give maximum performance, memory capacity, etc.

Each ``node'' (the term node not used here in the usual sense) of a GC Power Plus system contains two MC601 processors and 4 T805 transputers which are responsible for the communication. Two nodes are placed on one board, while 4 boards are interconnected with 16 C004 static routers to maintain the intercommunication within a so-called GC-cube. For every 4 nodes one redundant node is present for fault-tolerance. To complement the computing power, a parallel I/O system, the Parallel Storage System is available to aid in the handling of large-scale applications which require massive I/O.

The communication speed of the system is presently not particularly high with respect to the processor speed (although Parsytec from its PowerStone project claims that the present choice of computational versus communication capacity is optimal from the viewpoint of cost-effectiveness). There are plans to use T9000 transputers for communication instead of the present T805s and to replace the C004 routers by its successor, the C104. This would speed up the communication by at least a factor of 10, making the computation/communication speeds more balanced.

In the Parsytec CC series, also equipped with the MC604 but with ATM HS links, the link speed is up to about 75 MB/s. The CC series, however, is primarily directed to the embedded systems market.

The PARIX operating system is Unix-like. It allows to specify various virtual topologies onto the actual 2-D grid topology to match possible natural application topologies. Besides Parsytecs own communication library, PVM and PARMACS are available. An MPI communication library is presently developed.

Measured Performances: Early experiments have been done on a 64-processor system. On 4 processors the solution of an order N=1000 dense linear system attained a speed of 141 Mflop/s. For a scaled-up system on 32 processors a speed of 1007 Mflop/s was found, while for the NAS Embarassingly Parallel benchmark (see [#nasbm##1#] a speed of 2.8 Gflop/s was observed on 64 processors.

next up previous contents
Next: Systems Disappeared from the Up: Distributed-memory MIMD systems Previous: The Parsys TA9000.

Jack Dongarra
Sat Feb 10 15:12:38 EST 1996