@Preamble{
"\ifx \undefined \circled \def \circled #1{(#1)}\fi" #
"\ifx \undefined \reg \def \reg {\circled{R}}\fi" #
"\ifx \undefined \TM \def \TM {${}^{\sc TM}$} \fi"
}
@String{ack-nhfb = "Nelson H. F. Beebe,
University of Utah,
Department of Mathematics, 110 LCB,
155 S 1400 E RM 233,
Salt Lake City, UT 84112-0090, USA,
Tel: +1 801 581 5254,
FAX: +1 801 581 4148,
e-mail: \path|beebe@math.utah.edu|,
\path|beebe@acm.org|,
\path|beebe@computer.org| (Internet),
URL: \path|http://www.math.utah.edu/~beebe/|"}
@String{inst-HP = "Hewlett--Packard Corporation"}
@String{inst-HP:adr = "Palo Alto, CA, USA"}
@String{j-BYTE = "Byte Magazine"}
@String{j-CACM = "Communications of the ACM"}
@String{j-COMP-ARCH-NEWS = "ACM SIGARCH Computer Architecture News"}
@String{j-COMP-DESIGN = "Computer Design"}
@String{j-COMPUT-AIDED-ENG = "Computer-aided engineering: CAE"}
@String{j-COMPUTER = "Computer"}
@String{j-COMPUTERWOCHE = "Computerwoche"}
@String{j-DDJ = "Dr. Dobb's Journal of Software Tools"}
@String{j-DEC-TECH-J = "Digital Technical Journal of
Digital Equipment Corporation"}
@String{j-ELECTRONIC-DESIGN = "Electronic Design"}
@String{j-ELECTRONIK = "Elektronik"}
@String{j-FORM-METHODS-SYST-DES = "Formal Methods in System Design"}
@String{j-IEEE-COMPUT-ARCHIT-LETT = "IEEE Computer Architecture Letters"}
@String{j-IEEE-CONCURR = "IEEE Concurrency"}
@String{j-IEEE-J-SOLID-STATE-CIRCUITS = "IEEE Journal of Solid-State Circuits"}
@String{j-IEEE-MICRO = "IEEE Micro"}
@String{j-IEEE-SPECTRUM = "IEEE Spectrum"}
@String{j-IEEE-TRANS-SOFTW-ENG = "IEEE Transactions on Software Engineering"}
@String{j-INFORMATION-WEEK = "Information Week"}
@String{j-INTEL-TECH-J = "Intel Technology Journal"}
@String{j-LECT-NOTES-COMP-SCI = "Lecture Notes in Computer Science"}
@String{j-LIB-SYSTEMS = "Library systems"}
@String{j-LINUX-J = "Linux Journal"}
@String{j-MICROPROC-REP = "Microprocessor Report"}
@String{j-NEC-RES-DEV = "Nippon Electric Company research and
development"}
@String{j-NEC-TECH-J = "NEC Technical Journal = NEC giho"}
@String{j-OPER-SYS-REV = "Operating Systems Review"}
@String{j-QUEUE = "ACM Queue: Tomorrow's Computing Today"}
@String{j-SCI-PROG = "Scientific Programming"}
@String{j-SIGACT = "ACM SIGACT News"}
@String{j-SIGMETRICS = "ACM SIGMETRICS Performance Evaluation Review"}
@String{j-SIGNUM = "ACM SIGNUM Newsletter"}
@String{j-SIGPLAN = "ACM SIG{\-}PLAN Notices"}
@String{j-SPE = "Soft\-ware\emdash Prac\-tice and Experience"}
@String{j-TOCS = "ACM Transactions on Computer Systems"}
@String{j-TODAES = "ACM Transactions on Design Automation of
Electronic Systems (TODAES)"}
@String{j-TOMACS = "ACM Transactions on Modeling and
Computer Simulation"}
@String{j-TOMS = "ACM Transactions on Mathematical Software"}
@String{j-TOPLAS = "ACM Transactions on Programming
Languages and Systems"}
@String{j-UNIX-REVIEW = "UNIX Review"}
@String{j-WALL-ST-TECH = "Wall Street and Technology"}
@String{pub-ACM = "ACM Press"}
@String{pub-ACM:adr = "New York, NY, USA"}
@String{pub-HANSER = "Carl Hanser"}
@String{pub-HANSER:adr = "M{\"u}nchen, Germany"}
@String{pub-HP = "Hewlett--Packard Corporation"}
@String{pub-HP:adr = "Rockville, MD 20850, USA"}
@String{pub-IEEE = "IEEE Computer Society Press"}
@String{pub-IEEE:adr = "1109 Spring Street, Suite 300, Silver
Spring, MD 20910, USA"}
@String{pub-INTEL = "Intel Corporation"}
@String{pub-INTEL:adr = "Santa Clara, CA, USA"}
@String{pub-KLUWER = "Kluwer Academic Publishers Group"}
@String{pub-KLUWER:adr = "Norwell, MA, USA, and Dordrecht,
The Netherlands"}
@String{pub-MICROSOFT = "Microsoft Press"}
@String{pub-MICROSOFT:adr = "Bellevue, WA, USA"}
@String{pub-MIT = "MIT Press"}
@String{pub-MIT:adr = "Cambridge, MA, USA"}
@String{pub-MORGAN-KAUFMANN = "Morgan Kaufmann Publishers"}
@String{pub-MORGAN-KAUFMANN:adr = "San Francisco, CA, USA"}
@String{pub-MORGAN-KAUFMANN:adrbo = "Boston, MA, USA"}
@String{pub-NIST = "National Institute for Standards and
Technology"}
@String{pub-NIST:adr = "Gaithersburg, MD, USA"}
@String{pub-PH = "Pren{\-}tice-Hall"}
@String{pub-PH:adr = "Upper Saddle River, NJ 07458, USA"}
@String{pub-PHPTR = "Pren{\-}tice-Hall PTR"}
@String{pub-PHPTR:adr = "Upper Saddle River, NJ 07458, USA"}
@String{pub-SV = "Springer-Verlag Inc."}
@String{pub-SV:adr = "New York, NY, USA"}
@String{pub-USENIX = "USENIX"}
@String{pub-USENIX:adr = "Berkeley, CA, USA"}
@String{pub-WILEY = "Wiley"}
@String{pub-WILEY:adr = "New York, NY, USA"}
@String{ser-LNCS = "Lecture Notes in Computer Science"}
@Article{Moore:1965:CMC,
author = "Gordon E. Moore",
title = "Cramming More Components onto Integrated Circuits",
journal = "Electronics",
volume = "38",
number = "8",
pages = "114--117",
year = "1965",
bibdate = "Tue Nov 18 15:31:38 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.intel.com/technology/mooreslaw/index.htm",
acknowledgement = ack-nhfb,
remark = "This paper is the origin of \emph{Moore's Law}:
semiconductor performance roughly doubles every two
years or so.",
}
@PhdThesis{Fisher:1979:OHM,
author = "Joseph Allen Fisher",
title = "The Optimization of Horizontal Microcode With and
Beyond Basic Blocks: An Application of Processor
Scheduling with Resources",
type = "{Ph.D.} dissertation",
school = "Courant Institute, New York University",
address = "New York, NY, USA",
pages = "v + 174",
month = oct,
year = "1979",
bibdate = "Mon Aug 08 07:40:03 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://wwwlib.umi.com/dissertations/dlnow/8010348",
acknowledgement = ack-nhfb,
keywords = "CDC 6600; PUMA; trace scheduling",
}
@InProceedings{Fisher:1983:VLI,
author = "Joseph A. Fisher",
booktitle = "Proceedings of the 10th Annual International Symposium
on Computer Architectures, Stockholm, Sweden",
title = "Very Long Instruction Word Architectures and the
{ELI-512}",
volume = "11(3)",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "140--150",
year = "1983",
ISBN = "0-89791-101-6",
ISBN-13 = "978-0-89791-101-6",
ISSN = "0884-7495",
LCCN = "QA76.9.A73S9a",
bibdate = "Mon Aug 08 06:14:08 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Reprinted in \cite{Fisher:1998:VLI}.",
series = "SIGARCH Newsletter: Computer Architecture",
abstract = "By compiling ordinary scientific applications programs
with a radical technique called trace scheduling, we
are generating code for a parallel machine that will
run these programs faster than an equivalent sequential
machine --- we expect 10 to 30 times faster.\par
Trace scheduling generates code for machines called
Very Long Instruction Word architectures. In Very Long
Instruction Word machines, many statically scheduled,
tightly coupled, fine-grained operations execute in
parallel within a single instruction stream. VLIWs are
more parallel extensions of several current
architectures.\par
These current architectures have never cracked a
fundamental barrier. The speedup they get from
parallelism is never more than a factor of 2 to 3. Not
that we couldn't build more parallel machines of this
type; but until trace scheduling we didn't know how to
generate code for them. Trace scheduling finds
sufficient parallelism in ordinary code to justify
thinking about a highly parallel VLIW.\par
At Yale we are actually building one. Our machine, the
ELI-512, has a horizontal instruction word of over 500
bits and will do 10 to 30 RISC-level operations per
cycle [Patterson 82]. ELI stands for Enormously
Longword Instructions; 512 is the size of the
instruction word we hope to achieve. (The current
design has a 1200-bit instruction word.)\par
Once it became clear that we could actually compile
code for a VLIW machine, some new questions appeared,
and answers are presented in this paper. How do we put
enough tests in each cycle without making the machine
too big? How do we put enough memory references in each
cycle without making the machine too slow?",
acknowledgement = ack-nhfb,
bookpages = "ix + 438",
}
@Article{Higginbotham:1986:AF,
author = "T. F. Higginbotham",
title = "Another factor of $(10^{31} - 1)/9$",
journal = j-SIGNUM,
volume = "21",
number = "3",
pages = "12--12",
month = jul,
year = "1986",
CODEN = "SNEWD6",
DOI = "https://doi.org/10.1145/1057958.1057960",
ISSN = "0163-5778 (print), 1558-0237 (electronic)",
bibdate = "Thu Aug 07 18:41:01 2008",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "A second factor of $(10^{31} - 1)/9$ was found to be
6943319 with the use of an eight spoke wheel [1]. The
spokes D(i) were 1, 7, 11, 13, 17, 19, 23, and 29. The
possible factors 2, 3, and 5 were tested prior to
starting the wheel. The constant multiplier was 30. The
possible divisors were of the form $30 \times K + D(i),
K = 0, 1, 2, 3, \ldots{}$. The program was written in
COBOL for the Honeywell DPS 8, running under CP-6. The
picture clauses were selected such that 31-digit
decimal arithmetic was used. Execution time was about
forty-five minutes.",
acknowledgement = ack-nhfb,
keywords = "decimal arithmetic",
remark = "Maple 8 reports in 2 sec on a 1400 MHz Itanium IA-64:
ifactor((10^31 - 1)/9) = (57336415063790604359)
(6943319) (2791).",
}
@TechReport{Tirumalai:1990:PLE,
author = "Parthasarathy Tirumalai and Meng Lee and Michael S.
Schlansker",
title = "Parallelization of Loops with Exits on Pipelined
Architectures",
type = "Technical Report",
number = "HPL-90-107",
institution = inst-HP,
address = inst-HP:adr,
year = "1990",
bibdate = "Tue Nov 18 15:14:10 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.hpl.hp.com/techreports/",
acknowledgement = ack-nhfb,
}
@Article{Blickstein:1992:GOC,
author = "David S. Blickstein and Peter W. Craig and Caroline S.
Davidson and R. Neil {Faiman, Jr.} and Kent D. Glossop
and Richard B. Grove and Steven O. Hobbs and William B.
Noyce",
title = "The {GEM} Optimizing Compiler System",
journal = j-DEC-TECH-J,
volume = "4",
number = "4",
pages = "121--136",
month = "Fall",
year = "1992",
CODEN = "DTJOEL",
ISSN = "0898-901X",
bibdate = "Thu Mar 20 18:15:43 MST 1997",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "ftp://ftp.digital.com/pub/Digital/info/DTJ/v4n4/The_GEM_Optimizing_Compiler_Sy_01apr1993DTJ808P8.ps;
http://www.digital.com:80/info/DTJ808/DTJ808SC.TXT",
abstract = "The GEM compiler system is the technology Digital is
using to build state-of-the-art compiler products for a
variety of languages and hardware\slash software
platforms. Portable, modular software components with
carefully specified interfaces simplify the engineering
of diverse compilers. A single optimizer, independent
of the language and the target platform, transforms the
intermediate language generated by the front end into a
semantically equivalent form that executes faster on
the target machine. The GEM system supports a range of
languages and has been successfully retargeted and
rehosted for the Alpha AXP and MIPS architectures and
for several operating environments.",
acknowledgement = ack-nhfb,
classcodes = "C6150C (Compilers, interpreters and other processors);
C6140D (High level languages); C5220P (Parallel
architecture)",
classification = "C5220P (Parallel architecture); C6140D (High level
languages); C6150C (Compilers, interpreters and other
processors)",
keywords = "Alpha AXP; Compiler products; compiler products; DEC
computers; environments; equivalent form; GEM compiler
system; hardware/software; Hardware/software platforms;
high level languages; Intermediate language;
intermediate language; MIPS architectures; Modular
software components; modular software components;
operating; Operating environments; parallel
architectures; platforms; program compilers;
semantically; Semantically equivalent form; Single
optimizer; single optimizer; Target platform; target
platform",
thesaurus = "DEC computers; High level languages; Parallel
architectures; Program compilers",
treatment = "P Practical; R Product Review",
}
@TechReport{Rau:1992:ILP,
author = "B. Ramakrishna Rau and Joseph A. Fisher",
title = "Instruction-Level Parallel Processing: History,
Overview, and Perspective",
type = "Technical Report",
number = "HPL-92-132",
institution = inst-HP,
address = inst-HP:adr,
year = "1992",
bibdate = "Tue Nov 18 15:09:28 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.hpl.hp.com/techreports/",
acknowledgement = ack-nhfb,
}
@TechReport{Ramakrishna:1993:DST,
author = "B. Ramakrishna",
title = "Dynamic Scheduling Techniques for {VLIW} Processors",
type = "Technical Report",
number = "HPL-93-52",
institution = inst-HP,
address = inst-HP:adr,
year = "1993",
bibdate = "Tue Nov 18 15:08:31 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.hpl.hp.com/techreports/",
acknowledgement = ack-nhfb,
}
@Book{Rau:1993:ILP,
editor = "Bantwal Ramakrishna Rau and Joseph A. Fisher",
title = "Instruction-level parallelism: a special issue of {The
Journal of Supercomputing}",
volume = "SECS 235",
publisher = pub-KLUWER,
address = pub-KLUWER:adr,
pages = "282",
year = "1993",
ISBN = "0-7923-9367-8",
ISBN-13 = "978-0-7923-9367-2",
LCCN = "QA76.58 .I49 1993",
bibdate = "Mon Aug 8 06:04:12 MDT 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
z3950.loc.gov:7090/Voyager",
series = "The Kluwer international series in engineering and
computer science",
acknowledgement = ack-nhfb,
remark = "Reprinted from The journal of supercomputing, volume
7, number 1/2, 1993. Describes the Multiflow and Cydra
5 VLIW supercomputers whose architecture influenced
IA-64.",
subject = "Parallel processing (Electronic computers);
Supercomputers",
}
@Article{Christy:1996:IMW,
author = "Peter Christy",
title = "{IA-64} and {Merced} --- What and Why",
journal = j-MICROPROC-REP,
volume = "10",
number = "17",
pages = "17--19",
day = "30",
month = dec,
year = "1996",
ISSN = "0899-9341",
bibdate = "Sat Aug 04 12:39:54 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/15740-f00/public/doc/discussions/uniprocessors/ia64/mpr_merced_whats_new_dec96.ps.gz",
acknowledgement = ack-nhfb,
}
@Article{Gokhale:1996:DOO,
author = "Vipin V. Gokhale",
title = "Design of the 64-bit Option for the {Oracle7}
Relational Database Management System",
journal = j-DEC-TECH-J,
volume = "8",
number = "4",
pages = "76--??",
month = "????",
year = "1996",
CODEN = "DTJOEL",
ISSN = "0898-901X",
bibdate = "Fri Oct 17 19:42:47 MDT 1997",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.digital.com:80/info/DTJO06/DTJO06AH.HTM;
http://www.digital.com:80/info/DTJO06/DTJO06HM.HTM;
http://www.digital.com:80/info/DTJO06/DTJO06P8.PS;
http://www.digital.com:80/info/DTJO06/DTJO06PF.PDF;
http://www.digital.com:80/info/DTJO06/DTJO06SC.TXT",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:1997:OI,
author = "Anonymous",
title = "Optimizing the {IA-64}",
journal = j-IEEE-MICRO,
volume = "17",
number = "5",
pages = "6--6",
month = sep # "\slash " # oct,
year = "1997",
CODEN = "IEMIDZ",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Thu Dec 14 06:08:58 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
Science Citation Index database (1980--2000)",
acknowledgement = ack-nhfb,
}
@Article{Garber:1997:NBJ,
author = "Lee Garber and David Clark",
title = "News Briefs: Judge Rejects {US} Restrictions on Export
of Encryption; {Intel}, {HP} Unveil {Merced} Chip;
{Java} Wars Heat Up; {AOL} Acquires {CompuServe}
Subscribers; Confusion in the {DVD} Marketplace;
`Amazing Grace' Heads to Sea; {PC} Firms Back Down on
Convergence; Business Use Will Drive {Internet} Growth;
Company Offers \$1-Million Prize for Hackers",
journal = j-COMPUTER,
volume = "30",
number = "11",
pages = "22--25",
month = nov,
year = "1997",
CODEN = "CPTRB4",
ISSN = "0018-9162 (print), 1558-0814 (electronic)",
bibdate = "Mon Dec 8 20:53:24 MST 1997",
bibsource = "http://www.math.utah.edu/pub/tex/bib/computer1990.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://pdf.computer.org/co/books/co1997/pdf/ry022.pdf",
acknowledgement = ack-nhfb,
}
@Book{Gwennap:1997:IMI,
author = "Linley Gwennap",
title = "{Intel}'s {Merced} and {IA-64} technology and market
forecast",
publisher = "MicroDesign Resources",
address = "Sebastopol, CA, USA",
pages = "xiv + 96",
year = "1997",
ISBN = "1-885330-13-8",
ISBN-13 = "978-1-885330-13-0",
LCCN = "QA76.5 .G9524 1997",
bibdate = "Wed Mar 13 15:36:48 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Haavind:1997:PIP,
author = "Bob Haavind",
title = "Peek at {IA-64}, plus work-a-day embedded processors
bow --- First details of {Intel\slash H-P}
explicitly-parallel processor revealed at
{Microprocessor Forum}",
journal = j-COMP-DESIGN,
volume = "36",
number = "12",
pages = "64--69",
month = "????",
year = "1997",
CODEN = "CMPDAM",
ISSN = "0010-4566",
bibdate = "Tue Feb 06 18:38:22 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Kennedy:1997:NPC,
author = "Ken Kennedy and Charles F. Bender and John W. D.
Connolly and John L. Hennessy and Mary K. Vernon and
Larry Smarr",
title = "A Nationwide Parallel Computing Environment",
journal = j-CACM,
volume = "40",
number = "11",
pages = "62--72",
month = nov,
year = "1997",
CODEN = "CACMA2",
ISSN = "0001-0782 (print), 1557-7317 (electronic)",
bibdate = "Wed Dec 3 16:44:17 MST 1997",
bibsource = "http://www.acm.org/pubs/toc/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.acm.org:80/pubs/citations/journals/cacm/1997-40-11/p62-kennedy/",
acknowledgement = ack-nhfb,
keywords = "design; experimentation; IA-64; management;
performance",
subject = "{\bf C.5.1} Computer Systems Organization, COMPUTER
SYSTEM IMPLEMENTATION, Large and Medium (``Mainframe'')
Computers, Super (very large) computers. {\bf C.1.2}
Computer Systems Organization, PROCESSOR ARCHITECTURES,
Multiple Data Stream Architectures (Multiprocessors),
Parallel processors**. {\bf K.3.0} Computing Milieux,
COMPUTERS AND EDUCATION, General. {\bf I.3.7} Computing
Methodologies, COMPUTER GRAPHICS, Three-Dimensional
Graphics and Realism, Virtual reality. {\bf D.1.3}
Software, PROGRAMMING TECHNIQUES, Concurrent
Programming, Parallel programming. {\bf K.6.3}
Computing Milieux, MANAGEMENT OF COMPUTING AND
INFORMATION SYSTEMS, Software Management, Software
development.",
}
@Article{VanderWiel:1997:WCA,
author = "Steven P. VanderWiel and David J. Lilja",
title = "When Caches Aren't Enough: Data Prefetching
Techniques",
journal = j-COMPUTER,
volume = "30",
number = "7",
pages = "23--30",
month = jul,
year = "1997",
CODEN = "CPTRB4",
ISSN = "0018-9162 (print), 1558-0814 (electronic)",
bibdate = "Mon Feb 25 15:21:34 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/co/books/co1997/pdf/r7023.pdf;
http://www.computer.org/computer/co1997/r7023abs.htm",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64",
}
@InProceedings{Warton:1997:PSI,
author = "John Warton",
title = "Panel Session: If {{\em I}} Were Defining `{Merced}'",
crossref = "IEEE:1997:HCI",
pages = "??--??",
year = "1997",
bibdate = "Mon Jan 08 16:33:30 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
ftp://www.hotchips.org/pub/hotc7to11cd/hc97/pdf_images/hc97nav.txt;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Merced (HP/Intel IA-64 prototype code name)",
}
@InProceedings{Zhang:1997:SSA,
author = "Xiaolan Zhang and Zheng Wang and Nicholas Gloy and J.
Bradley Chen and Michael D. Smith",
booktitle = "Proceedings of the sixteenth ACM symposium on
Operating systems principles",
title = "System support for automatic profiling and
optimization",
publisher = pub-ACM,
address = pub-ACM:adr,
year = "1997",
DOI = "https://doi.org/10.1145.266640",
ISSN = "0163-5980 (print), 1943-586X (electronic)",
bibdate = "Fri Jul 27 06:31:50 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/270000/266640/p15-zhang.pdf",
acknowledgement = ack-nhfb,
keywords = "Digital Alpha; IA-64; Morph Editor; SUIF compiler",
}
@Article{Anonymous:1998:HOM,
author = "Anonymous",
title = "{HP} Offers {Merced} Deals. {NetServer} buyers to get
discounts on {IA-64} servers",
journal = j-INFORMATION-WEEK,
volume = "682",
pages = "34--34",
day = "18",
month = may,
year = "1998",
CODEN = "INFWE4",
ISSN = "8750-6874",
bibdate = "Tue Feb 06 18:15:10 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:1998:IPA,
author = "Anonymous",
title = "{IBM} to Port {AIX} to {IA-64}. Vendor says {Unix}
operating system will be ready when chip ships in
2000",
journal = j-INFORMATION-WEEK,
volume = "697",
pages = "24--24",
day = "24",
month = aug,
year = "1998",
CODEN = "INFWE4",
ISSN = "8750-6874",
bibdate = "Tue Feb 06 18:17:25 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:1998:MNM,
author = "Anonymous",
title = "Micro News: {Merced} Update",
journal = j-IEEE-MICRO,
volume = "18",
number = "2",
pages = "2--2",
month = mar # "\slash " # apr,
year = "1998",
CODEN = "IEMIDZ",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Thu Dec 14 06:08:58 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
Science Citation Index database (1980--2000)",
URL = "http://dlib.computer.org/dynaweb/mi/mi1998/@ebt-link;
http://dlib.computer.org/mi/books/mi1998/pdf/m2002.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{August:1998:IPS,
author = "David I. August and Daniel A. Connors and Scott A.
Mahlke and John W. Sias and Kevin M. Crozier and
Ben-Chung Cheng and Patrick R. Eaton and Qudus B.
Olaniran and Wen-mei W. Hwu",
booktitle = "Proceedings of the 25th annual international symposium
on Computer architecture",
title = "Integrated predicated and speculative execution in the
{IMPACT EPIC} architecture",
publisher = pub-IEEE,
address = pub-IEEE:adr,
year = "1998",
DOI = "https://doi.org/10.1145.279391",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Fri Jul 27 06:25:19 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/280000/279391/p227-august.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Bohr:1998:STL,
author = "Mark Bohr",
title = "Silicon trends and limits for advanced
microprocessors",
journal = j-CACM,
volume = "41",
number = "3",
pages = "80--87",
month = mar,
year = "1998",
CODEN = "CACMA2",
DOI = "https://doi.org/10.1145.272327",
ISSN = "0001-0782 (print), 1557-7317 (electronic)",
bibdate = "Thu Jun 4 06:13:01 MDT 1998",
bibsource = "http://www.acm.org/pubs/toc/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/280000/272327/p80-bohr.pdf;
http://www.acm.org:80/pubs/citations/journals/cacm/1998-41-3/p80-bohr/",
acknowledgement = ack-nhfb,
keywords = "design; economics; IA-64; performance",
subject = "{\bf B.7.1} Hardware, INTEGRATED CIRCUITS, Types and
Design Styles, Advanced technologies. {\bf C.5.3}
Computer Systems Organization, COMPUTER SYSTEM
IMPLEMENTATION, Microcomputers, Microprocessors. {\bf
B.8.0} Hardware, PERFORMANCE AND RELIABILITY, General.
{\bf K.1} Computing Milieux, THE COMPUTER INDUSTRY,
Intel.",
}
@InProceedings{Driesen:1998:AIB,
author = "Karel Driesen and Urs H{\"o}lzle",
booktitle = "Proceedings of the 25th annual international symposium
on Computer architecture",
title = "Accurate indirect branch prediction",
publisher = pub-IEEE,
address = pub-IEEE:adr,
year = "1998",
DOI = "https://doi.org/10.1145.279380",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Fri Jul 27 06:37:31 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/280000/279380/p167-driesen.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Dulong:1998:IAW,
author = "Carole Dulong",
title = "The {IA-64} Architecture at Work",
journal = j-COMPUTER,
volume = "31",
number = "7",
pages = "24--32",
month = jul,
year = "1998",
CODEN = "CPTRB4",
ISSN = "0018-9162 (print), 1558-0814 (electronic)",
bibdate = "Tue Jul 7 07:46:32 MDT 1998",
bibsource = "http://www.math.utah.edu/pub/tex/bib/computer1990.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/co/books/co1998/pdf/r7024.pdf;
http://www.computer.org/computer/co1998/r7024abs.htm",
acknowledgement = ack-nhfb,
}
@InProceedings{Fisher:1998:VLI,
author = "Joseph A. Fisher",
editor = "Gurindar Sohi",
booktitle = "25 years of the International Symposia on Computer
Architecture (selected papers), Barcelona, Spain",
title = "Very long instruction word architectures and the
{ELI-512}",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "263--273",
year = "1998",
DOI = "https://doi.org/10.1145/285930.285985",
ISBN = "1-58113-058-9",
ISBN-13 = "978-1-58113-058-4",
LCCN = "QA76.9.A73",
bibdate = "Mon Aug 08 06:22:38 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Reprint of \cite{Fisher:1983:VLI}.",
acknowledgement = ack-nhfb,
}
@Book{Gross:1998:IAP,
author = "Thomas Gross and David R. O'Hallaron",
title = "{iWarp}: anatomy of a parallel computing system",
publisher = pub-MIT,
address = pub-MIT:adr,
pages = "xxiv + 488",
year = "1998",
ISBN = "0-262-07183-5",
ISBN-13 = "978-0-262-07183-3",
LCCN = "QA76.8.I93 G76 1998",
bibdate = "Fri Jul 27 06:36:08 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Halfhill:1998:II,
author = "Tom R. Halfhill",
title = "Inside {IA-64}",
journal = j-BYTE,
volume = "23",
number = "6",
pages = "81--88",
month = jun,
year = "1998",
CODEN = "BYTEDJ",
ISSN = "0360-5280 (print), 1082-7838 (electronic)",
bibdate = "Fri Jul 27 06:25:01 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/byte1995.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "Behind Intel\slash HP's chip for tomorrow are ideas
from yesterday, like long instruction words and
parallel processing.",
acknowledgement = ack-nhfb,
}
@InProceedings{Hwu:1998:RIA,
author = "Wen-mei W. Hwu",
editor = "Gurindar Sohi",
booktitle = "25 years of the International Symposia on Computer
Architecture (selected papers)",
title = "Retrospective: {IMPACT}: an architectural framework
for multiple-instruction issue",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "77--79",
year = "1998",
DOI = "https://doi.org/10.1145.285960",
ISBN = "1-58113-058-9",
ISBN-13 = "978-1-58113-058-4",
LCCN = "QA76.9.A73 S944 1998",
bibdate = "Fri Jul 27 06:29:07 2001",
bibsource = "http://www.acm.org/pubs/contents/proceedings/isca/285930/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/290000/285960/p77-hwu.pdf",
acknowledgement = ack-nhfb,
bookpages = "xiii + 546",
keywords = "IA-64",
}
@Article{Jacobowitz:1998:LE,
author = "Norman M. Jacobowitz and Eric S. Raymond",
title = "{Linux Expo 1998}",
journal = j-LINUX-J,
volume = "52",
pages = "??--??",
month = aug,
year = "1998",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.328474",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Fri Jul 27 06:48:29 2001",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue52/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Krause:1998:UM,
author = "Jason Krause",
title = "{Unixes} for {Merced}",
journal = j-BYTE,
volume = "23",
number = "5",
pages = "25--26",
month = may,
year = "1998",
CODEN = "BYTEDJ",
ISSN = "0360-5280 (print), 1082-7838 (electronic)",
bibdate = "Mon May 11 07:38:50 MDT 1998",
bibsource = "http://www.math.utah.edu/pub/tex/bib/byte1995.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Machanick:1998:HST,
author = "Philip Machanick and Pierre Salverda and Lance Pompe",
title = "Hardware-Software Trade-Offs in a Direct {Rambus}
Implementation of the {RAMpage} Memory Hierarchy",
journal = j-SIGPLAN,
volume = "33",
number = "11",
pages = "105--114",
month = nov,
year = "1998",
CODEN = "SINODQ",
DOI = "https://doi.org/10.1145.291032",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Sat May 1 15:51:26 MDT 1999",
bibsource = "http://www.acm.org/pubs/toc/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/300000/291032/p105-machanick.pdf;
http://www.acm.org:80/pubs/citations/proceedings/asplos/291069/p105-machanick/",
acknowledgement = ack-nhfb,
keywords = "design; IA-64; measurement; performance; theory",
subject = "{\bf B.3.2} Hardware, MEMORY STRUCTURES, Design
Styles. {\bf B.7.1} Hardware, INTEGRATED CIRCUITS,
Types and Design Styles. {\bf C.0} Computer Systems
Organization, GENERAL. {\bf C.4} Computer Systems
Organization, PERFORMANCE OF SYSTEMS.",
}
@Article{Nance:1998:UGM,
author = "Barry Nance",
title = "{Unix} Gears Up for {Merced}. {SCO}'s new {UnixWare}",
journal = j-BYTE,
volume = "23",
number = "5",
pages = "45--45",
month = may,
year = "1998",
CODEN = "BYTEDJ",
ISSN = "0360-5280 (print), 1082-7838 (electronic)",
bibdate = "Mon May 11 07:38:50 MDT 1998",
bibsource = "http://www.math.utah.edu/pub/tex/bib/byte1995.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Pranevich:1998:KKW,
author = "Joseph Pranevich",
title = "Kernel Korner: The Wonderful World of {Linux 2.2}",
journal = j-LINUX-J,
volume = "56",
pages = "46--49",
month = dec,
year = "1998",
CODEN = "LIJOFX",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Nov 19 17:47:27 MST 1998",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue56/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@InProceedings{Qiu:1998:ODA,
author = "Xiaogang Qiu and Michel Dubois",
booktitle = "Proceedings of the 25th annual international symposium
on Computer architecture",
title = "Options for dynamic address translation in {COMAs}",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "214--225",
year = "1998",
DOI = "https://doi.org/10.1145.279390",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Fri Jul 27 06:34:16 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/280000/279390/p214-qiu.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Roelofs:1998:FL,
author = "Greg Roelofs",
title = "The Future of {Linux}",
journal = j-LINUX-J,
volume = "54",
pages = "34--38",
month = oct,
year = "1998",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.327503",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Fri Oct 9 08:35:26 MDT 1998",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue54/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "An informal report on the panel discussion that took
place in July.",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@TechReport{Schlansker:1998:EAI,
author = "Michael S. Schlansker and B. Ramakrishna Rau",
title = "{EPIC}: An Architecture for Instruction-Level Parallel
Processors",
type = "Technical Report",
number = "HPL-99-111",
institution = inst-HP,
address = inst-HP:adr,
year = "1998",
bibdate = "Tue Nov 18 15:10:35 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.hpl.hp.com/techreports/",
acknowledgement = ack-nhfb,
}
@InProceedings{Sibai:1998:HRN,
author = "Fadi N. Sibai",
booktitle = "Proceedings of the 1998 ACM symposium on Applied
Computing",
title = "The hyper-ring network: a cost-efficient topology for
scalable multicomputers",
publisher = pub-ACM,
address = pub-ACM:adr,
year = "1998",
DOI = "https://doi.org/10.1145.330982",
ISBN = "0-89791-969-6",
ISBN-13 = "978-0-89791-969-2",
LCCN = "????",
bibdate = "Sat Aug 04 12:23:55 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/340000/330982/p607-sibai.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64; Merced",
}
@InProceedings{Sibai:1998:PHR,
author = "Fadi N. Sibai",
booktitle = "Proceedings of the 1998 ACM symposium on Applied
Computing",
title = "Performance of the hyper-ring multicomputer",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "598--606",
year = "1998",
DOI = "https://doi.org/10.1145.330979",
ISBN = "0-89791-969-6",
ISBN-13 = "978-0-89791-969-2",
LCCN = "????",
bibdate = "Sat Aug 04 12:23:53 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/340000/330979/p598-sibai.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64; Merced",
}
@Article{Song:1998:DEI,
author = "Peter Song",
title = "Demystifying {EPIC} and {IA-64}",
journal = j-MICROPROC-REP,
volume = "12",
number = "1",
pages = "21--27",
day = "26",
month = jan,
year = "1998",
ISSN = "0899-9341",
bibdate = "Sat Aug 04 12:49:36 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/15740-f00/public/doc/discussions/uniprocessors/ia64/mpr_ia64_demyst_jan98.ps.gz",
acknowledgement = ack-nhfb,
}
@Article{Thompson:1998:JIP,
author = "Carol Thompson",
title = "{Java} on {IA-64} --- {A} peek into the future of
{Java} performance on {Intel}'s {Merced} and beyond",
journal = j-UNIX-REVIEW,
volume = "16",
number = "11",
pages = "41--48",
month = "????",
year = "1998",
CODEN = "UNRED5",
ISSN = "0742-3136",
bibdate = "Tue Feb 06 18:32:54 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@InProceedings{Vishkin:1998:EMT,
author = "Uzi Vishkin and Shlomit Dascal and Efraim Berkovich
and Joseph Nuzman",
booktitle = "SPAA '98: 10th Annual ACM Symposium on Parallel
Algorithms and Architectures, June 28--July 2, 1998,
Puerto Vallarta, Mexico",
title = "Explicit multi-threading ({XMT}) bridging models for
instruction parallelism (extended abstract)",
publisher = pub-ACM,
address = pub-ACM:adr,
year = "1998",
DOI = "https://doi.org/10.1145.277680",
ISBN = "0-89791-989-0",
ISBN-13 = "978-0-89791-989-0",
LCCN = "QA76.58 .A26 1998",
bibdate = "Fri Jul 27 05:37:45 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "ACM order number 417980.",
URL = "http://delivery.acm.org/10.1145/280000/277680/p140-vishkin.pdf",
acknowledgement = ack-nhfb,
bookpages = "viii + 310",
keywords = "IA-64",
}
@Article{Wilkes:1998:SP,
author = "M. V. Wilkes",
title = "A Swing of the Pendulum?",
journal = j-MICROPROC-REP,
volume = "12",
number = "8",
pages = "1--2",
day = "22",
month = jun,
year = "1998",
DOI = "",
ISSN = "0899-9341 (print), 1943-5231 (electronic)",
ISSN-L = "0899-9341",
bibdate = "Tue Sep 10 11:33:04 2024",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
https://www.math.utah.edu/pub/bibnet/authors/w/wilkes-maurice-v.bib",
URL = "https://www.ardent-tool.com/CPU/docs/MPR/19980622/1208vp.pdf",
acknowledgement = ack-nhfb,
author-dates = "Sir Maurice Vincent Wilkes (26 June 1913--29 November
2010)",
fjournal = "Microprocessor Report",
keywords = "Intel/HP Merced (later renamed IA-64 and Itanium)",
remark = "From the article: ``A great triumph of simulation was
to establish beyond any doubt that RISC processors were
faster than existing processors by a factor of
approximately two. However, what really gave RISC its
chance was not its high speed, but its small size. A
RISC processor needed only half as much silicon real
estate as a conventional processor. \ldots{} These two
years [1988--1989] were crucial in enabling the Unix
workstation based on a RISC processor to establish
itself in the market place.''",
RSBM-number = "160",
}
@InProceedings{Yeh:1998:RAI,
author = "Tse-Yu Yeh and Yale N. Patt",
editor = "Gurindar Sohi",
booktitle = "25 years of the International Symposia on Computer
Architecture (selected papers)",
title = "Retrospective: alternative implementations of
two-level adaptive training branch prediction",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "87--88",
year = "1998",
DOI = "https://doi.org/10.1145.285964",
ISBN = "1-58113-058-9",
ISBN-13 = "978-1-58113-058-4",
LCCN = "QA76.9.A73 S944 1998",
bibdate = "Fri Jul 27 06:27:49 2001",
bibsource = "http://www.acm.org/pubs/contents/proceedings/isca/285930/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/290000/285964/p87-yeh.pdf",
acknowledgement = ack-nhfb,
bookpages = "xiii + 546",
keywords = "IA-64",
}
@Misc{AMD:1999:ADN,
author = "{AMD Corporation}",
title = "{AMD} Discloses New Technologies at {Microprocessor
Forum} --- Including x86 64-bit Architecture and
{Lightning Data Transport}$^{{\sc TM}}$",
howpublished = "Press release.",
day = "5",
month = oct,
year = "1999",
bibdate = "Fri May 04 12:45:24 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.amd.com/news/prodpr/99105.html",
acknowledgement = ack-nhfb,
annote = "The x86-64 architecture is definitely not an IA-64
implementation, but rather, an extension of IA-32 by
widening the integer registers to 64-bits. See
\path=http://www1.amd.com/products/cpg/result/1,1265,1144,00.html=,
which says ``Question: Does AMD have any plans to
design an IA-64 compatible processor? Answer: AMD has
no plans to develop an IA-64 compatible processor.''",
keywords = "Lightning Data Transport (LDT); SledHammer; x86-64",
}
@Article{Anonymous:1999:DNI,
author = "Anonymous",
title = "Departments: News: {Itanium}, {Athlon} introduced;
electronic Paper",
journal = j-IEEE-MICRO,
volume = "19",
number = "6",
pages = "2--??",
month = nov # "\slash " # dec,
year = "1999",
CODEN = "IEMIDZ",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:1999:HIC,
author = "Anonymous",
title = "{Hardware --- IA-64-Cluster unter Linux --- {SGI}
demonstriert einen Server-Verbund auf Basis von Intels
Itanium-Chips}",
journal = j-COMPUTERWOCHE,
volume = "26",
number = "48",
pages = "39--40",
year = "1999",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:1999:IAR,
author = "Anonymous",
title = "{IA-64} approaches reality",
journal = "Electronic Business",
volume = "25",
number = "12",
pages = "10--12",
month = "????",
year = "1999",
CODEN = "ELBUDL",
ISSN = "0163-6197",
bibdate = "Tue Feb 06 18:35:07 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:1999:MNI,
author = "Anonymous",
title = "Micro News: {Intel} Unveils {Itanium} Processor",
journal = j-IEEE-MICRO,
volume = "19",
number = "6",
pages = "2--2",
month = nov # "\slash " # dec,
year = "1999",
CODEN = "IEMIDZ",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Thu Dec 14 06:08:58 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
Science Citation Index database (1980--2000)",
URL = "http://dlib.computer.org/mi/books/mi1999/pdf/m6002.pdf",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:1999:SII,
author = "Anonymous",
title = "Special issue on {Intel Architecture 64-bit (IA-64)}
Technology",
journal = j-INTEL-TECH-J,
number = "Q4",
day = "22",
month = nov,
year = "1999",
bibdate = "Fri Jun 01 05:46:56 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q41999.htm",
acknowledgement = ack-nhfb,
annote = "This quarterly journal appears in electronic form
only, with papers in HTML and PDF. There are no volume,
issue, or page numbers, nor CODEN nor ISSN
assignments.",
}
@InProceedings{Bharadwaj:1999:WSP,
author = "J. Bharadwaj and K. Menezes and C. McKinsey",
editor = "{IEEE}",
booktitle = "Proceedings: 32nd Annual International Symposium on
Microarchitecture: Haifa, Israel, November 16--18,
1999",
title = "Wavefront scheduling: path based data representation
and scheduling of subgraphs",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "262--271",
year = "1999",
ISBN = "0-7695-0437-X",
ISBN-13 = "978-0-7695-0437-7",
LCCN = "QA76.6.I5736 1999",
bibdate = "Thu Jul 26 19:02:49 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "IEEE Computer Society order number PR0043.",
URL = "http://ieeexplore.ieee.org/iel5/6577/17552/00809464.pdf",
acknowledgement = ack-nhfb,
bookpages = "xiii + 299",
keywords = "IA-64",
}
@Article{Carver:1999:POS,
author = "Kathy Carver and Chuck Fleckenstein and Joshua
LeVasseur and Stephan Zeisset",
title = "Porting Operating System Kernels to the {IA-64}
Architecture for Pre-silicon Validation Purposes",
journal = j-INTEL-TECH-J,
number = "Q4",
pages = "7",
day = "22",
month = nov,
year = "1999",
ISSN = "1535-766X",
bibdate = "Fri Jun 01 06:02:08 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q41999/articles/art_4.htm;
http://developer.intel.com/technology/itj/q41999/pdf/porting.pdf",
acknowledgement = ack-nhfb,
}
@Article{Cornea-Hasegan:1999:IFP,
author = "Marius Cornea-Hasegan and Bob Norin",
title = "{IA-64} Floating-Point Operations and the {IEEE}
Standard for Binary Floating-Point Arithmetic",
journal = j-INTEL-TECH-J,
number = "Q4",
pages = "16",
day = "22",
month = nov,
year = "1999",
bibdate = "Fri Jun 01 06:02:08 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q41999/articles/art_6.htm;
http://developer.intel.com/technology/itj/q41999/pdf/ia64fpbf.pdf",
acknowledgement = ack-nhfb,
}
@Article{Diefendorff:1999:PFM,
author = "Keith Diefendorff",
title = "{Power4} Focuses on Memory Bandwidth: {IBM} Confronts
{IA-64}, Says {ISA} Not Important",
journal = j-MICROPROC-REP,
volume = "13",
number = "13",
pages = "??--??",
day = "6",
month = oct,
year = "1999",
ISSN = "0899-9341",
bibdate = "Sat Aug 04 13:17:07 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@TechReport{Doran:1999:EFI,
author = "Mark Doran",
title = "{Extensible Firmware Interface}: booting the new
generation of {Intel Architecture} platforms",
type = "Technical report",
institution = pub-INTEL,
address = pub-INTEL:adr,
pages = "45",
day = "1",
month = sep,
year = "1999",
bibdate = "Fri Jan 05 10:58:29 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/IDFEFI.htm",
acknowledgement = ack-nhfb,
}
@TechReport{Doshi:1999:UIA,
author = "Gautam Doshi",
title = "Understanding the {IA-64} Architecture",
type = "Technical report",
institution = pub-INTEL,
address = pub-INTEL:adr,
pages = "65",
day = "31",
month = aug,
year = "1999",
bibdate = "Fri Jan 05 09:43:01 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/idfisa/index.htm",
acknowledgement = ack-nhfb,
}
@Article{Dove:1999:PAI,
author = "Ken Dove",
title = "Programmatic Advantages of {IA-64} For Large Systems",
journal = j-UNIX-REVIEW,
volume = "17",
number = "10",
pages = "34--36",
month = "????",
year = "1999",
CODEN = "UNRED5",
ISSN = "0742-3136",
bibdate = "Tue Feb 06 18:36:51 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Dulong:1999:OII,
author = "Carole Dulong and Rakesh Krishnaiyer and Dattatraya
Kulkarni and Daniel Lavery and Wei Li and John Ng and
David Sehr",
title = "An Overview of the {Intel IA-64} Compiler",
journal = j-INTEL-TECH-J,
number = "Q4",
pages = "15",
day = "22",
month = nov,
year = "1999",
bibdate = "Fri Jun 01 06:02:08 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q41999/articles/art_1.htm;
http://developer.intel.com/technology/itj/q41999/pdf/compiler.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Fang:1999:CTI,
author = "Jesse Fang",
title = "Compiler Technology on {IA-64}",
crossref = "IEEE:1999:HCS",
pages = "??--??",
year = "1999",
bibdate = "Mon Jan 08 17:44:03 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
ftp://www.hotchips.org//pub/hotc7to11cd/hc99/hc11_pdf/hc99nav.txt;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Fleckenstein:1999:POS,
author = "Chuck Fleckenstein and Kathy Carver and Joshua
LeVasseur and Stephan Zeisset",
title = "Porting Operating System Kernels to the {IA-64}
Architecture for Pre-silicon Validation Purposes",
journal = j-INTEL-TECH-J,
number = "Q4",
pages = "7",
day = "22",
month = nov,
year = "1999",
bibdate = "Fri Jun 01 05:38:04 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q41999/articles/art_4.htm;
http://developer.intel.com/technology/itj/q41999/pdf/porting.pdf",
acknowledgement = ack-nhfb,
}
@Article{Fowler:1999:N,
author = "Dennis Fowler",
title = "NetNews",
journal = "netWorker",
volume = "3",
number = "2",
pages = "7--11",
month = jun,
year = "1999",
DOI = "https://doi.org/10.1145.302501",
ISSN = "1091-3556",
bibdate = "Fri Jul 27 06:20:30 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/310000/302501/p7-fowler.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Gwennap:1999:IDN,
author = "Linley Gwennap",
title = "{Intel} Discloses New {IA-64} Features",
journal = j-MICROPROC-REP,
volume = "13",
number = "3",
pages = "16--19",
day = "8",
month = mar,
year = "1999",
ISSN = "0899-9341",
bibdate = "Sat Aug 04 12:55:40 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/15740-f00/public/doc/discussions/uniprocessors/ia64/mpr_ia64_regs_mar99.ps.gz",
acknowledgement = ack-nhfb,
}
@Article{Gwennap:1999:IPI,
author = "Linley Gwennap",
title = "{IA-64}: a parallel instruction set",
journal = j-MICROPROC-REP,
volume = "13",
number = "7",
pages = "1, 6--11",
day = "31",
month = may,
year = "1999",
ISSN = "0899-9341",
bibdate = "Sat Aug 04 12:54:32 2001",
bibsource = "ftp://ftp.ira.uka.de/bibliography/Math/computer.arithmetic.1.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/15740-f00/public/doc/discussions/uniprocessors/ia64/mpr_ia64_isa_may99.ps.gz",
crindex = "Classeur",
location = "http://sSs.inrialpes.fr/cgi-bin/sSs/sommaire?id_sommaire=0899-9341/13/7#1-2",
}
@Article{Gwennap:1999:MSI,
author = "Linley Gwennap",
title = "{Merced} Shows Innovative Design: Static, Dynamic
Elements work in Synergy With Compiler",
journal = j-MICROPROC-REP,
volume = "13",
number = "13",
pages = "1, 6--10",
day = "6",
month = oct,
year = "1999",
ISSN = "0899-9341",
bibdate = "Sat Aug 04 13:07:30 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
crindex = "Classeur",
location = "http://sSs.inrialpes.fr/cgi-bin/sSs/sommaire?id_sommaire=0899-9341/13/13#1-2",
}
@Article{Harrison:1999:CTF,
author = "John Harrison and Ted Kubaska and Shane Story and Ping
Tak Peter Tang",
title = "The Computation of Transcendental Functions on the
{IA-64} Architecture",
journal = j-INTEL-TECH-J,
number = "Q4",
pages = "7",
day = "22",
month = nov,
year = "1999",
bibdate = "Fri Jun 01 06:02:08 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q41999/articles/art_5.htm;
http://developer.intel.com/technology/itj/q41999/pdf/transendental.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Heil:1999:IBP,
author = "Timothy H. Heil and Zak Smith and J. E. Smith",
booktitle = "Proceedings: 32nd Annual International Symposium on
Microarchitecture: Haifa, Israel, November 16--18,
1999",
title = "Improving branch predictors by correlating on data
values",
publisher = pub-IEEE,
address = pub-IEEE:adr,
year = "1999",
DOI = "https://doi.org/10.1145.320086",
ISBN = "0-7695-0437-X",
ISBN-13 = "978-0-7695-0437-7",
LCCN = "QA76.6.I5736 1999",
bibdate = "Fri Jul 27 05:32:15 2001",
bibsource = "http://www.acm.org/pubs/contents/proceedings/micro/320080/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "IEEE Computer Society order number PR00437.",
URL = "http://delivery.acm.org/10.1145/330000/320086/p28-heil.pdf",
acknowledgement = ack-nhfb,
bookpages = "xiii + 299",
keywords = "IA-64",
}
@Book{Intel:1999:IAD,
author = "{Intel Corporation}",
title = "{IA-64} Application Developer's Architecture Guide",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "476",
month = may,
year = "1999",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 08:45:35 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/ADAG.pdf",
acknowledgement = ack-nhfb,
}
@Misc{Jarp:1999:IAD,
author = "Sverre Jarp",
title = "{IA-64} Architecture: {A} Detailed Tutorial",
howpublished = "World-Wide Web slide presentation",
pages = "101",
month = nov,
year = "1999",
bibdate = "Thu Jan 17 10:22:24 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://sverre.home.cern.ch/sverre/IA64_1.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Knies:1999:IAB,
author = "Allan Knies",
title = "{IA-64} Architecture Basics\slash Introduction",
crossref = "IEEE:1999:HCS",
pages = "??--??",
year = "1999",
bibdate = "Mon Jan 08 17:44:03 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
ftp://www.hotchips.org//pub/hotc7to11cd/hc99/hc11_pdf/hc99nav.txt;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@InProceedings{Knies:1999:OTU,
author = "Allan Knies",
title = "Optimization Techniques\slash Using {IA-64} Features",
crossref = "IEEE:1999:HCS",
pages = "??--??",
year = "1999",
bibdate = "Mon Jan 08 17:44:03 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
ftp://www.hotchips.org//pub/hotc7to11cd/hc99/hc11_pdf/hc99nav.txt;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@InProceedings{Knies:1999:TIA,
author = "Allan Knies and Jesse Fang and Wei Li",
title = "Tutorial: {IA64} Architecture and Compilers",
crossref = "IEEE:1999:HCS",
pages = "??--??",
year = "1999",
bibdate = "Mon Jan 08 05:28:04 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
ftp://www.hotchips.org//pub/hotc7to11cd/hc99/hc11_pdf/hc99.t2.s1.IA64tut.txt;
ftp://www.hotchips.org//pub/hotc7to11cd/hc99/hc11_pdf/hc99.t2.s2.IA64tut.txt;
ftp://www.hotchips.org//pub/hotc7to11cd/hc99/hc11_pdf/hc99.t2.s3.IA64tut.txt;
http://www.hotchips.org/hotc11_sunday.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "This tutorial covers an overview of the IA-64
architecture and discusses how an optimizing compiler
can exploit the architecture features. Since dynamic
compilation/dynamic translators are becoming a
mainstream technology, we also provide a brief
introduction to Java and dynamic compilation on
IA-64.\par (1) IA-64 Architecture
Basics/Introduction\\
* Registers * Instructions * Instruction groups *
Predication * Speculation * Branching\par (2)
Optimization Techniques/Using IA-64 Features\\
* Control Speculation * Data Speculation * Predication
* Multi-way branches performance improvements, when to
apply them, and performance considerations ---
conflicts, code size, cache effects, recovery code,
critical path, branch prediction\par (3) Compiler
Technology on IA-64\\
* Software conventions * Optimizations * Backend
Technology If-conversion, Software pipelining, Global
code scheduling, Global register allocation, Machine
model\par (4) Dynamic Compilation Technology on
IA-64\\
* Java software convention * JVM/JIT/GC technology *
Dynamic optimizations for C/C++",
acknowledgement = ack-nhfb,
}
@Article{Kroll:1999:VLW,
author = "Jason Kroll",
title = "{VA Linux} Workstation {VArStation XMP}",
journal = j-LINUX-J,
volume = "67",
pages = "??--??",
month = nov,
year = "1999",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.328049",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 14:31:45 MDT 2000",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue67/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://noframes.linuxjournal.com/lj-issues/issue67/3653.html",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@InProceedings{Larin:1999:CDC,
author = "S. Y. Larin and T. M. Conte",
booktitle = "Proceedings: 32nd Annual International Symposium on
Microarchitecture: Haifa, Israel, November 16--18,
1999",
title = "Compiler-driven cached code compression schemes for
embedded {ILP} processors",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "82--92",
year = "1999",
ISBN = "0-7695-0437-X",
ISBN-13 = "978-0-7695-0437-7",
LCCN = "QA76.6.I5736 1999",
bibdate = "Thu Jul 26 19:04:34 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://ieeexplore.ieee.org/iel5/6577/17552/00809446.pdf",
acknowledgement = ack-nhfb,
bookpages = "xiii + 299",
keywords = "HP PlayDoh; IA-64; TEPIC (TINKER EPIC)",
}
@InProceedings{Launchbury:1999:EMD,
author = "John Launchbury and Jeffrey R. Lewis and Byron Cook",
booktitle = "Proceedings of the ACM SIGPLAN international
conference on functional programming (ICFP '99), Paris,
France, September 27--29, 1999",
title = "On embedding a microarchitectural design language
within {Haskell}",
volume = "34(9)",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "60--69",
month = sep,
year = "1999",
DOI = "https://doi.org/10.1145.317784",
ISBN = "1-58113-111-9",
ISBN-13 = "978-1-58113-111-6",
LCCN = "QA76.7 .A1095 v.34 no.9 1999",
bibdate = "Thu Jul 26 19:19:41 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
series = j-SIGPLAN,
URL = "http://delivery.acm.org/10.1145/320000/317784/p60-launchbury.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Lewis:1999:BCFb,
author = "Ted Lewis",
title = "Binary Critic: Fast, Expensive, and Horribly Complex",
journal = j-COMPUTER,
volume = "32",
number = "9",
pages = "120, 118--119",
month = sep,
year = "1999",
CODEN = "CPTRB4",
ISSN = "0018-9162 (print), 1558-0814 (electronic)",
bibdate = "Tue Sep 7 19:41:32 MDT 1999",
bibsource = "http://www.math.utah.edu/pub/tex/bib/computer1990.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia64/index.htm;
http://dlib.computer.org/co/books/co1999/pdf/r9120.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Merced",
}
@Article{Schlansker:1999:CCB,
author = "Michael Schlansker and Scott Mahlke and Richard
Johnson",
title = "Control {CPR}: {A} Branch Height Reduction
Optimization for {EPIC} Architectures",
journal = j-SIGPLAN,
volume = "34",
number = "5",
pages = "155--168",
month = may,
year = "1999",
CODEN = "SINODQ",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Sat Jan 13 09:39:54 2001",
bibsource = "http://www.acm.org/pubs/contents/proceedings/pldi/301122/index.html;
http://www.acm.org/pubs/contents/proceedings/pldi/301618/index.html;
http://www.cs.rutgers.edu/pldi99/program.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "See PLDI'99 proceedings \cite{ACM:1999:PASa}.",
URL = "http://www.acm.org:80/pubs/citations/proceedings/pldi/301122/p155-schlansker/",
acknowledgement = ack-nhfb,
}
@TechReport{Sharangpani:1999:IIP,
author = "Harsh Sharangpani",
title = "{Intel Itanium} Processor Microarchitecture Overview",
institution = inst-HP,
address = inst-HP:adr,
year = "1999",
bibdate = "Tue Nov 18 15:34:45 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Presented at Microprocessor Forum, October 6--9,
1999.",
acknowledgement = ack-nhfb,
remark = "Cited as \url{microarch_ovw.pdf}, but I cannot find it
on the Web.",
}
@InProceedings{Story:1999:NAI,
author = "S. Story and P. T. P. Tang",
title = "New Algorithms for Improved Transcendental Functions
on {IA-64}",
crossref = "Koren:1999:ISC",
pages = "4--11",
year = "1999",
bibdate = "Mon Feb 7 07:28:26 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://euler.ecs.umass.edu/paper/final/paper-118.pdf;
http://euler.ecs.umass.edu/paper/final/paper-118.ps",
acknowledgement = ack-nhfb,
keywords = "ARITH; computer arithmetic; IEEE",
}
@Article{Tal:1999:ALP,
author = "Ady Tal and Vadim Bassin and Shay Gal-On and Elena
Demikhovsky",
title = "Assembly Language Programming Tools for the {IA-64}
Architecture",
journal = j-INTEL-TECH-J,
number = "Q4",
pages = "10",
day = "22",
month = nov,
year = "1999",
bibdate = "Fri Jun 01 06:02:08 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q41999/articles/art_3.htm;
http://developer.intel.com/technology/itj/q41999/pdf/assemble.pdf",
acknowledgement = ack-nhfb,
}
@Article{Thakkar:1999:ISS,
author = "Shreekant (Ticky) Thakkar and Tom Huff",
title = "The {Internet Streaming SIMD Extensions}",
journal = j-INTEL-TECH-J,
number = "Q2",
pages = "8",
day = "17",
month = may,
year = "1999",
ISSN = "1535-766X",
bibdate = "Fri Jun 01 06:02:08 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q21999/articles/art_1.htm;
http://developer.intel.com/technology/itj/q21999/pdf/simd_ext.pdf",
acknowledgement = ack-nhfb,
keywords = "Itanium; Streaming SIMD Extensions (SSE)",
}
@Article{Uhlig:1999:SPS,
author = "Richard Uhlig and Roman Fishtein and Oren Gershon and
Israel Hirsh and Hong Wang",
title = "{SoftSDV}: {A} Pre-silicon Software Development
Environment for the {IA-64} Architecture",
journal = j-INTEL-TECH-J,
number = "Q4",
pages = "14",
day = "22",
month = nov,
year = "1999",
bibdate = "Fri Jun 01 06:02:08 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q41999/articles/art_2.htm;
http://developer.intel.com/technology/itj/q41999/pdf/softsdv.pdf",
acknowledgement = ack-nhfb,
}
@Article{Wirt:1999:CNS,
author = "Richard Wirt",
title = "The Challenges of New Software for a New
Architecture",
journal = j-INTEL-TECH-J,
day = "22",
month = nov,
year = "1999",
ISSN = "1535-766X",
bibdate = "Tue Nov 18 15:40:22 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
remark = "Cited as \url{foreword.htm}, but where is it?",
}
@Article{Anonymous:19xx:TWI,
author = "Anonymous",
title = "Top Of The Week --- {Intel}'s Next Step --- The
chipmaker's {Itanium} processor could fundamental alter
the cost structure of business computing",
journal = j-INFORMATION-WEEK,
pages = "22--25",
year = "19xx",
CODEN = "INFWE4",
ISSN = "8750-6874",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Aditya:2000:CSM,
author = "Shail Aditya and Scott A. Mahlke and B. Ramakrishna
Rau",
title = "Code size minimization and retargetable assembly for
custom {EPIC} and {VLIW} instruction formats",
journal = j-TODAES,
volume = "5",
number = "4",
pages = "752--773",
month = jan,
year = "2000",
bibdate = "Fri Jul 27 10:05:33 MDT 2001",
bibsource = "http://www.acm.org/pubs/toc/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.acm.org/pubs/articles/journals/todaes/2000-5-4/p752-aditya/p752-aditya.pdf;
http://www.acm.org/pubs/citations/journals/todaes/2000-5-4/p752-aditya/",
abstract = "PICO is a fully automated system for designing the
architecture and the microarchitecture of VLIW and EPIC
processors. A serious concern with this class of
processors, due to their very long instructions, is
their code size. One focus of this paper is to describe
a series of code size minimization techniques used
within PICO, some of which are applied during the
automatic design of the instruction format, while
others are applied during program assembly. The design
of a retargetable assembler to support these techniques
also poses certain novel challenges, which constitute
the second focus of this paper. Contrary to widely held
perceptions, we demonstrate that it is entirely
possible to design VLIW and EPIC processors that are
capable of issuing large numbers of operational per
cycle, but whose code size is only moderately larger
than that for a sequential CISC processor.",
acknowledgement = ack-nhfb,
generalterms = "Design; Experimentation; Measurement",
keywords = "code size minimization; custom templates; design
automation; EPIC; instruction format design; noop
compression; retargetable assembly; VLIW",
subject = "Computer Systems Organization --- Processor
Architectures --- Single Data Stream Architectures
(C.1.1): {\bf RISC/CISC, VLIW architectures}; Software
--- Programming Languages --- Processors (D.3.4): {\bf
Code generation}; Software --- Programming Languages
--- Processors (D.3.4): {\bf Retargetable compilers};
Hardware --- Control Structures and Microprogramming
--- Control Structure Performance Analysis and Design
Aids (B.1.2)",
}
@TechReport{AMD:2000:XTW,
author = "{AMD Corporation}",
title = "x86-64{\TM} Technology White Paper",
institution = "{AMD Corporation}",
address = "One AMD Place, Sunnyvale, CA 94088, USA",
pages = "12",
day = "17",
month = aug,
year = "2000",
bibdate = "Fri May 04 12:53:45 2001",
bibsource = "http://www.amd.com/products/cpg/64bit/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.amd.com/products/cpg/64bit/pdf/x86-64_wp.pdf;
http://www1.amd.com/products/cpg/x8664bit/faq",
acknowledgement = ack-nhfb,
annote = "The x86-64 architecture is definitely not an IA-64
implementation, but rather, an extension of IA-32 by
widening the integer registers to 64-bits.",
}
@Article{Anonymous:2000:CWS,
author = "Anonymous",
title = "{Compaq} will skip {Intel}'s {Itanium} chip for big
servers, and move straight to its successors",
journal = "Computing (London 1980)",
pages = "6--6",
day = "9",
month = mar,
year = "2000",
CODEN = "CPTGB5",
ISSN = "0144-3097",
bibdate = "Tue Feb 06 18:57:46 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2000:FPF,
author = "Anonymous",
title = "Forefront: Product Features: Top {UNIX} Server Employs
64-Way Processor And Prepares For The {IA-64 Itanium
CPU}",
journal = j-ELECTRONIC-DESIGN,
volume = "48",
number = "22",
pages = "62--63",
year = "2000",
CODEN = "ELODAW",
ISSN = "0013-4872",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2000:HPS,
author = "Anonymous",
title = "{Hewlett--Packard setzt auf Linux --- HP forciert die
Portterung des Open-Source-Systems auf Intels Itanium
und PA-Risc-CPUs}. ({German}) [{Hewlett--Packard} sets
up {Linux} --- {HP} forces the porting of open-source
systems to {Intel}'s {Itanium} and {PA-RISC} {CPU}s]",
journal = j-COMPUTERWOCHE,
volume = "27",
number = "2",
pages = "26--26",
month = "????",
year = "2000",
ISSN = "0170-5121",
bibdate = "Tue Feb 06 18:44:37 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
language = "German",
}
@Article{Anonymous:2000:ICL,
author = "Anonymous",
title = "{IA-64-Cluster unter Linux --- SGI demonstriert einen
Server-Verbund auf Basis von Intels Itanium-Chips}.
({German}) [{IA-64} cluster under {Linux} --- {SGI}
demonstrates a server based on {Intel}' {Itanium}
chips]",
journal = j-COMPUTERWOCHE,
volume = "27",
number = "2",
pages = "26--26",
month = "????",
year = "2000",
ISSN = "0170-5121",
bibdate = "Tue Feb 06 18:44:37 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
language = "German",
}
@Article{Anonymous:2000:IPG,
author = "Anonymous",
title = "{Intel} Processor Gets {Linux} Boost. {TurboLinux}
demos software on {Intel}'s forthcoming 64-bit
{Itanium} chips",
journal = j-INFORMATION-WEEK,
volume = "790",
pages = "32--32",
day = "12",
month = jun,
year = "2000",
CODEN = "INFWE4",
ISSN = "8750-6874",
bibdate = "Tue Feb 06 18:48:33 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2000:IRK,
author = "Anonymous",
title = "{IA-64 --- der RISC-Killer? --- Intels Widersacher
haben gute Chancen}. ({German}) [{IA-64} --- the {RISC}
Killer? --- {Intel}'s opponent has good chances]",
journal = j-COMPUTERWOCHE,
volume = "27",
number = "38",
pages = "64--72",
month = "????",
year = "2000",
ISSN = "0170-5121",
bibdate = "Tue Feb 06 18:24:14 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
language = "German",
}
@Article{Anonymous:2000:IVS,
author = "Anonymous",
title = "{Itanium verspatet sich --- Intels 64-Bit-Architektur
kommt fruhestens im vierten Quartal 2000, Rechner erst
2001}. ({German}) [{Itanium} late --- {Intel}'s 64-bit
architecture comes in the fourth quarter of 2000 at the
earliest, the processor in 2001]",
journal = j-COMPUTERWOCHE,
volume = "27",
number = "30",
pages = "4--4",
month = "????",
year = "2000",
ISSN = "0170-5121",
bibdate = "Tue Feb 06 18:44:37 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
language = "German",
}
@Article{Anonymous:2000:LBW,
author = "Anonymous",
title = "{Linux} Beats {Windows} --- Open-source {Trillian
Linux} will be ready for {Intel}'s 64-bit {Itanium}
processors",
journal = "Computer Shopper",
pages = "254--255",
month = jun,
year = "2000",
ISSN = "0886-0556",
bibdate = "Tue Feb 06 18:50:42 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2000:LIS,
author = "Anonymous",
title = "{Linux: Mit IA-64 in den Server-Markt? --- Erfolg
hangt von Anwendungen ab}. ({German}) [{Linux}: With
{IA-64} in the Server Market? --- Success hangs on its
use]",
journal = j-COMPUTERWOCHE,
volume = "27",
number = "38",
pages = "75--78",
month = "????",
year = "2000",
ISSN = "0170-5121",
bibdate = "Tue Feb 06 18:24:14 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
language = "German",
}
@Article{Anonymous:2000:NCF,
author = "Anonymous",
title = "{Neue Chancen f{\"u}r Intel-Server --- Datenbanken
profitieren von IA-64}. ({German}) [New changes for
{Intel} Server --- Databases profit from {IA-64}]",
journal = j-COMPUTERWOCHE,
volume = "27",
number = "38",
pages = "62--63",
month = "????",
year = "2000",
ISSN = "0170-5121",
bibdate = "Tue Feb 06 18:24:14 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
language = "German",
}
@Article{Anonymous:2000:NES,
author = "Anonymous",
title = "New Enterprise Server Choices. {Intel}'s {Itanium}
processor attracts interest as a platform for {Unix}
apps",
journal = j-INFORMATION-WEEK,
volume = "786",
pages = "104--104",
day = "15",
month = may,
year = "2000",
CODEN = "INFWE4",
ISSN = "8750-6874",
bibdate = "Tue Feb 06 18:46:58 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2000:NNI,
author = "Anonymous",
title = "News --- {NEC}'s 16 {Itanium} Processor-Based
Prototype {IA-64} Server Running 64-Bit {SQL} Server on
64-Bit {Windows} Operating System",
journal = j-NEC-RES-DEV,
volume = "41",
number = "1",
pages = "122--122",
month = "????",
year = "2000",
CODEN = "NECRAU",
ISSN = "0048-0436; 0547-051X",
bibdate = "Tue Feb 06 18:30:55 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2000:NPAa,
author = "Anonymous",
title = "New Products: {AVP for Linux\slash FreeBSD UNIX,
Kaspersky Lab Ltd.; API PowerRAC Chassis 320, Alpha
Processor Inc.; ODBC-ODBC Bridge, Easysoft Ltd.;
LinkScan 6.1, Electronic Software Publishing
Corporation; Metro-X Enhanced Server CD, Metro Link,
Inc.; P-STAT Statistical Software, P-STAT, Inc.; System
Manager in a Box v1.0, PegaSoft Canada; PGI Workstation
3.1, PGI; Quick Restore 2.6, Workstation Solutions,
Inc.; Threads.h++ and Tools.h++ Professional, Rogue
Wave Software; Scriptics Connect 1.0, 1.1, Scriptics
Corporation; TapeWare 6.2 Backup Software, Yosemite
Technologies, Inc.; DoubleVision for Linux Systems,
Tridia Corporation}",
journal = j-LINUX-J,
volume = "71",
pages = "??--??",
month = mar,
year = "2000",
CODEN = "LIJOFX",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 07:44:12 MDT 2000",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue71/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Anonymous:2000:NPF,
author = "Anonymous",
title = "New Products: {FileZerver, Microtest, Inc.; AT75C310,
Aplio Inc.; Eyelet GUI, MoJo Designs Inc.; J2SE 1.2.2
for Linux, Sun Microsystems, Inc.; GNUPro Tools for
IA-64, Red Hat Software; Linux edition of ``A Mother's
Shoah'', IL NewMedia Publishing; +One Station, Maxspeed
Corporation; Parallel Computing Toolkit, Wolfram
Research; Rave Systems RackMount-1UAXe, Rave Computer
Association, Inc.; SafeWrite, TurnSafe Technologies,
Inc.; Progress SonicMQ Adds Support for Linux, Progress
Software Corporation; System Blocks, SM\&A Corp.;
T.Rex, Freemont Avenue Software, Inc.; Videomodem, COM
One Services; SNA Gateway, Gcom, Inc.; Best Linux 2000,
SOT Finnish Software Engineering Ltd.}",
journal = j-LINUX-J,
volume = "74",
pages = "??--??",
month = jun,
year = "2000",
CODEN = "LIJOFX",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 07:44:13 MDT 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/linux-journal.bib;
http://noframes.linuxjournal.com/lj-issues/issue74/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2000:SSC,
author = "Anonymous",
title = "Server Status: {Compaq} Refuses {Itanium}",
journal = j-WALL-ST-TECH,
volume = "18",
number = "5",
pages = "16--17",
month = "????",
year = "2000",
CODEN = "WSTEE5",
ISSN = "1060-989X",
bibdate = "Tue Feb 06 18:55:23 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2000:TUS,
author = "Anonymous",
title = "Top {UNIX} Server Employs 64-Way Processor And
Prepares For the {IA-64 Itanium CPU}",
journal = j-ELECTRONIC-DESIGN,
volume = "48",
number = "22",
pages = "62--63",
month = "????",
year = "2000",
CODEN = "ELODAW",
ISSN = "0013-4872",
bibdate = "Tue Feb 06 18:12:58 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Aono:2000:AWI,
author = "Fumio Aono and Masayuki Kimura",
title = "The {AzusA} 16-Way {Itanium} Server",
journal = j-IEEE-MICRO,
volume = "20",
number = "5",
pages = "54--60",
month = sep # "\slash " # oct,
year = "2000",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.877950",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Tue Oct 10 06:00:40 MDT 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m5054.pdf;
http://www.computer.org/micro/mi2000/m5054abs.htm",
acknowledgement = ack-nhfb,
keywords = "NEC Itanium server",
}
@InProceedings{Artigas:2000:ALT,
author = "Pedro V. Artigas and Manish Gupta and Samuel P.
Midkiff and Jos{\'e} E. Moreira",
editor = "{ACM}",
booktitle = "Conference proceedings of the 2000 International
Conference on Supercomputing: Santa Fe, New Mexico, May
8--11, 2000",
title = "Automatic loop transformations and parallelization for
{Java}",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "1--10",
year = "2000",
DOI = "https://doi.org/10.1145.335232",
ISBN = "1-58113-270-0",
ISBN-13 = "978-1-58113-270-0",
LCCN = "????",
bibdate = "Fri Jul 27 06:10:38 2001",
bibsource = "http://www.acm.org/pubs/contents/proceedings/supercomputing/335231/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/340000/335232/p1-artigas.pdf",
acknowledgement = ack-nhfb,
bookpages = "xi + 509",
keywords = "IA-64",
}
@InProceedings{Barroso:2000:PSA,
author = "Luiz Andr{\'e} Barroso and Kourosh Gharachorloo and
Robert McNamara and Andreas Nowatzyk and Shaz Qadeer
and Barton Sano and Scott Smith and Robert Stets and
Ben Verghese",
booktitle = "Proceedings of the 27th Annual International Symposium
on Computer Architecture: June 12--14, 2000, Vancouver,
British Columbia",
title = "{Piranha}: a scalable architecture based on
single-chip multiprocessing",
publisher = pub-ACM,
address = pub-ACM:adr,
year = "2000",
DOI = "https://doi.org/10.1145.339696",
ISBN = "1-58113-232-8",
ISBN-13 = "978-1-58113-232-8",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
LCCN = "QA76.9.A73 S97 2000",
bibdate = "Fri Jul 27 06:02:54 2001",
bibsource = "http://www.acm.org/pubs/contents/proceedings/isca/339647/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/340000/339696/p282-barroso.pdf",
acknowledgement = ack-nhfb,
bookpages = "vi + 328",
keywords = "IA-64",
}
@Article{Bharadwaj:2000:IIC,
author = "Jay Bharadwaj and William Y. Chen and Weihaw Chuang
and Gerolf Hoflehner and Kishore Menezes and Kalyan
Muthukumar and Jim Pierce",
title = "The {Intel IA-64} Compiler Code Generator",
journal = j-IEEE-MICRO,
volume = "20",
number = "5",
pages = "44--53",
month = sep # "\slash " # oct,
year = "2000",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.877949",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Tue Oct 10 06:00:40 MDT 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m5044.pdf;
http://www.computer.org/micro/mi2000/m5044abs.htm",
acknowledgement = ack-nhfb,
}
@Article{Brooks:2000:VBC,
author = "David Brooks and Margaret Martonosi",
title = "Value-based clock gating and operation packing:
dynamic strategies for improving processor power and
performance",
journal = j-TOCS,
volume = "18",
number = "2",
pages = "89--126",
month = may,
year = "2000",
CODEN = "ACSYEC",
ISSN = "0734-2071 (print), 1557-7333 (electronic)",
bibdate = "Tue Sep 26 07:54:31 MDT 2000",
bibsource = "http://www.acm.org/pubs/contents/journals/tocs/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.acm.org/pubs/citations/journals/tocs/2000-18-2/p89-brooks/",
abstract = "The large address space needs of many current
applications have pushed processor designs toward
64-bit word widths. Although full 64-bit addresses and
operations are indeed sometimes needed, arithmetic
operations on much smaller quantities are still more
common. In fact, another instruction set trend has been
the introduction of instructions geared toward subword
operations on 16-bit quantities. For examples, most
major processors now include instruction set support
for multimedia operations allowing parallel execution
of several subword operations in the same ALU. This
article presents our observations demonstrating that
operations on ``narrow-width'' quantities are common
not only in multimedia codes, but also in more general
workloads. In fact, across the SPECint95 benchmarks,
over half the integer operation executions require 16
bits or less. Based on this data, we propose two
hardware mechanisms that dynamically recognize and
capitalize on these narrow-width operations. The first,
power-oriented optimization reduces processor power
consumption by using operand-value-based clock gating
to turn off portions of arithmetic units that will be
unused by narrow-width operations. This optimization
results in a 45\%--60\% reduction in the integer unit's
power consumption for the SPECint95 and MediaBench
benchmark suites. Applying this optimization to
SPECfp95 benchmarks results in slightly smaller power
reductions, but still seems warranted. These reductions
in integer unit power consumption equate to a 5\%--10\%
full-chip power savings. Our second,
performance-oriented optimization improves processor
performance by packing together narrow-width operations
so that they share a single arithmetic unit.
Conceptually similar to a dynamic form of MMX, this
optimization offers speedups of 4.3\%--6.2\% for
SPECint95 and 8.0\%--10.4\% for MediaBench. \par
Overall, these optimizations highlight an increasing
opportunity for value-based optimizations to improve
both power and performance in current
microprocessors.",
acknowledgement = ack-nhfb,
keywords = "IA-64",
subject = "Hardware --- Arithmetic and Logic Structures (B.2);
Computer Systems Organization --- Processor
Architectures --- Single Data Stream Architectures
(C.1.1): {\bf RISC/CISC, VLIW architectures}",
}
@InProceedings{Catthoor:2000:HSC,
author = "Francky Catthoor and Nikil D. Dutt and Christoforos E.
Kozyrakis",
booktitle = "Design, Automation, and Test in Europe Conference and
Exhibition 2000: proceedings, Paris, France, March
27--30, 2000",
title = "How to solve the current memory access and data
transfer bottlenecks at the processor architecture or
at the compiler level",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "426--435",
year = "2000",
DOI = "https://doi.org/10.1145.343813",
ISBN = "1-58113-244-1; 0-7695-0537-6, 0-7695-0538-4
(casebound), 0-7695-0539-2 (microfiche)",
ISBN-13 = "978-1-58113-244-1; 978-0-7695-0537-4,
978-0-7695-0538-1 (casebound), 978-0-7695-0539-8
(microfiche)",
LCCN = "????",
bibdate = "Fri Jul 27 05:09:32 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/350000/343813/p426-catthoor.pdf",
acknowledgement = ack-nhfb,
bookpages = "xxxiv + 770",
keywords = "IA-64",
xxnote = "Check ISBN and booktitle?? UC/Melvyl has IEEE, not
ACM, as publisher. Was it co-published??",
}
@InProceedings{Chou:2000:IPC,
author = "Yuan Chou and John Paul Shen",
booktitle = "The 27th Annual International Symposium on Computer
architecture",
title = "Instruction path coprocessors",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "270--281",
year = "2000",
DOI = "https://doi.org/10.1145.339694",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Fri Jul 27 06:08:30 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/340000/339694/p270-chou.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Cierniak:2000:PJJ,
author = "Micha{\l} Cierniak and Guei-Yuan Lueh and James M.
Stichnoth",
title = "Practicing {JUDO}: {Java} under dynamic
optimizations",
journal = j-SIGPLAN,
volume = "35",
number = "5",
pages = "13--26",
month = may,
year = "2000",
CODEN = "SINODQ",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Tue Nov 7 17:22:50 MST 2000",
bibsource = "http://www.acm.org/pubs/contents/proceedings/series/pldi/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.acm.org/pubs/articles/proceedings/pldi/349299/p13-cierniak/p13-cierniak.pdf;
http://www.acm.org/pubs/citations/proceedings/pldi/349299/p13-cierniak/",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Crawford:2000:GEI,
author = "John H. Crawford",
title = "{Guest Editor}'s Introduction: Introducing the
{Itanium} Processors",
journal = j-IEEE-MICRO,
volume = "20",
number = "5",
pages = "9--11",
month = sep # "\slash " # oct,
year = "2000",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/MM.2000.877946",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Tue Oct 10 06:00:40 MDT 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m5009.pdf;
http://www.computer.org/micro/mi2000/m5009abs.htm",
acknowledgement = ack-nhfb,
}
@Article{Dahlen:2000:SWC,
author = "Eric Dahlen and Jennifer Gustin and Susan Meredith and
Doug Moran",
title = "The {82460GX} Server\slash Workstation Chip Set",
journal = j-IEEE-MICRO,
volume = "20",
number = "6",
pages = "69--75",
month = nov # "\slash " # dec,
year = "2000",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.888705",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Tue Dec 12 15:27:04 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m6069.pdf;
http://www.computer.org/micro/mi2000/m6069abs.htm",
abstract = "This article provides an introduction to the memory,
I/O, and graphics subsystems of Intel's Itanium
processor chip set and discusses several aspects of the
processor bus.",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{deDinechin:2000:CEHa,
author = "Christophe de Dinechin",
title = "{C++} Exception Handling for {IA64}",
crossref = "USENIX:2000:PFW",
pages = "??--??",
year = "2000",
bibdate = "Wed Oct 16 05:17:16 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.usenix.org/publications/library/proceedings/osdi2000/wiess2000/dinechin.html",
acknowledgement = ack-nhfb,
}
@Article{deDinechin:2000:CEHb,
author = "Christophe de Dinechin",
title = "{C++} Exception Handling",
journal = j-IEEE-CONCURR,
volume = "8",
number = "4",
pages = "72--79",
month = oct # "\slash " # dec,
year = "2000",
CODEN = "IECMFX",
DOI = "https://doi.org/10.1109/4434.895109",
ISSN = "1092-3063 (print), 1558-0849 (electronic)",
ISSN-L = "1092-3063",
bibdate = "Tue Jan 16 12:15:42 MST 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/pd/books/pd2000/pdf/p4072.pdf;
http://www.computer.org/concurrency/pd2000/p4072abs.htm",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@TechReport{Demshki:2000:DII,
author = "Michael Demshki and Melvin Benedict and Dong Wei and
Tomm Aldridge",
title = "Designing Interoperability into {IA-64} Systems:
{DIG64} Guidelines",
type = "Technical Report",
institution = pub-INTEL,
address = pub-INTEL:adr,
pages = "56",
year = "2000",
bibdate = "Fri Jan 05 10:53:56 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/idfdIG2/",
acknowledgement = ack-nhfb,
}
@InProceedings{Desai:2000:IPC,
author = "U. Desai and S. Tam and R. Kim. J. Zhang and S. Rusu",
title = "{Itanium} Processor Clock Design",
crossref = "ACM:2000:PIS",
pages = "94--98",
year = "2000",
bibsource = "http://www.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Misc/MPG/ispd00.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
}
@TechReport{Doshi:2000:IPP,
author = "{Intel Corporation}",
title = "{Itanium} Processor Program Update",
type = "Technical report",
institution = pub-INTEL,
address = pub-INTEL:adr,
year = "2000",
bibdate = "Fri Jan 05 09:45:51 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/IDFprogram_progress/",
acknowledgement = ack-nhfb,
}
@InProceedings{Eichenberger:2000:IAA,
author = "Alexandre Eichenberger and Waleed Meleis and Suman
Maradani",
booktitle = "Proceedings of the 33rd annual IEEE\slash ACM
international symposium on Microarchitecture",
title = "An integrated approach to accelerate data and
predicate computations in hyperblocks",
publisher = pub-ACM,
address = pub-ACM:adr,
year = "2000",
DOI = "https://doi.org/10.1145.360140",
ISBN = "1-58113-196-8",
ISBN-13 = "978-1-58113-196-3",
LCCN = "????",
bibdate = "Fri Jul 27 05:52:07 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/370000/360140/p101-eichenberger.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{English:2000:MNIb,
author = "Marie English",
title = "Micro News: {Intel} Releases {Itanium} Guide",
journal = j-IEEE-MICRO,
volume = "20",
number = "3",
pages = "3--3",
month = may # "\slash " # jun,
year = "2000",
CODEN = "IEMIDZ",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Thu Dec 14 06:08:58 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
Science Citation Index database (1980--2000)",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m3003.pdf",
acknowledgement = ack-nhfb,
}
@TechReport{Eranian:2000:LIP,
author = "St{\'e}phane Eranian and David Mosberger",
title = "The {Linux\slash ia64} Project: Kernel Design and
Status Report",
type = "Technical Report",
number = "HPL-2000-85",
institution = inst-HP,
address = inst-HP:adr,
year = "2000",
bibdate = "Tue Nov 18 14:59:00 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.hpl.hp.com/techreports/",
acknowledgement = ack-nhfb,
}
@InProceedings{Faraboschi:2000:LTP,
author = "Paolo Faraboschi and Geoffrey Brown and Joseph A.
Fisher and Giuseppe Desoli and Fred Homewood",
booktitle = "The 27th Annual International Symposium on Computer
architecture 2000",
title = "{Lx}: a technology platform for customizable {VLIW}
embedded processing",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "203--213",
year = "2000",
DOI = "https://doi.org/10.1145.339682",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Thu Jul 26 19:16:48 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
series = j-COMP-ARCH-NEWS,
URL = "http://delivery.acm.org/10.1145/340000/339682/p203-faraboschi.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Flautner:2000:TLP,
author = "Kriszti{\'a}n Flautner and Rich Uhlig and Steve
Reinhardt and Trevor Mudge",
title = "Thread Level Parallelism and Interactive Performance
of Desktop Applications",
journal = j-SIGPLAN,
volume = "35",
number = "11",
pages = "129--138",
month = nov,
year = "2000",
CODEN = "SINODQ",
DOI = "https://doi.org/10.1145.357001",
ISBN = "1-58113-317-0",
ISBN-13 = "978-1-58113-317-2",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
LCCN = "????",
bibdate = "Fri Jul 27 05:55:40 2001",
bibsource = "http://foothill.lcs.mit.edu/asplos2k/program.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/360000/357001/p129-flautner.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Flautner:2000:TLPb,
author = "Kriszti{\'a}n Flautner and Rich Uhlig and Steve
Reinhardt and Trevor Mudge",
title = "Thread Level Parallelism and Interactive Performance
of Desktop Applications",
journal = j-SIGPLAN,
volume = "35",
number = "11",
pages = "129--138",
month = nov,
year = "2000",
CODEN = "SINODQ",
DOI = "https://doi.org/10.1145.357001",
ISBN = "1-58113-317-0",
ISBN-13 = "978-1-58113-317-2",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Sun Dec 14 09:18:19 MST 2003",
bibsource = "http://foothill.lcs.mit.edu/asplos2k/program.html;
http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/360000/357001/p129-flautner.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Geppert:2000:DCT,
author = "L. Geppert",
title = "Devices and circuits [Technology 2000 analysis and
forecast]",
journal = j-IEEE-SPECTRUM,
volume = "37",
number = "1",
pages = "63--69",
month = jan,
year = "2000",
CODEN = "IEESAM",
DOI = "https://doi.org/10.1109/6.815441",
ISSN = "0018-9235 (print), 1939-9340 (electronic)",
ISSN-L = "0018-9235",
bibdate = "Sat Jan 18 12:29:46 2020",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeespectrum2000.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
fjournal = "IEEE Spectrum",
journal-URL = "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
keywords = "Circuits; clock rates; Compaq Alpha 21364; Computer
architecture; electronics industry; Electronics
industry; electronics industry; Error correction codes;
Hardware; high-end computers; IBM Power4 processor
chip; Intel; Itanium; microprocessor architecture;
microprocessor chips; Microprocessors; Parallel
processing; Processor scheduling; technological
forecasting",
}
@InProceedings{Grun:2000:MAC,
author = "Peter Grun and Nikil Dutt and Alex Nicolau",
editor = "{ACM}",
booktitle = "Proceedings 2000: Design Automation Conference, 37th,
Los Angeles Convention Center, Los Angeles, CA, June
5--9, 2000",
title = "Memory aware compilation through accurate timing
extraction",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "316--321",
year = "2000",
DOI = "https://doi.org/10.1145.337428",
ISBN = "1-58113-187-9, 1-58131-897-9, 0-7803-6315-9
(casebound), 0-7803-6316-7 (microfiche)",
ISBN-13 = "978-1-58113-187-1, 978-1-58131-897-5,
978-0-7803-6315-1 (casebound), 978-0-7803-6316-8
(microfiche)",
LCCN = "????",
bibdate = "Fri Jul 27 06:11:59 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "IEEE catalog number 00CH37106. ACM order number
477000.",
URL = "http://delivery.acm.org/10.1145/340000/337428/p316-grun.pdf",
acknowledgement = ack-nhfb,
bookpages = "xxxii + 819",
keywords = "IA-64",
xxnote = "Check ISBN: UC/Melvyl has 1-58131-897-9, which looks
suspicious??",
}
@InProceedings{Grundy:2000:VOI,
author = "Jim Grundy",
title = "Verified Optimizations for the {Intel IA-64}
Architecture",
crossref = "Aagaard:2000:TPH",
pages = "215--232",
year = "2000",
bibdate = "Tue Jan 23 18:48:04 MST 2001",
bibsource = "/u/sy/beebe/tex/bib/dblp/dblp-conf-tphol.bib;
http://dblp.uni-trier.de/db/conf/tphol/tphol2000.html#Grundy00;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
oldlabel = "Grundy00",
XMLdata = "ftp://ftp.informatik.uni-trier.de/pub/users/Ley/bib/records.tar.gz#conf/tphol/Grundy00",
}
@InProceedings{Gschwind:2000:BTA,
author = "Michael Gschwind and Kemal Ebcio{\u{g}}lu and Erik
Altman and Sumedh Sathaye",
booktitle = "Conference proceedings of the 2000 International
Conference on Supercomputing: Santa Fe, New Mexico, May
8--11, 2000 [ICS '00]",
title = "Binary translation and architecture convergence issues
for {IBM System\slash 390}",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "336--347",
year = "2000",
DOI = "https://doi.org/10.1145.335264",
ISBN = "1-58113-270-0",
ISBN-13 = "978-1-58113-270-0",
LCCN = "????",
bibdate = "Fri Jul 27 05:22:06 2001",
bibsource = "http://www.acm.org/pubs/contents/proceedings/supercomputing/335231/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/340000/335264/p336-gschwind.pdf",
acknowledgement = ack-nhfb,
bookpages = "xi + 509",
keywords = "AS/400; ESA/390; IA-64; Java Virtual Machine (JVM);
RS/6000",
}
@Book{Gwennap:2000:III,
author = "Linley Gwennap",
title = "{Intel}'s {Itanium} and {IA-64}: technology and market
forecast",
publisher = "MicroDesign Resources",
address = "Sunnyvale, CA, USA",
pages = "iii + 132",
year = "2000",
ISBN = "1-885330-21-9",
ISBN-13 = "978-1-885330-21-5",
LCCN = "QA76.8.I83 G84 2000",
bibdate = "Wed Mar 13 15:36:48 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Gwennap:2000:LLI,
author = "Linley Gwennap",
title = "{Linley} on {Linux}: {Intel}'s {Itanium} on Launch
Pad",
journal = j-LINUX-J,
volume = "74",
pages = "62--63",
month = jun,
year = "2000",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.349418",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 07:44:13 MDT 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/linux-journal.bib;
http://noframes.linuxjournal.com/lj-issues/issue74/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://noframes.linuxjournal.com/lj-issues/issue74/4019.html",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@InProceedings{Harrison:2000:FVI,
author = "John Harrison",
title = "Formal Verification of {IA-64} Division Algorithms",
crossref = "Aagaard:2000:TPH",
pages = "233--251",
year = "2000",
bibdate = "Tue Jan 23 18:48:10 MST 2001",
bibsource = "/u/sy/beebe/tex/bib/dblp/dblp-conf-tphol.bib;
http://dblp.uni-trier.de/db/conf/tphol/tphol2000.html#Harrison00;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
oldlabel = "Harrison00",
XMLdata = "ftp://ftp.informatik.uni-trier.de/pub/users/Ley/bib/records.tar.gz#conf/tphol/Harrison00",
}
@TechReport{Harrison:2000:HOM,
author = "John Harrison and Ted Kubaska and Bob Norin and Shane
Story and Ping Tak Peter Tang",
title = "Highly Optimized Mathematical Functions for the
{IA-64} Architectures",
type = "Technical report",
number = "245410-002",
institution = "Intel Corporation",
month = apr,
year = "2000",
bibdate = "Sat Jun 02 11:04:28 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "ftp://download.intel.com/design/IA-64/Downloads/libm.pdf",
acknowledgement = ack-nhfb,
}
@Article{Henry:2000:CWW,
author = "Dana S. Henry and Bradley C. Kuszmaul and Gabriel H.
Loh and Rahul Sami",
title = "Circuits for wide-window superscalar processors",
journal = j-COMP-ARCH-NEWS,
volume = "28",
number = "2",
pages = "236--247",
month = "????",
year = "2000",
CODEN = "CANED2",
DOI = "https://doi.org/10.1145.339689",
ISBN = "1-58113-232-8",
ISBN-13 = "978-1-58113-232-8",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
LCCN = "QA76.9.A73 S97 2000",
bibdate = "Fri Jul 27 05:12:15 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Proceedings of the 27th Annual International Symposium
on Computer Architecture: June 12--14, 2000, Vancouver,
British Columbia. ACM order number 415004. IEEE catalog
number RS00201.",
URL = "http://delivery.acm.org/10.1145/340000/339689/p236-henry.pdf",
acknowledgement = ack-nhfb,
bookpages = "vi + 328",
keywords = "IA-64",
}
@Manual{HP:2000:IAD,
title = "{IA-64} Architecture Disclosures",
organization = pub-HP,
address = pub-HP:adr,
pages = "??",
year = "2000",
bibdate = "Tue Jan 09 12:53:32 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ia64.hp.com/infolibrary/whitepapers/ia64_arch_wp.pdf",
acknowledgement = ack-nhfb,
}
@Manual{HP:2000:OIA,
title = "Overview of {IA-64} Architecture",
organization = pub-HP,
address = pub-HP:adr,
pages = "10",
year = "2000",
bibdate = "Tue Jan 09 12:53:32 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "This document is part of the HP-UX 11.x Software
Transition Kit.",
URL = "http://devresource.hp.com/STK/partner/ia64bkgnd.pdf",
acknowledgement = ack-nhfb,
}
@Article{Huck:2000:IIA,
author = "Jerry Huck and Dale Morris and Jonathan Ross and Allan
Knies and Hans Mulder and Rumi Zahir",
title = "Introducing the {IA-64} Architecture",
journal = j-IEEE-MICRO,
volume = "20",
number = "5",
pages = "12--23",
month = sep # "\slash " # oct,
year = "2000",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.877947",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Tue Oct 10 06:00:40 MDT 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m5012.pdf;
http://www.computer.org/micro/mi2000/m5012abs.htm",
acknowledgement = ack-nhfb,
}
@Article{Hughes:2000:PJ,
author = "Phil Hughes",
title = "From the Publisher: {January 2000}",
journal = j-LINUX-J,
volume = "69",
pages = "??--??",
month = jan,
year = "2000",
CODEN = "LIJOFX",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 07:44:11 MDT 2000",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue69/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Hughes:2000:PUL,
author = "Phil Hughes",
title = "From the Publisher: {UnixWare} and {Linux} Get
Hitched",
journal = j-LINUX-J,
volume = "78",
pages = "??--??",
month = oct,
year = "2000",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.364443",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 07:44:14 MDT 2000",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue78/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Misc{IBM:2000:MCC,
author = "{IBM}",
title = "Migrating {C} and {C++} Applications to {AIX 5L} on
{IA-64}",
howpublished = "World-Wide Web document.",
day = "3",
month = oct,
year = "2000",
bibdate = "Sat Mar 09 10:18:30 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www-1.ibm.com/servers/aix/itanium/devtools/migratingcandc++.pdf",
acknowledgement = ack-nhfb,
}
@TechReport{Intel:2000:AIC,
author = "{Intel Corporation}",
title = "The Advantages of {IA-64} for Cache Server Software
Information for Software Developers and {IT} Managers",
type = "Technical report",
institution = pub-INTEL,
address = pub-INTEL:adr,
pages = "5",
year = "2000",
bibdate = "Fri Jan 05 09:38:22 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/ia-64_cache2.htm",
acknowledgement = ack-nhfb,
alttitle = "Cache Tech Brief for {Itanium} Processor Family
Architecture",
}
@TechReport{Intel:2000:DIG,
author = "{Intel Corporation}",
title = "Developer's Interface Guide for {IA-64} Servers",
type = "Technical report",
institution = pub-INTEL,
address = pub-INTEL:adr,
year = "2000",
bibdate = "Fri Jan 05 11:04:27 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "This document is a directory of pointers to white
papers on the DIG-64 (Developer's Interface Guide)
specifications.",
URL = "http://developer.intel.com/design/servers/dev_guides/content/doc_lib/index.htm",
acknowledgement = ack-nhfb,
}
@Book{Intel:2000:IBL,
author = "{Intel Corporation}",
title = "{Itanium}-Based {Linux} Developer's Kit",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "????",
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 09:25:31 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/linux.htm",
acknowledgement = ack-nhfb,
}
@Book{Intel:2000:IIAa,
author = "{Intel Corporation}",
title = "{Intel IA-64} Architecture Software Developer's
Manual: Volume 1: {IA-64} Application Architecture",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "216",
month = jan,
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 08:45:35 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/245317.htm",
acknowledgement = ack-nhfb,
}
@Book{Intel:2000:IIAb,
author = "{Intel Corporation}",
title = "{Intel IA-64} Architecture Software Developer's
Manual: Volume 2: {IA-64} System Architecture",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "536",
month = jan,
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 08:45:35 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/245318.htm",
acknowledgement = ack-nhfb,
}
@Book{Intel:2000:IIAc,
author = "{Intel Corporation}",
title = "{Intel IA-64} Architecture Software Developer's
Manual: Volume 3: Instruction Set Reference",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "926",
month = jan,
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 08:45:35 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/245319.htm",
acknowledgement = ack-nhfb,
}
@Book{Intel:2000:IIAd,
author = "{Intel Corporation}",
title = "{Intel IA-64} Architecture Software Developer's
Manual: Volume 4: {Itanium} Processor Programmer's
Guide",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "76",
month = jan,
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 08:45:35 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/245320.htm",
acknowledgement = ack-nhfb,
}
@TechReport{Intel:2000:IIP,
author = "{Intel Corporation}",
title = "{Intel Itanium} Processor: High Performance On
Security Algorithms ({RSA} Decryption Kernel)",
institution = pub-INTEL,
address = pub-INTEL:adr,
pages = "8",
year = "2000",
bibdate = "Fri Jan 05 09:27:38 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/itaniumssl_seg_103.htm",
acknowledgement = ack-nhfb,
}
@Manual{Intel:2000:IPF,
title = "{Itanium} Processor Floating-point Software Assistance
and Floating-point Exception Handling",
number = "245415-001",
organization = pub-INTEL,
address = pub-INTEL:adr,
month = jan,
year = "2000",
bibdate = "Tue Nov 18 16:18:52 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cache-www.intel.com/cd/00/00/21/92/219290_fpswa_software.pdf",
acknowledgement = ack-nhfb,
}
@Book{Intel:2000:IPMa,
author = "{Intel Corporation}",
title = "{Itanium} Processor Microarchitecture Reference for
Software Optimization",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "32",
month = mar,
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 08:45:35 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/245473.htm",
acknowledgement = ack-nhfb,
}
@Book{Intel:2000:IPMb,
author = "{Intel Corporation}",
title = "{Itanium} Processor Microarchitecture Reference for
Software Optimization",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "34",
month = aug,
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 09:23:17 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/245474.htm",
acknowledgement = ack-nhfb,
}
@Book{Intel:2000:ISAa,
author = "{Intel Corporation}",
title = "{IA-64 System Abstraction Layer (SAL)} Specification",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "120",
month = jul,
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Fri Jan 05 10:50:32 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/downloads/24535902.htm",
acknowledgement = ack-nhfb,
}
@TechReport{Intel:2000:ISAb,
author = "{Intel Corporation}",
title = "The {IA-64} System Architecture: Tutorial for
Hardware, {OS}, and Application Developers",
type = "Technical report",
institution = pub-INTEL,
address = pub-INTEL:adr,
year = "2000",
bibdate = "Fri Jan 05 09:35:44 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/design/ia-64/archSysSoftware/",
acknowledgement = ack-nhfb,
}
@Article{Krishnaiyer:2000:AOI,
author = "Rakesh Krishnaiyer and Dattatraya Kulkarni and Daniel
Lavery and Wei Li and Chu-cheow Lim and John Ng and
David Sehr",
title = "An Advanced Optimizer for the {IA-64} Architecture",
journal = j-IEEE-MICRO,
volume = "20",
number = "6",
pages = "60--68",
month = nov # "\slash " # dec,
year = "2000",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.888704",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Thu Dec 14 05:20:47 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m6060.pdf;
http://www.computer.org/micro/mi2000/m6060abs.htm",
abstract = "Predication and large register files and control and
data speculation and an advanced branch architecture
all help IA-64 to enable more aggressive compiler
optimizations.",
acknowledgement = ack-nhfb,
}
@Article{Kroll:2000:NOS,
author = "Jason Kroll",
title = "{Netwinder} Office Server",
journal = j-LINUX-J,
volume = "72",
pages = "??--??",
month = apr,
year = "2000",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.348502",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 07:44:12 MDT 2000",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue72/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Kroll:2000:RCA,
author = "Jason Kroll",
title = "1999 Readers' Choice Awards: You voted, we counted ---
here are the results",
journal = j-LINUX-J,
volume = "69",
pages = "??--??",
month = jan,
year = "2000",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.328160",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Fri Jul 27 06:14:29 2001",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue69/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Lehrbaum:2000:ESNa,
author = "Rick Lehrbaum",
title = "Embedded Systems News Briefs",
journal = j-LINUX-J,
volume = "71",
pages = "??--??",
month = mar,
year = "2000",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.348533",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 07:44:12 MDT 2000",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue71/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Lehrbaum:2000:ESNc,
author = "Rick Lehrbaum",
title = "Embedded Systems News Briefs",
journal = j-LINUX-J,
volume = "73",
pages = "??--??",
month = may,
year = "2000",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.349123",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Thu Sep 21 07:44:12 MDT 2000",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue73/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Lucco:2000:SSD,
author = "Steven Lucco",
title = "Split-stream dictionary program compression",
journal = j-SIGPLAN,
volume = "35",
number = "5",
pages = "27--34",
month = may,
year = "2000",
CODEN = "SINODQ",
DOI = "https://doi.org/10.1145.349307",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Tue Nov 7 17:22:50 MST 2000",
bibsource = "http://www.acm.org/pubs/contents/proceedings/series/pldi/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/350000/349307/p27-lucco.pdf;
http://www.acm.org/pubs/articles/proceedings/pldi/349299/p27-lucco/p27-lucco.pdf;
http://www.acm.org/pubs/citations/proceedings/pldi/349299/p27-lucco/",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Book{Markstein:2000:IEF,
author = "Peter Markstein",
title = "{IA-64} and Elementary Functions: Speed and
Precision",
publisher = pub-PH,
address = pub-PH:adr,
pages = "xix + 298",
year = "2000",
ISBN = "0-13-018348-2",
ISBN-13 = "978-0-13-018348-4",
LCCN = "QA76.9.A73 M365 2000",
bibdate = "Fri Jan 5 08:00:52 MST 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/elefunt.bib;
http://www.math.utah.edu/pub/tex/bib/fparith.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
http://www.math.utah.edu/pub/tex/bib/master.bib;
http://www.math.utah.edu/pub/tex/bib/microchip.bib;
University of California MELVYL catalog.",
series = "Hewlett--Packard professional books",
URL = "http://www.markstein.org/",
acknowledgement = ack-nhfb,
keywords = "IA-64 (computer architecture)",
remark = "Besides recipes for accurate computation of elementary
functions, this book also contains algorithms for the
correctly-rounded computation of floating-point
division and square-root, and of integer division,
starting from low-precision reciprocal approximations.
There is also a wealth of information on the tradeoffs
between integer and floating-point instruction use in a
pipelined parallel architecture.",
tableofcontents = "IA-64 Architecture \\
New Architecture Objectives \\
VLIW \\
Memory Enhancements \\
Software Pipelining \\
Floating Point Enhancements \\
Summary \\
IA-64 Instructions And Registers \\
Instructions \\
Register Sets \\
Accessing Memory \\
Assembly Language \\
Problems \\
Increasing Instruction Level Parallelism \\
Branching \\
Speculation \\
Problems \\
Floating Point Architecture \\
Floating Point Status Register \\
Precision \\
Fused Multiply-Add \\
Division and Square Root Assists \\
Floating Comparisons \\
Communication between Floating Point and General
Purpose Registers \\
Fixed Point Multiplication \\
SIMD Arithmetic \\
Problems \\
Programming For IA-64 \\
Compiler Options \\
Pragmas \\
Floating Point Data Types \\
In-Line Assembly \\
The fenv.h Header \\
Extended Examples \\
Quad Precision \\
Problems \\
Computation of Elementary Functions \\
Mathematical Preliminaries \\
Floating Point \\
Approximation and Error Analysis \\
The Exclusion Theorem \\
Ulps \\
Problems \\
Approximation Of Functions \\
Taylor Series \\
Lagrangian Interpolation \\
Chebychev Approximation \\
Remez Approximation \\
Practical Considerations \\
Function Evaluation \\
Table Construction \\
Problems \\
Division \\
Approximations for the Reciprocal \\
Computing the Quotient \\
Division Using Only Final Precision Results \\
Fast Variants of Division \\
Remainder \\
Integer Division \\
An Implementation of Division \\
Problems \\
Square Root \\
Approximations \\
Rounding the Square Root \\
Computing the Square Root \\
Calculating the Reciprocal Square Root \\
An Implementation of Square Root \\
Problems \\
Exponential Functions \\
Definitions and Formulas \\
Argument Reduction \\
Error Containment \\
Computing the Exponential \\
The Function expm \\
Problems \\
Logarithmic Functions \\
General Relations \\
Argument Reductions \\
Error Analysis \\
The Function log1p \\
Computing the Logarithm \\
Problems \\
The Power Function \\
Definition \\
Single Precision \\
Double Precision \\
Double-Extended Precision \\
Quad Precision \\
Computing the Power Function \\
Problems \\
Trigonometric Functions \\
Formulas and Identities \\
Argument Reduction \\
Error Analysis \\
Computing the Trigonometric Functions \\
Problems \\
Inverse Sine And Cosine \\
Definitions and Formulas \\
Argument Reduction \\
Error Analysis \\
Computing the arcsin \\
Problems \\
Inverse Tangent Functions \\
Definitions and Formulas \\
Argument Reduction \\
Error Analysis \\
Computing the arctan \\
Problems \\
Hyperbolic Functions \\
Definitions and Formulas \\
Argument Reduction \\
Error Analysis \\
Computing the Hyperbolic Functions \\
Problems \\
Inverse Hyperbolic Functions \\
Definitions and Formulas. arcsinh. arccosh. arctanh \\
Problems \\
Odds And Ends \\
Correctly Rounded Functions \\
Monotonicity \\
Alternative Algorithms \\
Testing \\
New Architectural Directions \\
Problems \\
In-Line Assembly \\
Solutions To Problems \\
Bibliography \\
Subject Index",
}
@InProceedings{McInerney:2000:MRI,
author = "R. McInerney and K. Leeper and T. Hill and H. Chan and
B. Basaran and L. McQuiddy",
title = "Methodology for Repeater Insertion Management in the
{RTL}, Layout Floorplan and Fullchip Timing Databases
of the {Itanium} Microprocessor",
crossref = "ACM:2000:PIS",
pages = "99--104",
year = "2000",
bibsource = "http://www.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Misc/MPG/ispd00.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
}
@Article{Quach:2000:HAR,
author = "Nhon Quach",
title = "High-Availability and Reliability in the {Itanium}
Processor",
journal = j-IEEE-MICRO,
volume = "20",
number = "5",
pages = "61--69",
month = sep # "\slash " # oct,
year = "2000",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.877951",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Tue Oct 10 06:00:40 MDT 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m5061.pdf;
http://www.computer.org/micro/mi2000/m5061abs.htm",
acknowledgement = ack-nhfb,
}
@InProceedings{Quach:2000:IPF,
author = "Nhon Quach",
title = "The {Itanium} Processor Features for High Availability
and Reliability",
crossref = "IEEE:2000:HCS",
pages = "??--??",
year = "2000",
bibdate = "Mon Jan 08 05:28:04 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
ftp://www.hotchips.org/pub/hotc12cd/hotchips-pdf/itanium-features.PDF;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
pagecount = "18",
}
@InProceedings{Rusu:2000:CGD,
author = "S. Rusu and S. Tam",
editor = "John H. Wuorinen",
booktitle = "Digest of technical papers: 2000 IEEE International
Solid-State Circuits Conference, San Francisco Marriott
Hotel, 7--9 February 2000",
title = "Clock generation and distribution for the first
{IA-64} microprocessor",
volume = "43",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "176--177",
year = "2000",
ISBN = "0-7803-5853-8",
ISBN-13 = "978-0-7803-5853-9",
ISSN = "0193-6530",
LCCN = "TK7870 .I58 2000",
bibdate = "Thu Jul 26 18:57:39 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "IEEE catalog number 00CH37056.",
URL = "http://ieeexplore.ieee.org/iel5/6780/18154/00839738.pdf",
acknowledgement = ack-nhfb,
bookpages = "496",
keywords = "IA-64",
}
@Article{Rusu:2000:FIM,
author = "S. Rusu and G. Singer",
title = "The First {IA-64} Microprocessor",
journal = j-IEEE-J-SOLID-STATE-CIRCUITS,
volume = "35",
number = "11",
pages = "1539--1544",
month = "????",
year = "2000",
CODEN = "IJSCBC",
DOI = "https://doi.org/10.1109/4.881197",
ISSN = "0018-9200 (print), 1558-173X (electronic)",
bibdate = "Tue Feb 06 18:11:35 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@InProceedings{Samaras:2000:IPC,
author = "Bill Samaras",
title = "The {Itanium} Processor Cartridge",
crossref = "IEEE:2000:HCS",
pages = "??--??",
year = "2000",
bibdate = "Mon Jan 08 05:28:04 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
ftp://www.hotchips.org/pub/hotc12cd/hotchips-pdf/itanium-cartridge.PDF;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
pagecount = "29",
}
@TechReport{Schlansker:2000:AHL,
author = "Michael S. Schlansker and B. Ramakrishna Rau and Scott
Mahlke and Vinod Kathail and Richard Johnson and Sadun
Anik and Santosh G. Abraham",
title = "Achieving High Levels of Instruction-Level Parallelism
with Reduced Hardware Complexity",
type = "Technical Report",
number = "HPL-96-120",
institution = inst-HP,
address = inst-HP:adr,
year = "2000",
bibdate = "Tue Nov 18 15:11:52 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.hpl.hp.com/techreports/",
acknowledgement = ack-nhfb,
}
@Article{Schlansker:2000:EEP,
author = "Michael S. Schlansker and B. Ramakrishna Rau Cover",
title = "{EPIC}: Explicitly Parallel Instruction Computing",
journal = j-COMPUTER,
volume = "33",
number = "2",
pages = "37--45",
month = feb,
year = "2000",
CODEN = "CPTRB4",
ISSN = "0018-9162 (print), 1558-0814 (electronic)",
bibdate = "Mon Oct 30 19:18:20 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/computer2000.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/co/books/co2000/pdf/r2037.pdf;
http://www.computer.org/computer/co2000/r2037abs.htm",
acknowledgement = ack-nhfb,
keywords = "HP/Intel IA-64",
}
@InProceedings{Sharangpani:2000:IIP,
author = "Harsh Sharangpani",
title = "{Intel Itanium} Processor Core",
crossref = "IEEE:2000:HCS",
pages = "??--??",
year = "2000",
bibdate = "Mon Jan 08 05:28:04 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
ftp://www.hotchips.org/pub/hotc12cd/hotchips-pdf/itanium-core.pdf;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
pagecount = "15",
}
@InProceedings{Sharangpani:2000:IPC,
author = "Harsh Sharangpani",
title = "The {Itanium} Processor Core",
crossref = "IEEE:2000:HCS",
pages = "??--??",
year = "2000",
bibdate = "Mon Jan 08 05:28:04 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Runner-up for best presentation award.",
acknowledgement = ack-nhfb,
}
@Article{Sharangpani:2000:IPM,
author = "Harsh Sharangpani and Ken Arora",
title = "{Itanium} Processor Microarchitecture",
journal = j-IEEE-MICRO,
volume = "20",
number = "5",
pages = "24--43",
month = sep # "\slash " # oct,
year = "2000",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.877948",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Tue Oct 10 06:00:40 MDT 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m5024.pdf;
http://www.computer.org/micro/mi2000/m5024abs.htm",
acknowledgement = ack-nhfb,
}
@InProceedings{Sias:2000:AEP,
author = "John W. Sias and Wen-mei W. Hwu and David I. August",
booktitle = "Proceedings of the 33rd annual IEEE\slash ACM
international symposium on Microarchitecture December
2000",
title = "Accurate and efficient predicate analysis with binary
decision diagrams",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "112--123",
year = "2000",
DOI = "https://doi.org/10.1145.360141",
ISBN = "1-58113-196-8",
ISBN-13 = "978-1-58113-196-3",
LCCN = "????",
bibdate = "Thu Jul 26 19:13:49 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/370000/360141/p112-sias.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@InProceedings{Singer:2000:FIM,
author = "G. Singer and S. Rusu",
editor = "John H. Wuorinen",
booktitle = "Digest of technical papers: 2000 IEEE International
Solid-State Circuits Conference, San Francisco Marriott
Hotel, 7--9 February 2000",
title = "The first {IA-64} microprocessor: a design for
highly-parallel execution",
volume = "43",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "422--423",
year = "2000",
ISBN = "0-7803-5853-8",
ISBN-13 = "978-0-7803-5853-9",
ISSN = "0193-6530",
LCCN = "TK7870 .I58 2000",
bibdate = "Thu Jul 26 18:59:45 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "IEEE catalog number 00CH37056.",
URL = "http://ieeexplore.ieee.org/iel5/6780/18154/00839843.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Smith:2000:OCF,
author = "Michael D. Smith",
title = "Overcoming the Challenges to Feedback-Directed
Optimization",
journal = j-SIGPLAN,
volume = "35",
number = "7",
pages = "1--11",
month = jul,
year = "2000",
CODEN = "SINODQ",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Tue Nov 7 17:22:50 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@InProceedings{Swartzlander:2000:SPI,
author = "Earl E. {Swartzlander, Jr.} and Graham A. Jullien and
Michael J. Schulte",
editor = "Earl E. {Swartzlander, Jr.} and Graham A. Jullien and
Michael J. Schulte",
booktitle = "IEEE International Conference on Application-Specific
Systems, Architectures and Processors: proceedings,
July 10--12, 2000; Boston, Massachusetts",
title = "Subword permutation instructions for two-dimensional
multimedia processing in {MicroSIMD} architectures",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "3--14",
year = "2000",
ISBN = "0-7695-0716-6",
ISBN-13 = "978-0-7695-0716-3",
LCCN = "TK7874.6.I572 2000",
bibdate = "Thu Jul 26 18:53:18 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://ieeexplore.ieee.org/iel5/6949/18693/00862373.pdf",
acknowledgement = ack-nhfb,
bookpages = "xiv + 358 (or xiv + 360??)",
keywords = "IA-64; Mix; PA-RISC MAX-2",
}
@Article{Tam:2000:CGD,
author = "S. Tam and S. Rusu and U. N. Desai and R. Kim and J.
Zhang and I. Young",
title = "Clock Generation and Distribution for the First
{IA-64} Microprocessor",
journal = j-IEEE-J-SOLID-STATE-CIRCUITS,
volume = "35",
number = "11",
pages = "1545--1552",
month = nov,
year = "2000",
CODEN = "IJSCBC",
DOI = "https://doi.org/10.1109/4.881198",
ISSN = "0018-9200 (print), 1558-173X (electronic)",
bibdate = "Fri Mar 22 09:18:22 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Book{Triebel:2000:IAS,
author = "Walter Triebel",
title = "{Itanium} architecture for software developers",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "xxxv + 308",
year = "2000",
ISBN = "0-9702846-4-0",
ISBN-13 = "978-0-9702846-4-8",
LCCN = "????",
bibdate = "Wed Mar 13 15:45:26 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
xxtitle = "{IA-64} Architecture for Software Developers",
}
@InProceedings{Worley:2000:AFP,
author = "John Worley and Bill Worley and Tom Christian and
Christopher Worley",
title = "{AES} Finalists on {PA-RISC} and {IA-64}:
Implementations {\&} Performance",
crossref = "NIST:2000:TAE",
pages = "57--74",
year = "2000",
bibdate = "Tue Jan 23 13:29:28 MST 2001",
bibsource = "http://www.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Theory/qc.bib;
http://dblp.uni-trier.de/db/conf/aes/aes2000.html#WorleyWCW00;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
oldlabel = "WorleyWCW00",
XMLdata = "ftp://ftp.informatik.uni-trier.de/pub/users/Ley/bib/records.tar.gz#conf/aes/WorleyWCW00",
}
@InProceedings{Wu:2000:CRL,
author = "Youfeng Wu and Yong-fong Lee",
title = "Comprehensive Redundant Load Elimination for the
{IA-64} Architecture",
crossref = "Carter:2000:LCP",
pages = "53--69",
year = "2000",
bibdate = "Wed Jan 24 04:47:59 MST 2001",
bibsource = "/u/sy/beebe/tex/bib/dblp/dblp-conf-lcpc.bib;
http://dblp.uni-trier.de/db/conf/lcpc/lcpc1999.html#WuL99;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
oldlabel = "WuL99",
XMLdata = "ftp://ftp.informatik.uni-trier.de/pub/users/Ley/bib/records.tar.gz#conf/lcpc/WuL99",
}
@Article{Yi:2000:TLR,
author = "Qing Yi and Vikram Adve and Ken Kennedy",
title = "Transforming loops to recursion for multi-level memory
hierarchies",
journal = j-SIGPLAN,
volume = "35",
number = "5",
pages = "169--181",
month = may,
year = "2000",
CODEN = "SINODQ",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Tue Nov 7 17:22:50 MST 2000",
bibsource = "http://www.acm.org/pubs/contents/proceedings/series/pldi/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.acm.org/pubs/articles/proceedings/pldi/349299/p169-yi/p169-yi.pdf;
http://www.acm.org/pubs/citations/proceedings/pldi/349299/p169-yi/",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Zahir:2000:CCDa,
author = "Rumi Zahir and Jonathan Ross and Dale Morris and Drew
Hess",
title = "{OS} and compiler considerations in the design of the
{IA-64} architecture",
journal = j-COMP-ARCH-NEWS,
volume = "28",
number = "5",
pages = "212--221",
month = dec,
year = "2000",
CODEN = "CANED2",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Fri May 12 09:41:22 MDT 2006",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Co-published in {\em Operating Systems Review}, ({\bf
34})(5).",
acknowledgement = ack-nhfb,
}
@Article{Zahir:2000:CCDb,
author = "Rumi Zahir and Jonathan Ross and Dale Morris and Drew
hess",
title = "{OS} and Compiler Considerations in the Design of the
{IA-64} Architecture",
journal = j-SIGPLAN,
volume = "35",
number = "11",
pages = "212--221",
month = nov,
year = "2000",
CODEN = "SINODQ",
ISBN = "1-58113-317-0",
ISBN-13 = "978-1-58113-317-2",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Tue Nov 7 16:57:37 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/sigplan2000.bib;
http://foothill.lcs.mit.edu/asplos2k/program.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Zahir:2000:SHIa,
author = "Rumi Zahir and Jonathan Ross and Dale Morris and Drew
Hess",
title = "Support for High {ILP} processors --- {OS} and
Compiler Considerations in the Design of the {IA-64}
Architecture",
journal = j-OPER-SYS-REV,
volume = "34",
number = "5",
pages = "212--221",
month = "????",
year = "2000",
CODEN = "OSRED8",
ISSN = "0163-5980 (print), 1943-586X (electronic)",
bibdate = "Tue Feb 06 18:03:47 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Zahir:2000:SHIb,
author = "Rumi Zahir and Jonathan Ross and Dale Morris and Drew
Hess",
title = "Support for High {ILP} processors --- {OS} and
Compiler Considerations in the Design of the {IA-64}
Architecture",
journal = j-COMP-ARCH-NEWS,
volume = "28",
number = "5",
pages = "212--221",
month = "????",
year = "2000",
CODEN = "CANED2",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Tue Feb 06 18:03:47 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Zheng:2000:PRI,
author = "Cindy Zheng and Carol Thompson",
title = "{PA-RISC} to {IA-64}: Transparent Execution, No
Recompilation",
journal = j-COMPUTER,
volume = "33",
number = "3",
pages = "47--52",
month = mar,
year = "2000",
CODEN = "CPTRB4",
ISSN = "0018-9162 (print), 1558-0814 (electronic)",
bibdate = "Mon Oct 30 19:18:20 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/computer2000.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/co/books/co2000/pdf/r3047.pdf;
http://www.computer.org/computer/co2000/r3047abs.htm",
acknowledgement = ack-nhfb,
keywords = "Hewlett--Packard's Aries dynamic translator",
}
@Manual{AMD:2001:PIA,
title = "Preliminary Information: {AMD} 64-Bit Technology: The
{AMD} x86-64{\TM} Architecture Programmers Overview",
organization = "{AMD Corporation}",
address = "One AMD Place, Sunnyvale, CA 94088, USA",
pages = "134",
month = jan,
year = "2001",
bibdate = "Fri May 04 12:53:45 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.amd.com/products/cpg/64bit/pdf/x86-64_overview.pdf",
acknowledgement = ack-nhfb,
annote = "The x86-64 architecture is definitely not an IA-64
implementation, but rather, an extension of IA-32 by
widening the integer registers to 64-bits.",
}
@Article{Anonymous:2001:BSI,
author = "Anonymous",
title = "{Bea setzt auf den Itanium --- Die neue
Intel-Plattform soll eine Alternative fur Weblogic auf
Risc-Systemen bieten}",
journal = j-COMPUTERWOCHE,
volume = "28",
number = "32",
pages = "17--17",
year = "2001",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:BTL,
author = "Anonymous",
title = "64-bit Technology: At long last {Intel}'s {Itanium}
processor has arrived to herald a mass-market future
for 64-bit technology",
journal = "Personal computer world",
volume = "24",
number = "2",
pages = "144--148",
month = "????",
year = "2001",
CODEN = "PCWODU",
ISSN = "0142-0232",
bibdate = "Tue Feb 06 18:56:28 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:DNI,
author = "Anonymous",
title = "Departments: News: {Intel} Introduces {Itanium}.
Tender Offer Extended Again. Show Us Your Stuff. Center
Spotlights {STEP}. Use Benchmark to Compare Hardware.
Image of the Month. {SIGGRAPH} Celebrates Play",
journal = j-COMPUT-AIDED-ENG,
volume = "20",
number = "7",
pages = "10--??",
year = "2001",
CODEN = "CCAEDJ",
ISSN = "0733-3536",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:ESL,
author = "Anonymous",
title = "{Express: Supercomputer auf Linux-Basis:
3300-Itanium-Prozessoren fur neuen Weltrekordrechner}",
journal = j-ELECTRONIK,
volume = "50",
number = "18",
pages = "10--11",
year = "2001",
CODEN = "EKRKAR",
ISSN = "0013-5658",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:ESW,
author = "Anonymous",
title = "{Epic soll den Weg ebnen --- Mit der
Explicitly-Parallel-Instruction-Computing-(Epic-)
Architektur will Intel punkten. Eine breite Allianz von
Hardware- und Softwareherstellern soll den Itanium ins
Highend katapultieren}",
journal = j-COMPUTERWOCHE,
volume = "28",
number = "49",
pages = "45--45",
year = "2001",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:FLI,
author = "Anonymous",
title = "First Looks: The {Itanium} and 64-Bit Computing",
journal = "PC magazine: the independent guide to IBM-standard
personal computing",
volume = "20",
number = "16",
pages = "28--33",
year = "2001",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:FNI,
author = "Anonymous",
title = "Forefront: News: {Itanium} Processors Will Gang Up To
Perform 13.6 Teraflops",
journal = j-ELECTRONIC-DESIGN,
volume = "49",
number = "19",
pages = "36--37",
year = "2001",
CODEN = "ELODAW",
ISSN = "0013-4872",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:HIB,
author = "Anonymous",
title = "{Herausforderer Itanium --- Um in der 64-Bit-Welt
erfolgreich zu sein, reicht der Chip allein nicht aus.
Auch Compiler, Betriebssysteme und Applikationen mussen
speziell angepasst werden}",
journal = j-COMPUTERWOCHE,
volume = "28",
number = "49",
pages = "42--44",
year = "2001",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:IAP,
author = "Anonymous",
title = "{Itanium ante portas --- Am 29. Mai kommen die
64-Bit-CPUs in Stuckzahlen auf den Markt}",
journal = j-COMPUTERWOCHE,
volume = "28",
number = "20",
pages = "6--6",
year = "2001",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:ICS,
author = "Anonymous",
title = "{Intel} call on the software industry to drum up
interest in {Itanium}",
journal = "Computing",
volume = "16",
number = "9",
pages = "6--??",
year = "2001",
bibdate = "Fri Mar 22 10:22:21 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:IEJ,
author = "Anonymous",
title = "{Itanium ab Ende Juni --- Nach sieben Jahren
Entwicklung und mit zwei Jahren Verspatung ist es nun
soweit: Intel feiert leise das Prozessor-Debut seiner
IA-64-Architektur}",
journal = j-COMPUTERWOCHE,
volume = "28",
number = "23",
pages = "30--30",
year = "2001",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:IES,
author = "Anonymous",
title = "{Itanium-Entwicklung stockt}",
journal = j-COMPUTERWOCHE,
volume = "28",
number = "11",
pages = "48--51",
year = "2001",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:IIW,
author = "Anonymous",
title = "{IBM Itanium} workstation",
journal = "Personal computer world",
volume = "16",
number = "9",
pages = "62--63",
year = "2001",
bibdate = "Fri Mar 22 10:22:21 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:ILI,
author = "Anonymous",
title = "{Intel} Launches {Itanium}",
journal = j-LIB-SYSTEMS,
volume = "21",
number = "7",
pages = "3--??",
year = "2001",
ISSN = "0277-0288",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:IWI,
author = "Anonymous",
title = "{Mit dem Itanium will Intel in der
High-end-Server-Arena Fuss fassen. Nach dem Ruckzug von
Compaq und HP bleiben Sun und IBM als Konkurrenten}",
journal = j-COMPUTERWOCHE,
volume = "28",
number = "30",
pages = "16--17",
year = "2001",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:LMI,
author = "Anonymous",
title = "{Linux} Not Mentioned in {Itanium} Article",
journal = j-LIB-SYSTEMS,
volume = "21",
number = "9",
pages = "6--??",
year = "2001",
ISSN = "0277-0288",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:NEI,
author = "Anonymous",
title = "{Notizen --- Einblick: Itanium --- ein ``heisser'' Tip
fur Server?}",
journal = j-ELECTRONIK,
volume = "50",
number = "19",
pages = "28--29",
year = "2001",
CODEN = "EKRKAR",
ISSN = "0013-5658",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:NES,
author = "Anonymous",
title = "New Enterprise Server Choices: {Intel}'s {Itanium}
processor attracts interest as a platform for {Unix}
apps",
journal = j-INFORMATION-WEEK,
volume = "21",
number = "1",
pages = "104--110",
year = "2001",
CODEN = "INFWE4",
ISSN = "8750-6874",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:NNP,
author = "Anonymous",
title = "News: {NEC} Provided 16-Way {Itanium} Server
``{AzusA}'' for {Hewlett--Packard} as an {OEM}
Products",
journal = j-NEC-RES-DEV,
volume = "42",
number = "1",
pages = "91--91",
year = "2001",
CODEN = "NECRAU",
ISSN = "0048-0436; 0547-051X",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:NPP,
author = "Anonymous",
title = "New Products: {PowerEdge} Adopts {Intel Itanium}
Processors. {cA} Blocks Malicious Code",
journal = "Network magazine: the competitive edge in business
technology",
volume = "16",
number = "9",
pages = "80--81",
year = "2001",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:PIM,
author = "Anonymous",
title = "Pipeline: {Intel}'s {McKinley} chip shows its face.
{A} sea creature boosts optical networking. {CEO} pay
and worker pay are diverging. {AOL}, {EarthLink} helped
{FBI} find terrorists",
journal = "PC Magazine",
volume = "20",
number = "18",
pages = "29--29",
month = "????",
year = "2001",
bibdate = "Fri Mar 22 11:02:46 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:SRS,
author = "Anonymous",
title = "{Steckt Risc in der Sackgasse? --- Der Wettbewerb wird
harter. Leistungssteigerungen mussen die Risc-Anbieter
teuer erkaufen. Deshalb hat sich Compaq zur Aufgabe der
Alpha-Architektur und zum Umstieg auf Itanium
entschieden}",
journal = j-COMPUTERWOCHE,
volume = "28",
number = "49",
pages = "8--13",
year = "2001",
ISSN = "0170-5121",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:SSC,
author = "Anonymous",
title = "Server Status: {Compaq} Refuses {Itanium}",
journal = j-WALL-ST-TECH,
volume = "16",
number = "9",
pages = "16--17",
year = "2001",
CODEN = "WSTEE5",
ISSN = "1060-989X",
bibdate = "Fri Mar 22 10:22:21 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:TAA,
author = "Anonymous",
title = "Tech Analyzer: {AMD} Wields 64-Bit Hammer: Chipmaker's
new {Hammer CPU} is likely to cost less and offer
better backward compatibility than {Intel}'s {Itanium}
processor",
journal = j-INFORMATION-WEEK,
volume = "28",
number = "23",
pages = "64--68",
year = "2001",
CODEN = "INFWE4",
ISSN = "8750-6874",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:TLL,
author = "Anonymous",
title = "64bit Technology: At long last {Intel}'s {Itanium}
processor has arrived to herald a mass-market future
for 64bit technology",
journal = "Personal computer world",
volume = "16",
number = "9",
pages = "144--148",
year = "2001",
bibdate = "Fri Mar 22 10:22:21 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Anonymous:2001:WSM,
author = "Anonymous",
title = "A {Windows} for Supercomputing: {Microsoft} is quietly
launching an {OS} to handle {Intel}'s new, 64-bit
{Itanium CPU}",
journal = "PC world",
volume = "19",
number = "8",
pages = "58--65",
year = "2001",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Blau:2001:NAE,
author = "J. Blau and S. Barlas and V. Singh and L. Geppert and
H. Goldstein and S. K. Moore and M. J. Riezenman and S.
Miller",
title = "News analysis: (1) {Europe}'s Cellulars To Share
Infrastructure? (2) {Why} the Fuss About {3G}? (3)
{Senate} Changes Will Shake Telecom, Defense {R\&D},
{Energy}. (4) {In} {Energy}, Will {Bingaman}
Out-{Cheney} {Cheney}? (5) {India}'s Power Grid Finds
Helping Hand. (6) {The} {Itanium} Platform Lands Its
First Computing Systems. (7) {Ion} Beam Keeps Liquid
Crystals in Line. (8) {How} to Raise {UV} Nanolasers.
(9) {Swedish} Start-Up Puts New Spin on Pen and Paper.
(10) {Big} Welcome for {MIT}'s {Web}-Based Courseware",
journal = j-IEEE-SPECTRUM,
volume = "38",
number = "7",
pages = "20--37",
month = jul,
year = "2001",
CODEN = "IEESAM",
DOI = "https://doi.org/10.1109/MSPEC.2001.8827233",
ISSN = "0018-9235 (print), 1939-9340 (electronic)",
ISSN-L = "0018-9235",
bibdate = "Sat Jan 18 12:29:46 2020",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeespectrum2000.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
fjournal = "IEEE Spectrum",
journal-URL = "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
}
@Book{Chandrakasan:2001:DHP,
author = "Anantha Chandrakasan and William J. Bowhill and Frank
Fox",
title = "Design of high-performance microprocessor circuits",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "xx + 557",
year = "2001",
ISBN = "0-7803-6001-X",
ISBN-13 = "978-0-7803-6001-3",
LCCN = "TK7895.M5 D47 2001",
bibdate = "Fri Mar 22 09:23:06 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "IEEE order no. PC5836.",
price = "US\$125.00",
URL = "http://shop.ieee.org/store/product.asp?prodno=PC5836",
acknowledgement = ack-nhfb,
}
@Article{Charney:2001:UJO,
author = "Reginald Charney and Don Marti and Gary A.
Messenbrink",
title = "{upFRONT}: Job Opening Trends; The Kernel Speaks; Win
on Lin on Thin; {LJ} Index --- {March 2001}; {Linux}
Bytes Other Markets: {Bay Area Rapid Transit (BART)}:
Under Control with {Linux}; Stop the Presses: {Kylix}
Clix with {CLX}",
journal = j-LINUX-J,
volume = "84",
pages = "8, 10, 12, 14",
month = apr,
year = "2001",
CODEN = "LIJOFX",
DOI = "https://doi.org/10.1145.374662",
ISSN = "1075-3583 (print), 1938-3827 (electronic)",
bibdate = "Fri Jul 27 06:55:59 2001",
bibsource = "http://noframes.linuxjournal.com/lj-issues/issue84/index.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@InProceedings{Doshi:2001:OSD,
author = "G. Doshi and R. Krishnaiyer and K. Muthukumar",
editor = "{IEEE}",
booktitle = "2001 International Conference on Parallel
Architectures and Compilation Techniques: proceedings:
8--12 September, 2001, Barcelona, Catalunya, Spain",
title = "Optimizing software data prefetches with rotating
registers",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "x + 305",
year = "2001",
ISBN = "0-7695-1363-8",
ISBN-13 = "978-0-7695-1363-8",
LCCN = "QA76.58.I553 2001",
bibdate = "Mon Feb 25 15:10:51 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://ieeexplore.ieee.org/lpdocs/epic03/",
acknowledgement = ack-nhfb,
}
@Article{Dulong:2001:MCI,
author = "Carole Dulong and Priti Shrivastav and Azita Refah",
title = "The Making of a Compiler for the {Intel\reg{} Itanium}
Processor",
journal = j-INTEL-TECH-J,
number = "Q3",
pages = "7",
day = "1",
month = aug,
year = "2001",
ISSN = "1535-766X",
bibdate = "Tue Mar 05 10:59:15 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://developer.intel.com/technology/itj/q32001/articles/art_4.htm;
http://developer.intel.com/technology/itj/q32001/pdf/art_4.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Engels:2001:PPS,
author = "Daniel W. Engels and Jon Feldman and David R. Karger
and Matthias Ruhl",
booktitle = "Twelfth Annual Symposium on Discrete algorithms",
title = "Parallel processor scheduling with delay constraints",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "577--585",
year = "2001",
DOI = "https://doi.org/10.1145.365538",
ISBN = "0-89871-490-7",
ISBN-13 = "978-0-89871-490-6",
LCCN = "????",
bibdate = "Thu Jul 26 19:24:11 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/370000/365538/p577-engels.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Geppert:2001:SIP,
author = "Linda Geppert",
title = "Semiconductors: The {Itanium} Platform Lands Its First
Computing Systems",
journal = j-IEEE-SPECTRUM,
volume = "38",
number = "7",
pages = "28--29",
month = jul,
year = "2001",
CODEN = "IEESAM",
ISSN = "0018-9235 (print), 1939-9340 (electronic)",
ISSN-L = "0018-9235",
bibdate = "Thu Jul 26 18:37:21 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://sphinx4.ieee.org/spectrum/jul01/departments/nitan.html;
http://sphinx4.ieee.org/spectrum/jul01/pdfs/departments/news0701.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@InProceedings{Greer:2001:SCI,
author = "Bruce Greer and John Harrison and Greg Henry and Wei
Li and Peter Tang",
title = "Scientific Computing on the {Itanium\TM{}} Processor",
crossref = "ACM:2001:SHP",
pages = "??--??",
year = "2001",
bibdate = "Sat Feb 10 14:28:55 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.sc2001.org/papers/pap.pap266.pdf",
acknowledgement = ack-nhfb,
pagecount = "8",
}
@Misc{Hammond:2001:NGI,
author = "Gary Hammond and Sam Naffziger",
title = "Next Generation {Itanium\TM} Processor Overview",
howpublished = "World-Wide Web slide presentation",
day = "27--30",
month = aug,
year = "2001",
bibdate = "Fri Mar 22 09:12:18 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/McK-IDF-2001.pdf",
acknowledgement = ack-nhfb,
}
@Manual{HP:2001:HFV,
title = "{HP Fortran v2.5} for the {Itanium} Processor Family
Release Note",
organization = "Hewlett--Packard Company",
address = "Palo Alto, CA, USA",
pages = "22",
year = "2001",
bibdate = "Sat Jun 25 11:42:43 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Manufacturing Part Number: 5969-7863 0601.",
URL = "http://docs.hp.com/en/5969-7863/5969-7863.pdf",
acknowledgement = ack-nhfb,
}
@Article{Hudson:2001:CRG,
author = "Richard L. Hudson and J. Eliot B. Moss and Sreenivas
Subramoney and Weldon Washburn",
title = "Cycles to Recycle: Garbage Collection on the {IA-64}",
journal = j-SIGPLAN,
volume = "36",
number = "1",
pages = "101--110",
month = jan,
year = "2001",
CODEN = "SINODQ",
DOI = "https://doi.org/10.1145.362470",
ISBN = "1-58113-263-8",
ISBN-13 = "978-1-58113-263-2",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Fri Jul 27 06:57:44 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "ACM SIGPLAN International Symposium on Memory
Management (ISMM'00)",
}
@Article{Jarp:2001:OIP,
author = "Sverre Jarp",
title = "Optimizing {IA-64} Performance",
journal = j-DDJ,
volume = "26",
number = "7",
pages = "21--22, 24, 26",
month = jul,
year = "2001",
CODEN = "DDJOEB",
ISSN = "1044-789X",
bibdate = "Thu Jun 7 06:07:17 MDT 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ddj.com/ftp/2001/2001_07/ia64.txt;
http://www.ddj.com/ftp/2001/2001_07/ia64.zip",
abstract = "The IA-64, also known as Itanium, is a 64-bit
processor designed by Hewlett--Packard and Intel that
supports performance-enhancing techniques such as
predication, speculation, rotating registers, and the
like. It also sports a new kind of instruction set
based on the Explicit Parallel Instruction Computing
(EPIC) specification. Additional resources include
ia64.txt (listings) and ia64.zip (source code).",
acknowledgement = ack-nhfb,
}
@Article{Kastner:2001:IBI,
author = "Daniel K{\"a}stner and Sebastian Winkel",
title = "{ILP}-based Instruction Scheduling for {IA-64}",
journal = j-SIGPLAN,
volume = "36",
number = "8",
pages = "145--154",
month = aug,
year = "2001",
CODEN = "SINODQ",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Sun Dec 14 09:18:29 MST 2003",
bibsource = "http://portal.acm.org/;
http://redwood.snu.ac.kr/lctes2001/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
remark = "LCTES'01: The Workshop on Languages, Compilers and
Tools for Embedded Systems",
}
@Article{Kennai:2001:WAI,
author = "E. Kennai and H. Kawashima and Hagiwara and Y. and
others",
title = "{Windows OS} and Applications for {Itanium}",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "48--51",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Kimura:2001:MSI,
author = "K. Kimura and K. Naitoh and K. Hirata and others",
title = "Middle Software on {Itanium}",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "56--59",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Kobayashi:2001:RSI,
author = "K. Kobayashi",
title = "Remarks for Special Issue on {Itanium}-based Server
and Workstation Products",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "1--2",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Kondo:2001:OIS,
author = "T. Kondo and Y. Ito",
title = "Overview of {Itanium} 16way Server ``{AzusA}''",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "13--14",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Kreinovich:2001:INB,
author = "Vladik Kreinovich",
title = "{Itanium}'s New Basic Operation of Fused Multiply-Add:
Theoretical Explanation and Theoretical Challenge",
journal = j-SIGACT,
volume = "32",
number = "1",
pages = "115--117",
year = "2001",
bibdate = "Sat Dec 06 15:20:39 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.cs.utep.edu/vladik/2000/tr00-42.pdf;
http://www.cs.utep.edu/vladik/2000/tr00-42.ps.gz",
acknowledgement = ack-nhfb,
issue = "118",
}
@Article{Krewell:2001:IRI,
author = "Kevin Krewell",
title = "{Intel} Raises the {Itanium}: First {IA-64} Processor
Released at {733MHz} and {800MHz}",
journal = j-MICROPROC-REP,
volume = "??",
number = "??",
pages = "??--??",
day = "11",
month = jun,
year = "2001",
ISSN = "0899-9341",
bibdate = "Sat Aug 04 15:08:04 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.mdronline.com/mpr/h/2001/0611/152401.html",
acknowledgement = ack-nhfb,
}
@TechReport{Li:2001:CIA,
author = "Wei Li",
title = "Compiling for {Itanium} Architecture: Triumphs and
Challenges",
institution = inst-HP,
address = inst-HP:adr,
year = "2001",
bibdate = "Tue Nov 18 15:30:46 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://systems.cs.colorado.edu/EPIC1/",
acknowledgement = ack-nhfb,
}
@TechReport{Li:2001:LLF,
author = "Ren-Cang Li and Peter Markstein and Jon P. Okada and
James W. Thomas",
title = "The {\tt libm} library and floating-point arithmetic
for {HP-UX} on {Itanium}",
type = "Technical report",
institution = inst-HP,
address = inst-HP:adr,
pages = "??",
month = apr,
year = "2001",
bibdate = "Fri Jun 24 20:12:09 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://h21007.www2.hp.com/dspp/ddl/ddl_Download_File_TRX/1,1249,942,00.pdf;
http://h21007.www2.hp.com/dspp/tech/tech_TechDocumentDetailPage_IDX/1,1701,981,00.html",
acknowledgement = ack-nhfb,
}
@InProceedings{Manson:2001:CSM,
author = "Jeremy Manson and William Pugh",
booktitle = "ISCOPE Conference on ACM 2001 Java Grande",
title = "Core semantics of multithreaded {Java}",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "29--38",
year = "2001",
CODEN = "NECGEZ",
DOI = "https://doi.org/10.1145.376806",
ISBN = "1-58113-359-6",
ISBN-13 = "978-1-58113-359-2",
ISSN = "0285-4139",
LCCN = "????",
bibdate = "Fri Jul 27 05:42:33 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/380000/376806/p29-manson.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Article{Mikayama:2001:ISR,
author = "S. Mikayama and I. Sugasaki and Y. Nishikawa and
others",
title = "{Itanium} 16way Server {RAS} Firmware",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "29--32",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Nishioka:2001:AOS,
author = "H. Nishioka and Y. Taya and M. Nishikayama and
others",
title = "Automatic Operation System of {Itanium} 16way Server",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "33--36",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Partel:2001:DHU,
author = "M. Partel and D. Olander and M. Yoder and others",
title = "Development of {HP-UX} for {Itanium} Processor
Family",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "44--47",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Paul:2001:IIC,
author = "L. G. Paul",
title = "{Intel}'s {Itanium} Chip Positions New Workstations to
Rival {Unix} Machines",
journal = "Managing automation",
volume = "16",
number = "9",
pages = "50--55",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:21 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Samaras:2001:IIP,
author = "William A. Samaras and Naveen Cherukuri and Srinivas
Venkataraman",
title = "The {IA-64 Itanium} Processor Cartridge",
journal = j-IEEE-MICRO,
volume = "21",
number = "1",
pages = "82--89",
month = jan # "\slash " # feb,
year = "2001",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.903064",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Wed Feb 14 07:53:17 MST 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2001/pdf/m1082.pdf;
http://www.computer.org/micro/mi2001/m1082abs.htm",
acknowledgement = ack-nhfb,
}
@Article{Samaras:2001:SFI,
author = "William A. Samaras and Naveen Cherukuri and Srinivas
Venkataraman",
title = "Special Feature: The {IA-64 Itanium} Processor
Cartridge: For high-performance computing in a
multiprocessing system environment, consider this
innovative packaging solution",
journal = j-IEEE-MICRO,
volume = "21",
number = "1",
pages = "82--89",
month = jan # "\slash " # feb,
year = "2001",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/40.903064",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@InProceedings{Scott:2001:SFB,
author = "D. Scott",
title = "Sixty-four bit architecture and the {Itanium}
processor",
crossref = "Kraemer:2001:SCV",
pages = "20--??",
year = "2001",
bibdate = "Sat Dec 06 15:52:42 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Senta:2001:ISS,
author = "T. Senta and M. Yamamori and F. Aono and others",
title = "{Itanium} 16way Server System Architecture",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "25--28",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Shibata:2001:SIL,
author = "T. Shibata and S. Sakon and J. Nomura and others",
title = "Software for {IA-64 Linux} on {Express5800\slash 1000
Series}",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "52--55",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:52:49 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC",
acknowledgement = ack-nhfb,
}
@Article{Shibuya:2001:ISH,
author = "T. Shibuya and I. Uehara and M. Kimura and others",
title = "{Itanium} 16way Server Hardware",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "15--18",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Shimizu:2001:SMC,
author = "Kanna Shimizu and David L. Dill and Ching-Tsun Chou",
title = "A Specification Methodology by a Collection of Compact
Properties as Applied to the {Intel{\reg} Itanium{\TM}}
Processor Bus Protocol",
journal = j-LECT-NOTES-COMP-SCI,
volume = "2144",
pages = "340--??",
year = "2001",
CODEN = "LNCSD9",
ISSN = "0302-9743 (print), 1611-3349 (electronic)",
bibdate = "Sat Feb 2 13:05:47 MST 2002",
bibsource = "http://link.springer-ny.com/link/service/series/0558/tocs/t2144.htm;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://link.springer-ny.com/link/service/series/0558/bibs/2144/21440340.htm;
http://link.springer-ny.com/link/service/series/0558/papers/2144/21440340.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Sylvester:2001:FPC,
author = "Dennis Sylvester and Himanshu Kaul",
booktitle = "Proceedings of the 38th Conference on Design
Automation Conference",
title = "Future performance challenges in nanometer design",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "3--8",
year = "2001",
ISBN = "1-58113-297-2",
ISBN-13 = "978-1-58113-297-7",
LCCN = "????",
bibdate = "Fri Jul 27 05:34:36 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/380000/378245/p3-sylvester.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@Book{Triebel:2001:PIB,
author = "Walter Triebel and Joseph D. Bissell and Rick Booth",
title = "Programming {Itanium}-based systems: Developing High
Performance Applications for Intel's New Architecture",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "xvi + 360",
year = "2001",
ISBN = "0-9702846-2-4",
ISBN-13 = "978-0-9702846-2-4",
LCCN = "????",
bibdate = "Wed Mar 13 15:45:55 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Tsukakoshi:2001:OIT,
author = "M. Tsukakoshi",
title = "Outline of {Itanium} Technical Server",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "9--10",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Umeki:2001:ISH,
author = "T. Umeki and O. Suwa and A. Kobayashi and others",
title = "{Itanium} 4way Server Hardware",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "37--39",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@Article{Umesato:2001:HTI,
author = "S. Umesato and S. Mano and T. Takagi and others",
title = "Hardware Technology for {Itanium} 16way Server",
journal = j-NEC-TECH-J,
volume = "54",
number = "10",
pages = "19--24",
year = "2001",
CODEN = "NECGEZ",
ISSN = "0285-4139",
bibdate = "Fri Mar 22 10:22:20 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
OCLC Article1st database",
acknowledgement = ack-nhfb,
}
@InProceedings{Velev:2001:EUB,
author = "Miroslav N. Velev and Randal E. Bryant",
booktitle = "Proceedings of the 38th Conference on Design
Automation Conference 2001",
title = "Effective use of boolean satisfiability procedures in
the formal verification of superscalar and {VLIW}",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "226--231",
year = "2001",
ISBN = "1-58113-297-2",
ISBN-13 = "978-1-58113-297-7",
LCCN = "????",
bibdate = "Thu Jul 26 19:21:09 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://delivery.acm.org/10.1145/380000/378469/p226-velev.pdf",
acknowledgement = ack-nhfb,
keywords = "IA-64",
}
@InProceedings{Wang:2001:RRS,
author = "P. H. Wang and Hong Wang and R. M. Kling and K.
Ramakrishnan and J. P. Shen",
editor = "{IEEE}",
booktitle = "HPCA: the seventh International Symposium on
High-Performance Computer Architecture: proceedings,
19--24 January 2001, Monterrey, Nuevo Leon, Mexico",
title = "Register renaming and scheduling for dynamic execution
of predicated code",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "15--25",
year = "2001",
ISBN = "0-7695-1019-1",
ISBN-13 = "978-0-7695-1019-4",
LCCN = "QA76.9.A73 I566 2001",
bibdate = "Thu Jul 26 18:45:59 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
bookpages = "xvi + 318",
keywords = "IA-64",
}
@Article{Allan:2002:TRS,
author = "Alan Allan and Don Edenfeld and William H. {Joyner,
Jr.} and Andrew B. Kahng and Mike Rodgers and Yervant
Zorian",
title = "2001 Technology Roadmap for Semiconductors",
journal = j-COMPUTER,
volume = "35",
number = "1",
pages = "42--53",
month = jan,
year = "2002",
CODEN = "CPTRB4",
ISSN = "0018-9162 (print), 1558-0814 (electronic)",
bibdate = "Fri Feb 8 07:11:47 MST 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/co/books/co2002/pdf/r1042.pdf;
http://www.computer.org/computer/co2002/r1042abs.htm;
http://www.intel.com/technology/silicon/alanallanieeecomputer0102.htm",
acknowledgement = ack-nhfb,
keywords = "IA-64; Itanium",
}
@InProceedings{Anderson:2002:CCS,
author = "Ferd E. Anderson and J. Steve Wells and Eugene Z.
Berta",
title = "The Core Clock System on the Next Generation
{Itanium\TM} Microprocessor",
crossref = "IEEE:2002:IIS",
pages = "??--??",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/isscc_2002/isscc_2002_6.shtml",
acknowledgement = ack-nhfb,
}
@TechReport{Anonymous:2002:ASI,
author = "Anonymous",
title = "From {AlphaServer} Systems to the {Intel Itanium}
Architecture a Bright Future for {OpenVMS} System
Management",
type = "White paper",
institution = inst-HP,
address = inst-HP:adr,
year = "2002",
bibdate = "Tue Nov 18 15:24:42 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://sysdoc.doors.ch/HP/OpenVMS_Itanium_system_management.pdf",
acknowledgement = ack-nhfb,
}
@TechReport{Anonymous:2002:III,
author = "Anonymous",
title = "Inside the {Intel Itanium 2} Processor",
type = "White paper",
institution = inst-HP,
address = inst-HP:adr,
month = jul,
year = "2002",
bibdate = "Tue Nov 18 15:17:27 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.dig64.org/about/Itanium2_white_paper_public.pdf",
acknowledgement = ack-nhfb,
}
@TechReport{Anonymous:2002:OAI,
author = "Anonymous",
title = "Optimizing Applications with the {Intel C++} and
{Fortran} Compilers for {Windows} and {Linux}",
institution = inst-HP,
address = inst-HP:adr,
year = "2002",
bibdate = "Tue Nov 18 15:51:07 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.intel.com/software/products/compilers/c60/techtopics/Compiler_Optimization_6.pdf",
acknowledgement = ack-nhfb,
remark = "Web page currently inaccessible.",
}
@TechReport{Anonymous:2002:OFP,
author = "Anonymous",
title = "{OpenVMS} floating-point arithmetic on the {Itanium}
architecture",
institution = inst-HP,
address = inst-HP:adr,
month = sep,
year = "2002",
bibdate = "Tue Nov 18 15:23:17 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://sysdoc.doors.ch/HP/openvms_ipf_floating_point_wp.pdf",
acknowledgement = ack-nhfb,
}
@TechReport{Beck:2002:POA,
author = "Will Beck and Glenn Bowles and Drew Comstock and
Gaitan D'Antoni and Jim Parker",
title = "Porting {OpenVMS} Applications to {Intel Itanium}
Architecture",
type = "White paper",
institution = inst-HP,
address = inst-HP:adr,
month = apr,
year = "2002",
bibdate = "Tue Nov 18 15:20:59 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://sysdoc.doors.ch/HP/OpenVMS_IPF_PORTING_WP.pdf",
abstract = "This white paper describes aspects of porting OpenVMS
applications from OpenVMS Alpha to the Intel Itanium
architecture. The audience for this paper is system
integrators, systems and software developers,
Independent Software Vendors (ISVs), and other
partners.",
acknowledgement = ack-nhfb,
}
@TechReport{Bohr:2002:INT,
author = "Mark Bohr",
title = "{Intel}'s 90 nm Technology: {Moore's Law} and More",
institution = inst-HP,
address = inst-HP:adr,
year = "2002",
bibdate = "Tue Nov 18 15:28:49 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.intel.com/research/silicon/micron.htm",
acknowledgement = ack-nhfb,
}
@InProceedings{Bradley:2002:SCR,
author = "David Bradley and Patrick Mahoney and Blaine
Stackhouse",
title = "The {16kB} Single-Cycle Read Access Cache on a Next
Generation 64b {Itanium} Microprocessor",
crossref = "IEEE:2002:IIS",
pages = "??--??",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/isscc_2002/isscc_2002_3.shtml",
acknowledgement = ack-nhfb,
}
@Article{Brender:2002:BPL,
author = "Ronald F. Brender",
title = "The {BLISS} programming language: a history",
journal = j-SPE,
volume = "32",
number = "10",
pages = "955--981",
month = aug,
year = "2002",
CODEN = "SPEXBL",
DOI = "https://doi.org/10.1002/spe.470",
ISSN = "0038-0644 (print), 1097-024X (electronic)",
bibdate = "Wed Oct 16 18:25:57 MDT 2002",
bibsource = "http://www.interscience.wiley.com/jpages/0038-0644;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
http://www3.interscience.wiley.com/journalfinder.html",
URL = "http://www3.interscience.wiley.com/cgi-bin/abstract/96516179/START;
http://www3.interscience.wiley.com/cgi-bin/fulltext?ID=96516179&PLACEBO=IE.pdf",
abstract = "The BLISS programming language was invented by William
A. Wulf and others at Carnegie-Mellon University in
1969, originally for the DEC PDP-10. BLISS-10 caught
the interest of Ronald F. Brender of DEC (Digital
Equipment Corporation). After several years of
collaboration, including the creation of BLISS-11 for
the PDP-11, BLISS was adopted as DEC's implementation
language for use on its new line of VAX computers in
1975. DEC developed a completely new generation of
BLISSs for the VAX, PDP-10 and PDP-11, which became
widely used at DEC during the 1970s and 1980s. With the
creation of the Alpha architecture in the early 1990s,
BLISS was extended again, in both 32- and 64-bit
flavors. BLISS support for the Intel IA-32 architecture
was introduced in 1995 and IA-64 support is now in
progress.\par
BLISS has a number of unusual characteristics: it is
typeless, requires use of an explicit contents of
operator (written as a period or dot), takes an
algorithmic approach to data structure definition, has
no goto, is an expression language, and has an
unusually rich compile-time language.\par
This paper reviews the evolution and use of BLISS over
its three decade lifetime. Emphasis is on how the
language evolved to facilitate portable programming
while retaining its initial highly machine-specific
character. Finally, the success of its characteristics
are assessed.",
acknowledgement = ack-nhfb,
keywords = "BLISS; history; machine-oriented language; portable
programming; system implementation language",
}
@Book{Cornea:2002:SCI,
author = "Marius Cornea and John Harrison and Ping Tak Peter
Tang",
title = "Scientific computing on {Itanium}-based systems",
publisher = pub-INTEL,
address = pub-INTEL:adr,
pages = "xvii + 406",
year = "2002",
ISBN = "0-9712887-7-1",
ISBN-13 = "978-0-9712887-7-5",
LCCN = "????",
bibdate = "Sat Dec 06 15:02:26 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
price = "US\$69.95",
URL = "http://www.intel.com/intelpress/sum_scientific.htm",
abstract = "Written for professionals who need to write, port, or
maintain reliable, accurate, and efficient numerical
software for the Itanium architecture, Scientific
Computing on Itanium-based Systems shows you how to
construct key numerical infrastructure and application
programs.\par
This book describes the crucial techniques required for
stability and reliability in developing numerical
kernels and applications. Through numerous tested
examples, the authors explain how you can get the most
from the 64-bit architecture. This combination of
explanation with example helps you to make difficult
computations more easily and to increase the
performance of your numerical software.\par
This book provides examples to solve problems
encountered in scientific and engineering computations,
such as:\par
* Polynomial evaluation\\
* Complex arithmetic\\
* Quad-precision arithmetic\\
* Software pipelining, to include register rotation and
modulo-scheduled loop support\\
* SIMD instructions\\
* Interval arithmetic\\
* Fast-Fourier Transformation (FFT) algorithms\\
* Numerical linear algebra and basic linear algebra
subprograms(BLAS)\\
* Vector Math Library (VML)\\
* Cryptography",
acknowledgement = ack-nhfb,
}
@InProceedings{Fetzer:2002:FBI,
author = "Eric S. Fetzer and John T. Orton",
title = "A Fully-Bypassed 6-Issue Integer Datapath and Register
File on an {Itanium} Microprocessor",
crossref = "IEEE:2002:IIS",
pages = "??--??",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/isscc_2002/isscc_2002_2.shtml",
acknowledgement = ack-nhfb,
}
@Article{Greer:2002:SCI,
author = "Bruce Greer and John Harrison and Greg Henry and
others",
title = "Scientific computing on the {Itanium\reg{}}
processor",
journal = j-SCI-PROG,
volume = "10",
number = "4",
pages = "329--337",
year = "2002",
CODEN = "SCIPEV",
ISSN = "1058-9244 (print), 1875-919X (electronic)",
bibdate = "Mon Jan 12 06:28:14 MST 2004",
bibsource = "http://www.iospress.nl/site/html/10589244.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@TechReport{Johnson:2002:OIB,
author = "Teresa Johnson and Nathaniel McIntosh",
title = "Optimizing {Itanium}-based Applications",
institution = inst-HP,
address = inst-HP:adr,
year = "2002",
bibdate = "Tue Nov 18 15:04:38 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Version 1.3.",
URL = "http://h21007.www2.hp.com/dspp/tech/tech_TechDocumentDetailPage_IDX/1,1701,3207,00.html",
acknowledgement = ack-nhfb,
}
@InProceedings{Josephson:2002:DMM,
author = "Don Douglas Josephson and Steve Poehlman and Vincent
Govan",
title = "Debug Methodology for the {McKinley} Processor",
crossref = "IEEE:2002:IIS",
pages = "451--460",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/itc_2001/debug_paper.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Josephson:2002:TMMa,
author = "Doug Josephson and Steve Poehlman and Vincent Govan
and Clint Mumford",
title = "Test Methodology for the {McKinley} Processor",
crossref = "IEEE:2002:IIS",
pages = "578--585",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/itc_2001/test_paper.pdf",
acknowledgement = ack-nhfb,
}
@Misc{Josephson:2002:TMMb,
author = "Doug Josephson and Steve Poehlman and Vincent Govan
and Clint Mumford",
title = "Test Methodology for the {McKinley} Processor",
howpublished = "World-Wide Web slide presentation",
year = "2002",
bibdate = "Fri Mar 22 09:09:22 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/itc_2001/test_slides.pdf",
acknowledgement = ack-nhfb,
}
@TechReport{Li:2002:LLF,
author = "Ren-Cang Li and Peter Markstein and Jon P. Okada and
James W. Thomas",
title = "The {\tt libm} library and floating-point arithmetic
for {HP-UX} on {Itanium-2}",
type = "Technical report",
institution = inst-HP,
address = inst-HP:adr,
pages = "??",
year = "2002",
bibdate = "Tue Nov 18 15:06:56 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "????",
acknowledgement = ack-nhfb,
}
@Book{Mosberger:2002:ILK,
author = "David Mosberger and St{\'e}phane Eranian",
title = "{IA-64 Linux} kernel: design and implementation",
publisher = pub-PHPTR,
address = pub-PHPTR:adr,
pages = "559 (est.)",
year = "2002",
ISBN = "0-13-061014-3",
ISBN-13 = "978-0-13-061014-0",
LCCN = "QA76.9.A73 M67 2002",
bibdate = "Fri Mar 22 08:25:46 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
http://www.phptr.com/ptrbooks/ptr_0130610143.html",
price = "US\$59.99",
series = "Hewlett--Packard professional books",
acknowledgement = ack-nhfb,
annote = "From the publisher: ``The IA-64 Linux kernel makes
extraordinary power available to every Linux developer.
In this book, the kernel project's leaders
systematically present every major subsystem,
introducing interfaces used by Linux to abstract
platform differences, showing how these interfaces are
used in IA-64, and illuminating key issues associated
with Linux kernel operation on any platform. Covers
processes, tasks, threads, virtual memory, I/O,
symmetric multiprocessing, bootstrapping, and more.''",
}
@InProceedings{Naffziger:2002:ING,
author = "Samuel D. Naffziger and Gary Hammond",
title = "The Implementation of the Next Generation 64b
{Itanium\TM} Microprocessor",
crossref = "IEEE:2002:IIS",
pages = "??--??",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/isscc_2002/isscc_2002_1.shtml;
http://www.intel.com/design/Itanium2/techpubs/",
abstract = "The processor incorporates over 220M transistors on a
465mm 2 die and operates at >1.2GHz with an 8-stage
pipeline in a $0.18\mu$ process. It has three levels of
on-chip cache totaling over 3.3MB providing >32GB/s
bandwidth at each level.",
acknowledgement = ack-nhfb,
keywords = "McKinley",
}
@Article{Popovich:2002:ILN,
author = "Ken Popovich",
title = "{Intel} Looks to Next {Itanium}: 64-bit processor and
hyperthreading for {Xeon} chips will star at {Intel}'s
developer conference",
journal = "eWeek",
volume = "19",
number = "8",
pages = "16--16",
day = "25",
month = feb,
year = "2002",
CODEN = "????",
ISSN = "1530-6283",
bibdate = "Wed Mar 13 14:41:10 2002",
bibsource = "http://www.eweek.com/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
annote = "Merced: 733 MHz and 800 MHz, 32KB L1 cache, 96KB L2
cache, 4MB L3 cache (off chip), 2.1GB/s bus bandwidth,
released May 2001; McKinley: 1 GHz, 32KB L1 cache,
256KB L2 cache, 3 MB L3 cache (on chip), 6.4GB/s bus
bandwidth, released Q2 2002.",
}
@InProceedings{Riedlinger:2002:HBL,
author = "Reid Riedlinger and Tom Grutkowski",
title = "The High Bandwidth, {256KB} 2nd Level Cache on an
{Itanium} Microprocessor",
crossref = "IEEE:2002:IIS",
pages = "??--??",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/isscc_2002/isscc_2002_4.shtml",
acknowledgement = ack-nhfb,
}
@TechReport{Sery:2002:AOB,
author = "George Sery",
title = "Approaching the One Billion Transistor Logic Product:
Process and Design Challenges",
institution = inst-HP,
address = inst-HP:adr,
year = "2002",
bibdate = "Tue Nov 18 15:33:21 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "ftp://download.intel.com/technology/silicon/GeorgeSerySPIE0302.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Stoughton:2002:DPA,
author = "Nick Stoughton",
title = "Developing Portable Applications",
crossref = "USENIX:2002:PGT",
year = "2002",
bibdate = "Tue Oct 15 11:37:49 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Unpublished guru session talk, 2002 USENIX Annual
Technical Conference, June 10-15, 2002, Monterey
Conference Center, Monterey, CA.",
URL = "http://www.usenix.org/publications/library/proceedings/usenix02/tech/techonefile.html",
abstract = "Nick is a principal with MSB Associates, a small Bay
Area consulting firm. He is the USENIX standards
liaison, and has been working on developing standards
for portable applications (most notably POSIX and LSB)
for 10 years. He is head of delegation for the UK to
ISO/IEC JTC1/SC22/WG15, Secretary to the IEEE Portable
Applications Standards Committee, and Technical Editor
for the Itanium Architecture Specific Linix Standards
Base document. While not developing standards for
portability, he is writing portable applications for
his clients.",
acknowledgement = ack-nhfb,
}
@MastersThesis{Svensson:2002:PAI,
author = "Fredrik Svensson",
title = "Performance analysis on {Intel Itanium}",
type = "Examensarbete",
school = "Civilingenj{\"o}rsprogrammet, Lule{\aa} tekniska
universitet",
address = "Lule{\aa}, Sweden",
year = "2002",
ISSN = "1402-1617",
bibdate = "Sat Dec 06 15:04:09 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://epubl.luth.se/1402-1617/2002/078",
acknowledgement = ack-nhfb,
}
@Article{Tuomi:2002:LDM,
author = "Ilkka Tuomi",
title = "The Lives and Death of {Moore's Law}",
journal = "First Monday",
volume = "7",
number = "11",
pages = "??--??",
day = "4",
month = "11",
year = "2002",
bibdate = "Tue Nov 18 15:54:25 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://firstmonday.org/htbin/cgiwrap/bin/ojs/index.php/fm/article/view/1000/921;
http://firstmonday.org/issues/issue7_11/tuomi/",
abstract = "Moore's Law has been an important benchmark for
developments in microelectronics and information
processing for over three decades. During this time,
its applications and interpretations have proliferated
and expanded, often far beyond the validity of the
original assumptions made by Moore. Technical
considerations of optimal chip manufacturing costs have
been expanded to processor performance, economics of
computing, and social development. It is therefore
useful to review the various interpretations of Moore's
Law and empirical evidence that could support
them.\par
Such an analysis reveals that semiconductor technology
has evolved during the last four decades under very
special economic conditions. In particular, the rapid
development of microelectronics implies that economic
and social demand has played a limited role in this
industry. Contrary to popular claims, it appears that
the common versions of Moore's Law have not been valid
during the last decades. As semiconductors are becoming
important in economy and society, Moore's Law is now
becoming an increasingly misleading predictor of future
developments.",
acknowledgement = ack-nhfb,
}
@MastersThesis{Waligora:2002:MVI,
author = "Tina Waligora",
title = "{Medizinische 3D Visualisierungsalgorithmen auf Intel
Itanium (64 Bit) Prozessoren unter Windows XP 64 Bit}",
type = "{Diplomarbeit}",
school = "Stralsund Fachhochschule",
address = "Stralsund, Germany",
pages = "90",
year = "2002",
bibdate = "Wed Aug 20 09:02:54 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@InProceedings{Weiss:2002:CSB,
author = "Don Weiss and John J. Wuu and Victor Chin",
title = "The On-chip {3MB} Subarray Based 3rd Level Cache on an
{Itanium} Microprocessor",
crossref = "IEEE:2002:IIS",
pages = "??--??",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://cpus.hp.com/technical_references/isscc_2002/isscc_2002_5.shtml",
acknowledgement = ack-nhfb,
}
@InProceedings{Wells:2002:CCS,
author = "S. Wells and F. Anderson and E. Berta",
title = "The Core Clock System for a Next-Generation {Itanium}
Processor",
crossref = "IEEE:2002:IIS",
pages = "??--??",
year = "2002",
bibdate = "Fri Mar 22 09:03:13 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Aamodt:2003:FMO,
author = "Tor M. Aamodt and Pedro Marcuello and Paul Chow and
Antonio Gonz{\'a}lez and Per Hammarlund and Hong Wang
and John P. Shen",
title = "A framework for modeling and optimization of prescient
instruction prefetch",
journal = j-SIGMETRICS,
volume = "31",
number = "1",
pages = "13--24",
month = jun,
year = "2003",
CODEN = "????",
DOI = "https://doi.org/10.1145/781027.781030",
ISSN = "0163-5999 (print), 1557-9484 (electronic)",
bibdate = "Thu Jun 26 11:41:41 MDT 2008",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "This paper describes a framework for modeling
macroscopic program behavior and applies it to
optimizing prescient instruction prefetch --- novel
technique that uses helper threads to improve
single-threaded application performance by performing
judicious and timely instruction prefetch. A helper
thread is initiated when the main thread encounters a
spawn point, and prefetches instructions starting at a
distant target point. The target identifies a code
region tending to incur I-cache misses that the main
thread is likely to execute soon, even though
intervening control flow may be unpredictable. The
optimization of spawn-target pair selections is
formulated by modeling program behavior as a Markov
chain based on profile statistics. Execution paths are
considered stochastic outcomes, and aspects of program
behavior are summarized via path expression mappings.
Mappings for computing reaching, and posteriori
probability; path length mean, and variance; and
expected path footprint are presented. These are used
with Tarjan's fast path algorithm to efficiently
estimate the benefit of spawn-target pair selections.
Using this framework we propose a spawn-target pair
selection algorithm for prescient instruction prefetch.
This algorithm has been implemented, and evaluated for
the Itanium Processor Family architecture. A limit
study finds 4.8\%to 17\% speedups on an in-order
simultaneous multithreading processor with eight
contexts, over nextline and streaming I-prefetch for a
set of benchmarks with high I-cache miss rates. The
framework in this paper is potentially applicable to
other thread speculation techniques.",
acknowledgement = ack-nhfb,
keywords = "analytical modeling; helper threads; instruction
prefetch; multithreading; optimization; path
expressions",
}
@Book{Carlson:2003:IRB,
author = "Jim Carlson and Jerry Huck",
title = "{Itanium} rising: breaking through {Moore}'s second
law of computing power",
publisher = pub-PHPTR,
address = pub-PHPTR:adr,
pages = "xx + 198",
year = "2003",
ISBN = "0-13-046415-5",
ISBN-13 = "978-0-13-046415-6",
LCCN = "QA76.9.A73 C365 2003",
bibdate = "Wed Aug 20 08:55:32 MDT 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "business enterprises -- computer networks; Itanium
(microprocessor); mobile computing",
}
@Misc{CC:2003:UPI,
author = "{Cambridge Consulting}",
title = "{UltraSPARC}'s Prospects in an {Itanium} World: a
Comparative Analysis of Ultra{SPARC} and {Itanium}
Architectures, Performance Attributes, and Roadmaps for
the Future",
howpublished = "World-Wide Web document.",
day = "30",
month = may,
year = "2003",
bibdate = "Mon Jun 19 14:46:33 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://h71028.www7.hp.com/ERC/downloads/CambridgeUltraSPARC_v6.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Collard:2003:OPC,
author = "Jean-Fran{\c{c}}ois Collard and Daniel Lavery",
title = "Optimizations to prevent cache penalties for the
{Intel Itanium 2} Processor",
crossref = "IEEE:2003:PCI",
pages = "105--114",
year = "2003",
DOI = "https://doi.org/10.1109/CGO.2003.1191537",
bibdate = "Thu Jun 09 18:33:51 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "This paper describes scheduling optimizations in the
Intel Itanium compiler to prevent cache penalties due
to various micro-architectural effects on the Itanium 2
processor. This paper does not try to improve cache hit
rates but to avoid penalties, which probably all
processors have in one form or another, even in the
case of cache hits. These optimizations make use of
sophisticated methods for disambiguation of memory
references, and this paper examines the performance
improvement obtained by integrating these methods into
the cache optimizations.",
acknowledgement = ack-nhfb,
keywords = "EPIC; Intel IA-64; Itanium",
}
@TechReport{Cornea:2003:DSR,
author = "M. Cornea and J. Harrison and C. Iordache and B. Norin
and S. Story",
title = "Division, Square Root and Remainder Algorithms for the
{Intel Itanium} Architecture",
type = "Report",
institution = pub-INTEL,
address = pub-INTEL:adr,
month = nov,
year = "2003",
bibdate = "Fri Jun 24 12:05:58 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Book{Evans:2003:IAP,
author = "James S. Evans and Gregory L. Trimper",
title = "{Itanium} architecture for programmers: understanding
64-bit processors and {EPIC} principles",
publisher = pub-PH,
address = pub-PH:adr,
pages = "xxxiv + 529",
year = "2003",
ISBN = "0-13-101372-6",
ISBN-13 = "978-0-13-101372-8",
LCCN = "QA76.8.I83 E83 2003",
bibdate = "Wed Aug 20 08:55:32 MDT 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Itanium (microprocessor)",
}
@Article{Harrison:2003:FVS,
author = "John Harrison",
title = "Formal verification of square root algorithms",
journal = j-FORM-METHODS-SYST-DES,
volume = "22",
number = "2",
pages = "143--153",
month = mar,
year = "2003",
CODEN = "FMSDE6",
DOI = "https://doi.org/10.1023/A:1022973506233",
ISSN = "0925-9856 (print), 1572-8102 (electronic)",
ISSN-L = "0925-9856",
bibdate = "Sat Feb 08 08:47:21 2020",
bibsource = "http://www.math.utah.edu/pub/tex/bib/elefunt.bib;
http://www.math.utah.edu/pub/tex/bib/fparith.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "https://dl.acm.org/doi/abs/10.1023/A:1022973506233",
abstract = "We discuss the formal verification of some low-level
mathematical software for the Intel Itanium
architecture. A number of important algorithms have
been proven correct using the HOL Light theorem prover.
After briefly surveying some of our formal verification
work, we discuss in more detail the verification of a
square root algorithm, which helps to illustrate why
some features of HOL Light, in particular
programmability, make it especially suitable for these
applications.",
acknowledgement = ack-nhfb,
fjournal = "Formal Methods in System Design",
journal-URL = "https://dl.acm.org/loi/fmsd",
}
@InCollection{Hennessy:2003:PIA,
author = "John L. Hennessy and David A. Patterson",
title = "Putting It All Together: The {Intel IA-64}
Architecture and {Itanium} Processor",
crossref = "Hennessy:2003:CAQ",
pages = "351--362",
year = "2003",
bibdate = "Sat Oct 14 18:19:48 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@InProceedings{Inagaki:2003:IPS,
author = "Tatsushi Inagaki and Hideaki Komatsu and Toshio
Nakatani",
title = "Integrated prepass scheduling for a {Java}
{Just-In-Time} compiler on the {IA-64} architecture",
crossref = "IEEE:2003:PCI",
pages = "159--168",
year = "2003",
DOI = "https://doi.org/10.1109/CGO.2003.1191542",
bibdate = "Thu Jun 09 18:42:46 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "We present a new integrated prepass scheduling (IPS)
algorithm for a Java Just-In-Time (JIT) compiler, which
integrates register minimization into list scheduling.
We use backtracking in the list scheduling when we have
used up all the available registers. To reduce the
overhead of backtracking, we incrementally maintain a
set of candidate instructions for undoing scheduling.
To maximize the ILP after undoing scheduling. To
maximize the ILP after undoing scheduling, we select an
instruction chain with the smallest increase in the
total execution time. We implemented our new algorithm
in a production-level Java JIT compiler for the Intel
Itanium processor. The experiment showed that, compared
to the best known algorithm by Govindarajan et al., our
IPS algorithm improved the performance by up to +1.8\%
while it reduced the compilation time for IPS by 58\%
on average.",
acknowledgement = ack-nhfb,
}
@Misc{Intel:2003:DSR,
author = "{Intel}",
title = "Divide, Square Root, and Remainder Algorithms for the
{Itanium} Architecture",
howpublished = "Intel Software Development Products",
day = "18",
month = dec,
year = "2003",
bibdate = "Tue Nov 18 16:23:36 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.intel.com/cd/software/products/asmo-na/eng/219863.htm",
acknowledgement = ack-nhfb,
}
@Misc{Intel:2003:NID,
author = "{Intel}",
title = "Non-{IEEE} Division, Square Root, Reciprocal, and
Reciprocal Square Root Algorithms for the {Intel
Itanium} Architecture",
howpublished = "Intel Software Development Products",
day = "18",
month = dec,
year = "2003",
bibdate = "Tue Nov 18 16:23:36 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.intel.com/cd/software/products/asmo-na/eng/219864.htm",
acknowledgement = ack-nhfb,
}
@InProceedings{Lin:2003:SRP,
author = "Jin Lin and Tong Chen and Wei-Chung Hsu and Pen-Chung
Yew",
title = "Speculative register promotion using Advanced Load
Address Table ({ALAT})",
crossref = "IEEE:2003:PCI",
pages = "125--134",
year = "2003",
DOI = "https://doi.org/10.1109/CGO.2003.1191539",
bibdate = "Thu Jun 09 18:39:29 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "The pervasive use of pointers with complicated
patterns in C programs often constrains compiler alias
analysis to yield conservative register allocation and
promotion. Speculative register promotion with hardware
support has the potential to more aggressively promote
memory references into registers in the presence of
aliases. This paper studies the use of the Advanced
Load Address Table (ALAT), a data speculation feature
defined in the IA-64 architecture, for speculative
register promotion. An algorithm for speculative
register promotion based on partial redundancy
elimination is presented. The algorithm is implemented
in Intel's Open Research Compiler (ORC). Experiments on
SPEC CPU2000 benchmark programs are conducted to show
that speculative register promotion can improve
performance of some benchmarks by 1\% to 7\%.",
acknowledgement = ack-nhfb,
keywords = "EPIC; Intel IA-64; Itanium",
}
@InProceedings{Markstein:2003:FQP,
author = "Peter Markstein",
title = "A fast quad precision elementary function library for
{Itanium}",
crossref = "Anonymous:2003:CRN",
pages = "5--12",
year = "2003",
bibdate = "Fri Jun 24 20:14:39 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "This talk will describe Itanium's floating point
architecture and how it has been used to produce a high
performance, highly accurate quad precision elementary
function library.\par
Itanium's floating-point features will first be
described, from the point of view of a computer
architect. Many conflicting requirements vie for
consideration during the design of a new computer
architecture. These include instruction word size,
number of registers, the set of operations, arithmetic
precisions supported, and memory access. Some of the
trade-offs during the design phase will be
discussed.\par
One of the objectives of the original Itanium design
was to accelerate quad precision arithmetic. The talk
will describe how the Itanium elementary function
library was constructed, with attention to performance
and accuracy. Because a pair of double-extended
floating point words are used for internal operations
involving quad precision numbers, intermediate results,
holding 128 bits, provide 15 guard bits during
intermediate calculations, resulting in a very low
percentage of misrounded results.",
acknowledgement = ack-nhfb,
}
@Book{Martin:2003:ERG,
author = "Christian M{\"a}rtin",
title = "{Einf{\"u}hrung in die Rechnerarchitektur}. (German)
[{Introduction} to Computer Architecture]",
publisher = pub-HANSER,
address = pub-HANSER:adr,
pages = "170",
year = "2003",
ISBN = "3-446-22242-1",
ISBN-13 = "978-3-446-22242-7",
LCCN = "????",
bibdate = "Wed Aug 20 08:58:55 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Includes CD-ROM.",
price = "14,90 Eur[D]; 15,40 Eur[A]; 23,30 sFr",
acknowledgement = ack-nhfb,
keywords = "IBM Power 4; Intel Itanium 2; Intel Pentium 4; Intel
XScale",
language = "German",
}
@Article{McNairy:2003:IPM,
author = "Cameron McNairy and Don Soltis",
title = "{Itanium 2} Processor Microarchitecture",
journal = j-IEEE-MICRO,
volume = "23",
number = "2",
pages = "44--55",
month = mar # "\slash " # apr,
year = "2003",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/MM.2003.1196114",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Wed Apr 23 18:57:11 MDT 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://dlib.computer.org/mi/books/mi2003/pdf/m2044.pdf;
http://www.computer.org/micro/mi2003/m2044abs.htm",
acknowledgement = ack-nhfb,
}
@InProceedings{Settle:2003:OII,
author = "Alex Settle and Daniel A. Connors and Gerolf Hoflehner
and Dan Lavery",
title = "Optimization for the {Intel Itanium} Architecture
Register Stack",
crossref = "IEEE:2003:PCI",
pages = "115--124",
year = "2003",
DOI = "https://doi.org/10.1109/CGO.2003.1191538",
bibdate = "Thu Jun 09 18:28:59 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://rogue.colorado.edu/draco/abstract.php?pub=opt_regstack.pub&paper_dir=papers;
http://rogue.colorado.edu/draco/papers/cgo-03-register.pdf;
http://rogue.colorado.edu/draco/papers/cgo-03-register.ps",
abstract = "The Intel Itanium architecture contains a number of
innovative compiler-controllable features designed to
exploit instruction level parallelism. New code
generation and optimization techniques are critical to
the application of these features to improve processor
performance. For instance, the Itanium architecture
provides a compiler-controllable virtual register stack
to reduce the penalty of memory accesses associated
with procedure calls. The Itanium Register Stack Engine
(RSE) transparently manages the register stack and
saves and restores physical registers to and from
memory as needed. Existing code generation techniques
for the register stack aggressively allocate virtual
registers without regard to the register pressure on
different control-flow paths. As such, applications
with large data sets may stress the RSE, and cause
substantial execution delays due to the high number of
register saves and restores. Since the Itanium
architecture is developed around Explicitly Parallel
Instruction Computing (EPIC) concepts, solutions to
increasing the register stack efficiency favor code
generation techniques rather than hardware
approaches.",
acknowledgement = ack-nhfb,
keywords = "EPIC; Intel IA-64; Itanium",
pagecount = "10",
}
@Article{Seznec:2003:HUL,
author = "Andr{\'e} Seznec and Nicolas Sendrier",
title = "{HAVEGE}: {A} user-level software heuristic for
generating empirically strong random numbers",
journal = j-TOMACS,
volume = "13",
number = "4",
pages = "334--346",
month = oct,
year = "2003",
CODEN = "ATMCEZ",
ISSN = "1049-3301 (print), 1558-1195 (electronic)",
bibdate = "Fri Oct 31 05:50:26 MST 2003",
bibsource = "http://www.acm.org/pubs/contents/journals/tomacs/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "Random numbers with high cryptographic quality are
needed to enhance the security of cryptography
applications. Software heuristics for generating
empirically strong random number sequences rely on
entropy gathering by measuring unpredictable external
events. These generators only deliver a few bits per
event. This limits them to being used as seeds for
pseudorandom generators. General-purpose processors
feature a large number of hardware mechanisms that aim
to improve performance: caches, branch predictors,
\ldots{}. The state of these components is not
architectural (i.e., the result of an ordinary
application does not depend on it). It is also volatile
and cannot be directly monitored by the user. On the
other hand, every operating system interrupt modifies
thousands of these binary volatile states. In this
article, we present and analyze HAVEGE (HArdware
Volatile Entropy Gathering and Expansion), a new
user-level software heuristic to generate practically
strong random numbers on general-purpose computers. The
hardware clock cycle counter of the processor can be
used to gather part of the entropy\slash uncertainty
introduced by operating system interrupts in the
internal states of the processor. Then, we show how
this entropy gathering technique can be combined with
pseudorandom number generation in HAVEGE. Since the
internal state of HAVEGE includes thousands of internal
volatile hardware states, it seems impossible even for
the user itself to reproduce the generated sequences.",
acknowledgement = ack-nhfb,
annote = "From the article: ``On current PCs and workstations,
the HAVEG algorithms collects several tens of thousands
of empirically strong random bits, on average, per
every operating system interrupt, that is, HAVEG is
three to four orders of magnitude more efficient than
previous software entropy gathering
techniques.\par
\ldots{}\par
\ldots{} on all the target platforms of HAVEGE in 2002
[Seznec and Sendrier 2002], the HAVEG algorithm
illustrated in Figure 1 allows to gather at least
8K--64K random bits in average per operating system
interrupt (from 8K on Itanium/Linux to 64K on
Solaris/UltraSparc II). That is, at least three to four
orders of magnitude more than the `entropy' gathered by
previously available entropy-gathering
techniques.\par
\ldots{}\par
In average on Pentium III, 920 million $\pm5\%$ cycles
were needed to collect 32 Mbytes of random numbers,
while on the UltraSparc II, 500 million $\pm5\%$ cycles
were sufficient. This throughput is in the same range
as the throughput of standard pseudorandom number
generators.''\par
Thus, it seems that this algorithm deserves careful
consideration for use in {\tt /dev/random} and {\tt
/dev/urandom} pseudodevices in Unix systems, since the
former in particular on several platforms can be
rapidly drained of data, causing very long input waits
(e.g., two days to read 10MB of data.)",
}
@Article{Shacklett:2003:IDC,
author = "Mary Shacklett",
title = "{Itanium} in the Data Center",
journal = "Enterprise Networks \& Servers",
volume = "9",
number = "8",
pages = "9, 14",
month = aug,
year = "2003",
ISSN = "1058-5400",
bibdate = "Wed Aug 20 08:50:08 2003",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@InProceedings{Stinson:2003:GTG,
author = "Jason Stinson and Stefan Rusu",
editor = "{IEEE}",
booktitle = "Digest of technical papers: 2003 IEEE International
Solid-State Circuits Conference: Sunday through
Thursday, February 9--13, 2003, San Francisco,
California",
title = "A {1.5 GHz} Third Generation {Itanium}
Microprocessor",
publisher = pub-IEEE,
address = pub-IEEE:adr,
year = "2003",
bibdate = "Tue Nov 18 15:37:17 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "IEEE Catalog Number 03CH37414",
URL = "http://sunsite.rediris.es/pub/mirror/intel/Itanium2/download/14_4_slides_r31_nsn.pdf",
acknowledgement = ack-nhfb,
bookpages = "532 + 32",
}
@InProceedings{Thomas:2003:IMF,
author = "James W. Thomas",
title = "Inlining of mathematical functions in {HP-UX} for
{Itanium 2}",
crossref = "IEEE:2003:PCI",
pages = "135--144",
year = "2003",
DOI = "https://doi.org/10.1109/CGO.2003.1191540",
bibdate = "Thu Jun 09 18:37:10 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "HP-UX compilers inline mathematical functions for
Itanium Processor Family (IPF) systems to improve
throughput 4X--8X versus external library calls,
achieving speeds comparable to highly tuned vector
functions, without requiring the user to code for a
vector interface and without sacrificing accuracy or
edge-case behaviors. This paper highlights IPF
architectural features that support implementation of
high-performance, high-quality math functions for
inlining. It discusses strategies for utilizing the
features and developing inlineable sequences on a large
scale, and it presents requisite compiler features and
language extensions. Also, this paper describes
compiler mechanisms that produce inlineable code and
inline it.",
acknowledgement = ack-nhfb,
keywords = "EPIC; Intel IA-64; Itanium",
}
@TechReport{Akutin:2004:HOM,
author = "Yuri Akutin and Cristina Anderson and Marius Cornea
and Alexey Ershov and Eugeny Gladkov and Evgeny Gvozdev
and Bob Hanek and John Harrison and Alexander Isaev and
Andrey Kolesov and Alexey Kovalev and Elena Luneva and
Sergey Maidanov and Andrey Naraikin and Bob Norin and
Pavel Shelepugin and Vladimir Sorokin and Shane Story
and Ping Tak Peter Tang",
title = "Highly Optimized Mathematical Functions for the
{IA-64} Architecture",
type = "Application note",
number = "245410-011",
institution = pub-INTEL,
address = pub-INTEL:adr,
pages = "14",
day = "16",
month = dec,
year = "2004",
bibdate = "Tue Nov 18 15:45:26 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "ftp://download.intel.com/software/opensource/numerics/libm.pdf;
http://www.intel.com/cd/software/products/asmo-na/eng/219868.htm;
http://www.intel.com/cd/software/products/asmo-na/eng/219871.htm?prn=y",
abstract = "Highly Optimized Mathematical Functions for the Intel
Itanium Architecture Intel Corporation is providing
Intel Itanium assembler source code to evaluate certain
core mathematical support functions for the C and
FORTRAN programming languages. The intent is that these
should replace less optimized implementations that
would normally be provided by the compiler or OS
vendor. The functions work well on the Itanium 2
processor as well as the original Itanium
processor.\par
The present document explains the rationale behind this
decision and summarizes important information on
performance and accuracy of the Intel-provided
functions.",
acknowledgement = ack-nhfb,
}
@Misc{Anonymous:2004:IIP,
author = "Anonymous",
title = "{Intel Itanium} Processor Family Reference Guide:
{IA-32} Execution Layer",
howpublished = "Web document.",
institution = inst-HP,
address = inst-HP:adr,
pages = "2",
year = "2004",
bibdate = "Tue Nov 18 15:43:45 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://download.intel.com/design/Itanium/Downloads/25431803.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{August:2004:IPS,
author = "David I. August and Daniel A. Connors and Scott A.
Mahlke and John W. Sias and Kevin M. Crozier and
Ben-Chung Cheng and Patrick R. Eaton and Qudus B.
Olaniran and Wen-mei W. Hwu",
title = "Integrated Predicated and Speculative Execution in the
{IMPACT EPIC} Architecture",
crossref = "DeGroot:1998:PIS",
pages = "227--237",
year = "2004",
DOI = "https://doi.org/10.1145/279358.279391",
bibdate = "Thu Jun 09 18:10:27 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://rogue.colorado.edu/draco/abstract.php?pub=impact.pub&paper_dir=papers;
http://rogue.colorado.edu/draco/papers/isca-98-epic.pdf;
http://rogue.colorado.edu/draco/papers/isca-98-epic.ps",
abstract = "Explicitly Parallel Instruction Computing (EPIC)
architectures require the compiler to express program
instruction level parallelism directly to the hardware.
EPIC techniques which enable the compiler to represent
control speculation, data dependence speculation, and
predication have individually been shown to be very
effective. However, these techniques have not been
studied in combination with each other. This paper
presents the IMPACT EPIC Architecture to address the
issues involved in designing processors based on these
EPIC concepts. In particular, we focus on new execution
and recovery models in which microarchitectural support
for predicated execution is also used to enable
efficient recovery from exceptions caused by
speculatively executed instructions. This paper
demonstrates that a coherent framework to integrate the
three techniques can be elegantly designed to achieve
much better performance than each individual technique
could alone provide.",
acknowledgement = ack-nhfb,
keywords = "IMPACT EPIC; Intel IA-64; Itanium",
}
@TechReport{Baraz:2004:IEL,
author = "Leonid Baraz and Tevi Devor and Orna Etzion and Shalom
Goldenberg and Alex Skaletsky and Yun Wang and Yigal
Zemach",
title = "{IA-32} Execution Layer: a two-phase dynamic
translator designed to support {IA-32} applications on
{Itanium}-based systems",
institution = inst-HP,
address = inst-HP:adr,
year = "2004",
bibdate = "Tue Nov 18 15:27:35 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.intel.com/cd/ids/developer/asmo-na/eng/93086.htm",
acknowledgement = ack-nhfb,
}
@Article{Brifault:2004:DCM,
author = "K. Brifault and H. P. Charles",
title = "Data cache management on {EPIC} architecture:
optimizing memory access for image processing",
journal = j-COMP-ARCH-NEWS,
volume = "32",
number = "3",
pages = "35--42",
month = jun,
year = "2004",
CODEN = "CANED2",
DOI = "https://doi.org/10.1145/1024295.1024300",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Thu Jun 09 18:45:48 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "Nowadays, multimedia applications are more and more
used, and take a larger place in the workloads of
modern computing systems. It appears that the classical
1D spatial locality arrangement in the cache is not
adapted to the management of this data type, because
its structures exhibit an intrinsic 2D locality.In this
article, we study cache behavior and alternative
strategies for multimedia, using a JPEG benchmark on an
Itanium 2 cache system. We demonstrate, through
systematic experiments, that performance can be very
sensitive to data structure, revealing that cache
organization has a major impact on performance. We then
present the results of our experiments with suggestions
to improve future media processing compiler design.",
acknowledgement = ack-nhfb,
}
@InProceedings{Buck:2004:DCC,
author = "Bryan R. Buck and Jeffrey K. Hollingsworth",
title = "Data Centric Cache Measurement on the {Intel Itanium
2} Processor",
crossref = "ACM:2004:SHP",
pages = "58--58",
year = "2004",
bibdate = "Tue Dec 27 07:57:20 MST 2005",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@TechReport{deDinechin:2004:FCR,
author = "Florent de Dinechin and David Defour and Christoph
Lauter",
title = "Fast correct rounding of elementary functions in
double precision using double-extended arithmetic",
type = "Research Report",
number = "RR2004-10",
institution = "{\'E}cole Normale Sup{\'e}rieure de Lyon",
address = "69364 Lyon Cedex 07, France",
pages = "2 + 12",
month = mar,
year = "2004",
bibdate = "Mon Dec 06 10:49:12 2004",
bibsource = "http://www.ens-lyon.fr/LIP/Pub/rr2004.php;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-10.pdf",
abstract = "This article shows that IEEE-754 double-precision
correct rounding of the most common elementary
functions (exp/log, trigonometric and hyperbolic) is
achievable on current processors using only
double-double-extended arithmetic. This allows to
improve by several orders of magnitude the worst case
performance of a correctly-rounded mathematical
library, compared to the current state of the art. This
article builds up on previous work by Lef{\`e}vre and
Muller, who have shown that an intermediate accuracy of
up to 158 bits is required for the evaluation of some
functions. We show that the practical accuracy required
can always be reduced to less than 119 bits, which is
easy to obtain using well-known and well-proven
techniques of double-double-extended arithmetic. As an
example, a prototype implementation of the exponential
function on the Itanium has a worst-case time about
twice that of the standard, highly optimized libm by
Intel, which doesn't offer correct rounding. Such a
small performance penalty should allow correct rounding
of elementary functions to become the standard.",
acknowledgement = ack-nhfb,
keywords = "Correct Rounding; Double-extended Precision;
Elementary Functions; IEEE-754",
}
@InProceedings{Hoflehner:2004:COT,
author = "Gerolf Hoflehner and Knud Kirkegaard and Rod Skinner
and Daniel Lavery and Yong-fong Lee and Wei Li",
title = "Compiler Optimizations for Transaction Processing
Workloads on {Itanium Linux} Systems",
crossref = "IEEE:2004:PIS",
pages = "294--303",
year = "2004",
DOI = "https://doi.org/10.1109/MICRO.2004.11",
bibdate = "Thu Jun 09 19:04:31 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "This paper discusses a repertoire of well-known and
new compiler optimizations that help produce excellent
server application performance and investigates their
performance contributions. These optimizations combined
produce a 40\% speed-up in on-line transaction
processing (OLTP) performance and have been implemented
in the Intel C/C++ Itanium compiler. In particular, the
paper presents compiler optimizations that take
advantage of the Itanium register stack, proposes an
enhanced Linux preemption model and demonstrates their
performance potential for server applications.",
acknowledgement = ack-nhfb,
}
@Article{Rusu:2004:IPH,
author = "Stefan Rusu and Harry Muljono and Brian Cherkauer",
title = "{Itanium 2} Processor {6M}: Higher Frequency and
Larger {L3} Cache",
journal = j-IEEE-MICRO,
volume = "24",
number = "2",
pages = "10--18",
month = mar # "\slash " # apr,
year = "2004",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/MM.2004.1289279",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Sat Dec 11 17:59:16 MST 2004",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://csdl.computer.org/comp/mags/mi/2004/02/m2010abs.htm;
http://csdl.computer.org/dl/mags/mi/2004/02/m2010.htm;
http://csdl.computer.org/dl/mags/mi/2004/02/m2010.pdf",
acknowledgement = ack-nhfb,
}
@InProceedings{Settle:2004:CCR,
author = "Alex Settle and Daniel Lavery and Gerolf Hoflehner and
Daniel A. Connors",
editor = "????",
booktitle = "Proceedings of the 3rd Workshop on Explicitly Parallel
Instruction Computing Architectures and Compiler
Techniques. March, 2004.",
title = "Compiler Controlled Register Stack Management for the
{Intel Itanium} Architecture",
publisher = "????",
address = "????",
pages = "??--??",
day = "20",
month = jan,
year = "2004",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Thu Jun 09 18:10:27 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://rogue.colorado.edu/draco/abstract.php?pub=epic04-regstack.pub&paper_dir=papers;
http://rogue.colorado.edu/draco/papers/epic04-regstack.pdf;
http://rogue.colorado.edu/draco/papers/epic04-regstack.ps",
acknowledgement = ack-nhfb,
keywords = "EPIC; Intel IA-64; Itanium",
pagecount = "10",
}
@Article{Sias:2004:FTI,
author = "John W. Sias and Sain-zee Ueng and Geoff A. Kent and
Ian M. Steiner and Erik M. Nystrom and Wen-mei W. Hwu",
title = "Field-testing {IMPACT EPIC} research results in
{Itanium 2}",
journal = j-COMP-ARCH-NEWS,
volume = "32",
number = "2",
pages = "26--26",
month = mar,
year = "2004",
CODEN = "CANED2",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Fri May 12 09:40:45 MDT 2006",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@TechReport{Thomas:2004:LLF,
author = "James W. Thomas and Jon P. Okada and Peter Markstein
and Ren-Cang Li",
title = "The {\tt Libm} Library and Floating-Point Arithmetic
in {HP-UX} for {Itanium}-Based Systems: Updated for
{HP-UX 11i v2}",
type = "Technical report",
institution = inst-HP,
address = inst-HP:adr,
pages = "26",
day = "3",
month = dec,
year = "2004",
bibdate = "Fri Jun 24 20:12:09 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://h21007.www2.hp.com/dspp/ddl/ddl_Download_File_TRX/1,1249,942,00.pdf",
abstract = "The HP-UX libm library provides mathematical functions
for C, C++, and Fortran 90. The HP-UX libm library and
compilers for Itanium-based systems provide a leading
combination of functionality, quality, and
performance.With inlining and software pipelining,
commonly used math functions can achieve throughput
comparable to hand-tuned vector routines without
requiring user code to be written for a vector
interface, and with no loss of accuracy or edge-case
behavior: For example, the single precision exponential
can exceed 400 million evaluations per second on a 1.5
GHz Itanium 2 system. The math API encompasses C99,
X/Open, and other popular functionality and offers four
fully supported IEEE floating types. The libm library
and compilers provide features that facilitate
programming techniques that have not been practical
heretofore. The libm implementation for Itanium-based
systems, introduced in 2001 in HP-UX B.11.20 (11i
v1.5), has been upgraded in B.11.22 (11i v1.6), B.11.23
(11i v2), and most recently in B.11.23 AR1204 and the
associated Math Library Cumulative Patch PHSS_31853
with improved performance and overall quality and with
a few new functions. The AR1204 compilers are available
as patches for B.11.22; the associated Math patch for
B.11.22 is PHSS_32066. This paper (1) describes the
latest libm library (including sequences the compilers
inline) in terms of functionality, speed, accuracy,
standards, and special-case behavior; (2) discusses
programming techniques that exploit the floating-point
capabilities of HP-UX on Itanium- based systems; and
(3) describes motivations, goals, and development
strategies for the libm library and the compiler
floating-point facilities.",
acknowledgement = ack-nhfb,
}
@InProceedings{Vachharajani:2004:FPF,
author = "Manish Vachharajani. {Matthew Iyer, Chinmay Ashok,
Josh Stone, Neil Vachharajani, Daniel A. Connors}",
editor = "????",
booktitle = "Proceedings of the 4th Workshop on Explicitly Parallel
Instruction Computing. March, 2005.",
title = "Finding Parallelism for Future {EPIC} Machines",
publisher = "????",
address = "????",
pages = "??--??",
year = "2004",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Thu Jun 09 18:10:27 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://rogue.colorado.edu/draco/abstract.php?pub=epic05-ilp.pub&paper_dir=papers;
http://rogue.colorado.edu/draco/papers/epic05-ilp.pdf;
http://rogue.colorado.edu/draco/papers/epic05-ilp.ps",
acknowledgement = ack-nhfb,
keywords = "EPIC; Intel IA-64; Itanium",
}
@Article{Vachharajani:2004:LSE,
author = "Manish Vachharajani and Neil Vachharajani and David A.
Penry and Jason A. Blome and David I. August",
title = "The {Liberty Simulation Environment}, version 1.0",
journal = j-SIGMETRICS,
volume = "31",
number = "4",
pages = "19--24",
month = mar,
year = "2004",
CODEN = "????",
DOI = "https://doi.org/10.1145/1054907.1054912",
ISSN = "0163-5999 (print), 1557-9484 (electronic)",
bibdate = "Fri Jun 27 09:20:52 MDT 2008",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "High-level hardware modeling via simulation is an
essential step in hardware systems design and research.
Despite the importance of simulation, current model
creation methods are error prone and are unnecessarily
time consuming. To address these problems, we have
publicly released the Liberty Simulation Environment
(LSE), Version 1.0, consisting of a simulator builder
and automatic visualizer based on a shared hardware
description language. LSE's design was motivated by a
careful analysis of the strengths and weaknesses of
existing systems. This has resulted in a system in
which models are easier to understand, faster to
develop, and have performance on par with other
systems. LSE is capable of modeling {\em any\/}
synchronous hardware system. To date, LSE has been used
to simulate and convey ideas about a diverse set of
complex systems including a chip multiprocessor
out-of-order IA-64 machine and a multiprocessor system
with detailed device models.",
acknowledgement = ack-nhfb,
}
@Article{Wang:2004:HTVa,
author = "Perry H. Wang and Jamison D. Collins and Hong Wang and
Dongkeun Kim and Bill Greene and Kai-Ming Chan and
Aamir B. Yunus and Terry Sych and Stephen F. Moore and
John P. Shen",
title = "Helper threads via virtual multithreading on an
experimental {Itanium-2} processor-based platform",
journal = j-COMP-ARCH-NEWS,
volume = "32",
number = "5",
pages = "144--155",
month = dec,
year = "2004",
CODEN = "CANED2",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Fri May 12 09:41:24 MDT 2006",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Co-published in {\em Operating Systems Review}, ({\bf
38})(4).",
acknowledgement = ack-nhfb,
}
@Article{Wang:2004:HTVb,
author = "Perry H. Wang and Jamison D. Collins and Hong Wang and
Dongkeun Kim and Bill Greene and Kai-Ming Chan and
Aamir B. Yunus and Terry Sych and Stephen F. Moore and
John P. Shen",
title = "Helper threads via virtual multithreading on an
experimental {Itanium-2} processor-based platform",
journal = j-SIGPLAN,
volume = "39",
number = "11",
pages = "144--155",
month = nov,
year = "2004",
CODEN = "SINODQ",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Tue Apr 12 09:38:13 MDT 2005",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Wang:2004:HTVc,
author = "Perry H. Wang and Jamison D. Collins and Hong Wang and
Dongkeun Kim and Bill Greene and Kai-Ming Chan and
Aamir B. Yunus and Terry Sych and Stephen F. Moore and
John P. Shen",
title = "Helper threads via virtual multithreading on an
experimental {Itanium-2} processor-based platform",
journal = j-OPER-SYS-REV,
volume = "38",
number = "5",
pages = "144--155",
month = dec,
year = "2004",
CODEN = "OSRED8",
ISSN = "0163-5980 (print), 1943-586X (electronic)",
bibdate = "Sat Aug 26 08:55:56 MDT 2006",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Article{Wolfe:2004:GTC,
author = "Alexander Wolfe",
title = "{Grid} Tools: Coming to a Cluster Near You",
journal = j-QUEUE,
volume = "2",
number = "4",
pages = "20--23",
month = jun,
year = "2004",
bibdate = "Thu Jun 03 17:42:59 2004",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Gelato Federation; GNU/Linux; HP Ski emulator for
Itanium architecture; SmartFrog (Smart Framework for
Object Groups)",
}
@InProceedings{Boldo:2005:SFC,
author = "Sylvie Boldo and Jean-Michel Muller",
title = "Some Functions Computable with a Fused-mac",
crossref = "IEEE:2005:PIS",
pages = "??--??",
year = "2005",
bibdate = "Wed Jun 22 07:02:55 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://arith17.polito.it/final/paper-106.pdf",
abstract = "The fused multiply accumulate instruction (fused-mac)
that is available on some current processors such as
the Power PC or the Itanium eases some calculations. We
give examples of some floating-point functions (such as
ulp(x) or Nextafter(x, y)), or some useful tests, that
are easily computable using a fused-mac. Then, we show
that, with rounding to the nearest, the error of a
fused-mac instruction is exactly representable as the
sum of two floating-point numbers. We give an algorithm
that computes that error.",
acknowledgement = ack-nhfb,
pagecount = "7",
}
@Book{Colwell:2005:PCP,
author = "Robert P. Colwell",
title = "The {Pentium} Chronicles: The People, Passion, and
Politics Behind {Intel}'s Landmark Chips",
publisher = pub-WILEY,
address = pub-WILEY:adr,
pages = "xix + 187",
year = "2005",
ISBN = "0-471-73617-1",
ISBN-13 = "978-0-471-73617-2",
LCCN = "????",
bibdate = "Fri Dec 09 06:57:21 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
price = "US\$24.95",
acknowledgement = ack-nhfb,
remark = "Chapter 7 contains some interesting remarks on the
internal conflicts between the IA-32 and IA-64 design
teams, and on architectural complexity.",
}
@InProceedings{Djoudi:2005:MMA,
author = "Lamia Djoudi and Denis Barthou and Patrick Carribault
and Christophe Lemuet and Jean-Thomas Acquaviva and
William Jalby",
editor = "????",
booktitle = "{The 4th Workshop on EPIC architectures and compiler
technology, San Jose, CA, USA}",
title = "{MAQAO}: Modular assembler quality analyzer and
optimizer for {Itanium 2}",
volume = "200",
publisher = "????",
address = "????",
pages = "20",
year = "2005",
bibdate = "Sat Feb 08 10:41:13 2020",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "https://hal.archives-ouvertes.fr/hal-00141075/en/;
https://www.labri.fr/perso/barthou/ps/maqao.pdf",
acknowledgement = ack-nhfb,
}
@Book{Fisher:2005:ECV,
author = "Joseph A. Fisher and Paolo Faraboschi and Clifford
Young",
title = "Embedded computing: a {VLIW} approach to architecture,
compilers and tools",
publisher = pub-MORGAN-KAUFMANN,
address = pub-MORGAN-KAUFMANN:adr,
pages = "xxxiii + 671",
year = "2005",
ISBN = "1-55860-766-8 (hardcover)",
ISBN-13 = "978-1-55860-766-8 (hardcover)",
LCCN = "TK7895.E42 F57 2005; TK7895.E42 F57 2005",
bibdate = "Mon Aug 8 06:07:19 MDT 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
libraries.colorado.edu:210/INNOPAC",
acknowledgement = ack-nhfb,
subject = "Embedded computer systems; Design and construction",
}
@InProceedings{Markstein:2005:FSM,
author = "Peter Markstein",
title = "A Fast-Start Method for Computing the Inverse
Tangent",
crossref = "IEEE:2005:PIS",
pages = "??--??",
year = "2005",
bibdate = "Wed Jun 22 07:02:55 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://arith17.polito.it/final/paper-112.pdf",
abstract = "In a search for an algorithm to compute $\atan(x)$
which has both low latency and few floating point
instructions, an interesting variant of familiar
trigonometry formulas was discovered that allow the
start of argument reduction to commence before any
references to tables stored in memory are needed. Low
latency makes the method suitable for a closed
subroutine, and few floating point operations make the
method advantageous for a software-pipelined
implementation.",
acknowledgement = ack-nhfb,
keywords = "IA-64; Itanium-2",
pagecount = "6",
}
@Article{McNairy:2005:MDC,
author = "Cameron McNairy and Rohit Bhatia",
title = "{Montecito}: {A} Dual-Core, Dual-Thread {Itanium}
Processor",
journal = j-IEEE-MICRO,
volume = "25",
number = "2",
pages = "10--20",
month = mar # "\slash " # apr,
year = "2005",
CODEN = "IEMIDZ",
DOI = "https://doi.org/10.1109/MM.2005.34",
ISSN = "0272-1732 (print), 1937-4143 (electronic)",
bibdate = "Wed Apr 20 08:11:29 MDT 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://csdl.computer.org/comp/mags/mi/2005/02/m2010abs.htm;
http://csdl.computer.org/dl/mags/mi/2005/02/m2010.pdf",
acknowledgement = ack-nhfb,
}
@Book{Poniatowski:2005:LHI,
author = "Marty Poniatowski",
title = "{Linux} on {HP Integrity Servers}: system
administration for {Itanium}-based systems",
publisher = pub-PHPTR,
address = pub-PHPTR:adr,
pages = "xxvi + 332",
year = "2005",
ISBN = "0-13-140000-2",
ISBN-13 = "978-0-13-140000-9",
LCCN = "QA76.76.O63 P652 2005",
bibdate = "Wed Nov 19 08:25:10 MST 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
z3950.loc.gov:7090/Voyager",
acknowledgement = ack-nhfb,
keywords = "IA-64; Itanium",
subject = "Linux; operating systems (computers); Hewlett--Packard
computers; computer networks",
}
@InProceedings{Robison:2005:BUD,
author = "Arch Robison",
title = "{$N$}-Bit Unsigned Division Via {$N$}-Bit
Multiply-Add",
crossref = "IEEE:2005:PIS",
pages = "??--??",
year = "2005",
bibdate = "Wed Jun 22 07:02:55 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://arith17.polito.it/final/paper-104.pdf",
abstract = "Integer division on modern processors is expensive
compared to multiplication. Previous algorithms for
performing unsigned division by an invariant divisor,
via reciprocal approximation, suffer in the worst case
from a common requirement for $n+1$ bit multiplication,
which typically must be synthesized from $n$-bit
multiplication and extra arithmetic operations. This
paper presents, and proves, a hybrid of previous
algorithms that replaces $n+1$ bit multiplication with
a single fused multiply-add operation on $n$-bit
operands, thus reducing any $n$-bit unsigned division
to the upper $n$ bits of a multiply-add, followed by a
single right shift. An additional benefit is that the
prerequisite calculations are simple and fast. On the
Itanium 2 processor, the technique is advantageous for
as few as two quotients that share a common run-time
divisor.",
acknowledgement = ack-nhfb,
pagecount = "9",
}
@Article{Snavely:2005:UUU,
author = "N. Snavely and S. Debray and G. R. Andrews",
title = "Unpredication, unscheduling, unspeculation: reverse
engineering {Itanium} executables",
journal = j-IEEE-TRANS-SOFTW-ENG,
volume = "31",
number = "2",
pages = "99--115",
month = feb,
year = "2005",
CODEN = "IESEDJ",
DOI = "https://doi.org/10.1109/TSE.2005.27",
ISSN = "0098-5589 (print), 1939-3520 (electronic)",
ISSN-L = "0098-5589",
bibdate = "Thu Feb 1 11:00:42 MST 2018",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeetranssoftweng2000.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1401927",
acknowledgement = ack-nhfb,
fjournal = "IEEE Transactions on Software Engineering",
journal-URL = "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=32",
}
@InProceedings{Anwar:2006:SNG,
author = "Arif Anwar",
title = "{SynaBASE}: Next-Generation Bioinformatics Database
Platform",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Avetisyan:2006:IRA,
author = "Arutyun I. Avetisyan",
title = "The {ISP RAS} Activities for Improving {GCC} for
{Itanium}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_gccimprov_avetisyan_ispras.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Chatterjee:2006:BML,
author = "Soumitra Chatterjee",
title = "64-Bit Migration to {Linux} on {Itanium}: Challenges,
Advantages, and Tools",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "GNU/Linux; Intel IA-64; Itanium",
}
@InProceedings{Chubb:2006:GS,
author = "Peter Chubb",
title = "The {GPT} and Superpages",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_superpages_chubb_unsw.pdf",
acknowledgement = ack-nhfb,
keywords = "Global Page Table (GPT); Intel IA-64; Itanium",
}
@InProceedings{Chubb:2006:VUL,
author = "Peter Chubb",
title = "Virtualization and User-Level Drivers",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_vm_chubb_unsw.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Chung:2006:COA,
author = "Shin Yee Chung",
title = "{ClustalW} Optimization: Adaptive Scheduling",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_clustalwaddon_chung_ihpc.pdf;
http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_clustalwperf_chung_ihpc.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@Misc{Clabby:2006:HIA,
author = "Joe Clabby",
title = "The {HP Itanium} Architecture Decision",
howpublished = "Internet video program.",
day = "24",
month = oct,
year = "2006",
bibdate = "Tue Oct 24 11:33:08 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://itw.itworld.com/GoNow/a30051a154506a382798246a0",
acknowledgement = ack-nhfb,
keywords = "IA-64",
remark = "Negative review of Itanium.",
}
@InProceedings{DeRose:2006:EXI,
author = "C{\'e}sar {De Rose}",
title = "Evaluating {Xen IA-64} Security and Performance",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_xeneval_derose_pucrs.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Dong:2006:XIV,
author = "Yaozu Dong",
title = "{Xen} and {Intel} Virtualization Technology for
{IA-64}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_xenvt_dong_intel.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Eranian:2006:UPI,
author = "St{\'e}phane Eranian",
title = "Update on the {Perfmon2} Interface",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_perfmon2_eranian_hp.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Geary:2006:KGC,
author = "Steve Geary",
title = "Keynote---{Gelato}: {A} Call to Arms",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{George:2006:PMI,
author = "Jini Susan George",
title = "Performance Monitoring on {Itanium}: the {PMU} Counter
Advantage",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_caliper_george_hp.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Gigante:2006:HPS,
author = "Mike Gigante",
title = "High-Performance Storage Solutions on {IA-64 Linux}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "GNU/Linux; Intel IA-64; Itanium",
}
@InCollection{Hennessy:2006:III,
author = "John L. Hennessy and David A. Patterson",
title = "The {Intel IA-64} and {Itanium} Processor",
crossref = "Hennessy:2006:CAQ",
pages = "{G-32}-{G-43}",
year = "2006",
bibdate = "Sat Oct 14 18:16:41 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@InProceedings{Huang:2006:CLK,
author = "Feilong Huang",
title = "Compiling the {Linux} Kernel with the {Intel}
Compiler",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "GNU/Linux kernel; Intel IA-64; Itanium",
}
@InProceedings{Hung:2006:HPH,
author = "Terence Hung",
title = "Host Presentation---{HPC} and {Grid} {R\&D} Activities
at {IHPC}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_ihpc_hung_ihpc.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Johnson:2006:SLO,
author = "Doug Johnson",
title = "Storage Layout Optimizations to Improve Parallel
Distributed Filesystem Performance",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Johnsson:2006:EIC,
author = "Lennart Johnsson",
title = "Experiences with {Itanium} Clusters in {Grids}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_clustergrid_johnsson_uhouston.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Jurga:2006:PEP,
author = "Ryszard Erazm Jurga",
title = "Practical Experience with Performance Monitors on
{Xeon} and {Itanium}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_pmuexperience_jurga_cern.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@Article{Kawahito:2006:ESE,
author = "Motohiro Kawahito and Hideaki Komatsu and Toshio
Nakatani",
title = "Effective sign extension elimination for {Java}",
journal = j-TOPLAS,
volume = "28",
number = "1",
pages = "106--133",
month = jan,
year = "2006",
CODEN = "ATPSDT",
DOI = "https://doi.org/10.1145/1111596.1111599",
ISSN = "0164-0925 (print), 1558-4593 (electronic)",
bibdate = "Tue Jan 24 05:55:31 MST 2006",
bibsource = "http://www.acm.org/pubs/contents/journals/toplas/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "Computer designs are shifting from 32-bit
architectures to 64-bit architectures, while most of
the programs available today are still designed for
32-bit architectures. Java, for example, specifies the
frequently used ``int'' as a 32-bit signed integer. If
such Java programs are executed on a 64-bit
architecture, many 32-bit signed integers must be
sign-extended to 64-bit signed integers for correct
operations. This causes serious performance overhead.
In this article, we present a fast and effective
algorithm for eliminating sign extensions. We
implemented this algorithm in the IBM Java Just-in-Time
(JIT) compiler for IA-64. Our experimental results show
that our algorithm effectively eliminates the majority
of sign extensions. They also show that it improves
performance by 6.9\% for jBYTEmark and 3.3\% for
SPECjvm98 over the previously known best algorithm,
while it increases JIT compilation time by only
0.11\%.",
acknowledgement = ack-nhfb,
}
@InProceedings{Konagaya:2006:PSS,
author = "Akihiko Konagaya and Ryuzo Azuma",
title = "Particle Simulation for Subcellular Dynamics and
Localization of Biological Molecules",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_partsim_konagaya_riken.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Kulkarni:2006:SCS,
author = "Pankaj Kulkarni",
title = "{S7} Case Study: Porting 2 Million Lines of {C++} Code
to {HP-UX Itanium}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_s7study_kulkarni_s7softwaresolutions.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Lau:2006:IPR,
author = "Jon Lau",
title = "{Itanium} Projects: From {R\&D} to Industry",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_projects_lau_ngo.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Lee:2006:HPN,
author = "Hing Yan Lee",
title = "Host Presentation---{National Grid Office} in
{Singapore}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_ngo_lee_ngo.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Liu:2006:UOP,
author = "Shin-Ming Liu",
title = "Update on the {Osprey Project}, the Alternative {GCC}
Backend for {Itanium}",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_osprey_liu_hp.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{McNairy:2006:BII,
author = "Cameron McNairy",
title = "Basic {Intel Itanium} Architecture",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{McNairy:2006:HTD,
author = "Cameron McNairy",
title = "Hyper-Threading on Dual-Core {Intel Itanium 2}
Processors",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Moore:2006:OSI,
author = "Eric W. Moore",
title = "Optimizing Software for {Intel Itanium} Architecture
with {Intel} Compilers",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Neuner:2006:ILS,
author = "Steve Neuner",
title = "An Inside Look at Scaling {Linux} to 1024 Processors",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_scaling1024_neuner_sgi.pdf",
acknowledgement = ack-nhfb,
keywords = "GNU/Linux; Intel IA-64; Itanium",
}
@InProceedings{Pinsky:2006:GCC,
author = "Lawrence Pinsky",
title = "{Grid} Computing at {CERN}: An Update on Preparations
for First Beam in 2007",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_gridlhc_pinsky_uhouston.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Roothaan:2006:CDC,
author = "Clemens C. Roothaan",
title = "Compiler Design Criteria for Modulo Scheduled
{Itanium} Codes",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Shermerhorn:2006:HOL,
author = "Lee Shermerhorn",
title = "{HP\slash OSLO Linux} Scalability Tracking and
Investigations",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_scaltracking_shermerhorn_hp.pdf",
acknowledgement = ack-nhfb,
keywords = "GNU/Linux; Intel IA-64; Itanium",
}
@Article{Srinivasan:2006:PMU,
author = "R. Srinivasan and J. Cook and O. Lubeck",
title = "Performance modeling using {Monte Carlo} simulation",
journal = j-IEEE-COMPUT-ARCHIT-LETT,
volume = "5",
number = "1",
pages = "38--41",
month = jan,
year = "2006",
DOI = "https://doi.org/10.1109/L-CA.2006.10",
ISSN = "1556-6056 (print), 1556-6064 (electronic)",
ISSN-L = "1556-6056",
bibdate = "Fri Jun 21 05:49:19 2019",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "Cycle accurate simulation has long been the primary
tool for micro-architecture design and evaluation.
Though accurate, the slow speed often imposes
constraints on the extent of design exploration. In
this work, we propose a fast, accurate Monte-Carlo
based model for predicting processor performance. We
apply this technique to predict the CPI of in-order
architectures and validate it against the Itanium-2.
The Monte Carlo model uses micro-architecture
independent application characteristics, and cache,
branch predictor statistics to predict CPI with an
average error of less than 7\%. Since prediction is
achieved in a few seconds, the model can be used for
fast design space exploration that can efficiently cull
the space for cycle-accurate simulations. Besides
accurately predicting CPI, the model also breaks down
CPI into various components, where each component
quantifies the effect of a particular stall condition
(branch misprediction, cache miss, etc.) on overall
CPI. Such a CPI decomposition can help processor
designers quickly identify and resolve critical
performance bottlenecks",
acknowledgement = ack-nhfb,
fjournal = "IEEE Computer Architecture Letters",
journal-URL = "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208",
keywords = "branch predictor statistics; Computational modeling;
Computer architecture; CPI decomposition; design space
exploration; Error analysis; Itanium-2; Laboratories;
Mathematical analysis; memory architecture;
microarchitecture design; microarchitecture evaluation;
Monte Carlo methods; Monte Carlo simulation;
performance evaluation; Predictive models; Process
design; processor performance modeling; program
processors; Sampling methods; Space exploration",
}
@InProceedings{Takeda:2006:SMS,
author = "Shingo Takeda",
title = "A Security Monitoring System for {Grid} Computing",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_gridsecurity_takeda_osakauniv.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Tan:2006:TSC,
author = "Kenneth Tan",
title = "Technical and Scientific Computing Performance: Today
and Tomorrow",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium",
}
@InProceedings{Wichmann:2006:ULO,
author = "Mats D. Wichmann",
title = "An Update on {LSB} and Open Standards",
crossref = "Anonymous:2006:PGI",
pages = "??--??",
year = "2006",
bibdate = "Sat Oct 14 18:26:53 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/oct06/pres_pdf/gelato_ICE06oct_lsb_wichmann_intel.pdf",
acknowledgement = ack-nhfb,
keywords = "Intel IA-64; Itanium; LSB",
}
@InProceedings{Williams:2006:PCP,
author = "Samuel Williams and John Shalf and Leonid Oliker and
Shoaib Kamil and Parry Husbands and Katherine Yelick",
title = "The potential of the cell processor for scientific
computing",
crossref = "ACM:2006:PCC",
pages = "9--20",
year = "2006",
DOI = "https://doi.org/10.1145/1128022.1128027",
bibdate = "Tue Jun 20 07:02:14 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "The slowing pace of commodity microprocessor
performance improvements combined with ever-increasing
chip power demands has become of utmost concern to
computational scientists. As a result, the high
performance computing community is examining
alternative architectures that address the limitations
of modern cache-based designs. In this work, we examine
the potential of using the forthcoming STI Cell
processor as a building block for future high-end
computing systems. Our work contains several novel
contributions. First, we introduce a performance model
for Cell and apply it to several key scientific
computing kernels: dense matrix multiply, sparse matrix
vector multiply, stencil computations, and 1D/2D FFTs.
The difficulty of programming Cell, which requires
assembly level intrinsics for the best performance,
makes this model useful as an initial step in algorithm
design and evaluation. Next, we validate the accuracy
of our model by comparing results against published
hardware results, as well as our own implementations on
the Cell full system simulator. Additionally, we
compare Cell performance to benchmarks run on leading
superscalar (AMD Opteron), VLIW (Intel Itanium2), and
vector (Cray X1E) architectures. Our work also explores
several different mappings of the kernels and
demonstrates a simple and effective programming model
for Cell's unique architecture. Finally, we propose
modest microarchitectural modifications that could
significantly increase the efficiency of
double-precision calculations. Overall results
demonstrate the tremendous potential of the Cell
architecture for scientific computations in terms of
both raw performance and power efficiency.",
acknowledgement = ack-nhfb,
}
@Article{Hoflehner:2007:CCS,
author = "Gerolf F. Hoflehner and Darshan Desai and Daniel M.
Lavery and Alexandru Nicolau and Alexander V.
Veidenbaum",
title = "Comparative characterization of {SPEC CPU2000} and
{CPU2006} on {Itanium}{\reg} architecture",
journal = j-SIGMETRICS,
volume = "35",
number = "1",
pages = "361--362",
month = jun,
year = "2007",
CODEN = "????",
DOI = "https://doi.org/10.1145/1254882.1254930",
ISSN = "0163-5999 (print), 1557-9484 (electronic)",
bibdate = "Fri Jun 27 09:42:48 MDT 2008",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "Recently SPEC1 released the next generation of its CPU
benchmark, widely used by compiler writers and
architects for measuring processor performance. This
calls for characterization of the applications in SPEC
CPU2006 to guide the design of future microprocessors.
In addition, it necessitates assessing the change in
the characteristics of the applications from one suite
to another. Although similar studies using the retired
SPEC CPU benchmark suites have been done in the past,
to the best of our knowledge, a thorough
characterization of CPU2006 and its comparison with
CPU2000 has not been done so far. In this paper, we
present the above; specifically, we analyze IPC
(instructions per cycle), L1, L2 data cache misses and
branch prediction, especially in CPU2006.",
acknowledgement = ack-nhfb,
keywords = "branch prediction; caches; performance evaluation;
SPEC CPU benchmarks",
}
@Article{Karger:2007:PSL,
author = "Paul A. Karger",
title = "Performance and security lessons learned from
virtualizing the {Alpha} processor",
journal = j-COMP-ARCH-NEWS,
volume = "35",
number = "2",
pages = "392--401",
month = may,
year = "2007",
CODEN = "CANED2",
DOI = "https://doi.org/10.1145/1273440.1250711",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Tue Jun 17 11:48:43 MDT 2008",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "Virtualization has become much more important
throughout the computer industry both to improve
security and to support multiple workloads on the same
hardware with effective isolation between those
workloads. The most widely used chip architecture, the
Intel and AMD x86 processors, have begun to support
virtualization, but the initial implementations show
some limitations. This paper examines the
virtualization properties of the Alpha architecture
with particular emphasis on features that improve
performance and security. It shows how the Alpha's
features of PALcode, address space numbers, software
handling of translation buffer misses, lack of used and
modified bits, and secure handling of unpredictable
results all contribute to making virtualization of the
Alpha particularly easy. The paper then compares the
virtual architecture of the Alpha with Intel's and
AMD's virtualization approaches for x86. It also
comments briefly on Intel's virtualization technology
for Itanium, IBM's zSeries and pSeries hypervisors and
Sun's UltraSPARC virtualization. It particularly
identifies some differences between translation buffers
on x86 and translation buffers on VAX and Alpha that
can have adverse performance consequences.",
acknowledgement = ack-nhfb,
keywords = "hypervisors; security; virtual machine monitors;
virtualizability",
}
@Book{Mackin:2007:MSP,
author = "J. C. Mackin and Mike Hotek and Tobias Thernstr{\"o}m
and Shannon Horn",
title = "{MCITP} self-paced training kit (Exam 70-443):
designing a database server infrastructure using
{Microsoft SQL Server 2005}",
publisher = pub-MICROSOFT,
address = pub-MICROSOFT:adr,
pages = "xxxii + 708",
year = "2007",
ISBN = "0-7356-2173-X",
ISBN-13 = "978-0-7356-2173-2",
LCCN = "QA76.3 .M3224 2007",
bibdate = "Tue Oct 28 09:37:10 MDT 2008",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
z3950.loc.gov:7090/Voyager",
URL = "http://www.loc.gov/catdir/toc/fy0711/2006932079.html",
abstract = "Microsoft SQL Server 2005 Enterprise Edition
evaluation software (1 DVD-ROM (4 3/4 in.)). 180-day
limit on use. This disc contains x86, x64 and
Itanium-based software. Exam prep guide. Ace your
preparation for the skills measured by MCITP Exam
70-443 - and on the job. Work at your own pace through
a series of lessons and reviews that fully cover each
exam objective. Then, reinforce what you've learned by
applying your knowledge to real-world case scenarios
and practice exercises. This official Microsoft study
guide is designed to help you make the most of your
study time. Maximize your performance on the exam by
learning to: install, consolidate, and configure
multiple database instances; design tables, file
groups, and indexes for a physical database; develop
and implement security policies at the server,
database, and object levels; design, implement, and
configure clustering, log shipping, database mirroring,
and replication; and implement your plans for data
archiving, data backups, and disaster recovery. - Back
cover. Practice tests. Assess your skills with practice
tests on CD. You can work through hundreds of questions
using multiple testing modes to meet your specific
learning needs. You get detailed explanations for right
and wrong answers - including a customized learning
path that describes how and where to focus your
studies. - Back cover.",
acknowledgement = ack-nhfb,
remark = "Practice test questions on companion CD coauthored by
Tobias Thernstr{\"o}m and Shannon Horn.",
subject = "Electronic data processing personnel; Certification;
Microsoft software; Examinations; Study guides;
Databases; Design; Microsoft Windows server; SQL
server; Database management",
tableofcontents = "1. Planning a database server infrastructure \\
2. Deploying and consolidating multiple instances \\
3. Designing SQL server security in the enterprise \\
4. Designing database server security policies \\
5. Designing SQL server endpoints \\
6. Designing database security \\
7. Planning for high availability in the enterprise \\
8. Failover clustering \\
9. Database mirroring \\
10. Log shipping \\
11. Replication \\
12. Designing the physical database \\
13. Designing a data recovery strategy \\
14. Archiving database data\ldots{} disc 1. MCITP
self-paced training kit (exam 7-443) : designing a
database server infrastructure using Microsoft SQL
server 2005 \\
disc 2. Microsoft server 2005 enterprise edition
evaluation software",
}
@Article{Mouli:2007:FF,
author = "C. Mouli and W. Carriker",
title = "Future Fab",
journal = j-IEEE-SPECTRUM,
volume = "44",
number = "3",
pages = "38--43",
month = mar,
year = "2007",
CODEN = "IEESAM",
DOI = "https://doi.org/10.1109/MSPEC.2007.323431",
ISSN = "0018-9235 (print), 1939-9340 (electronic)",
ISSN-L = "0018-9235",
bibdate = "Sat Jan 18 12:29:46 2020",
bibsource = "http://www.math.utah.edu/pub/tex/bib/ieeespectrum2000.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
fjournal = "IEEE Spectrum",
journal-URL = "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
keywords = "chip-making process; Core 2 Duo processors; Data
mining; integrated circuit manufacture; Intel
microprocessors; Itanium processors; Manufacturing;
manufacturing execution system; manufacturing systems;
material handling; microprocessor chips; Pentium
processors; Process control; process control
automation; Resists; Software; software suite dubbed
automated manufacturing technology; tool control;
Transistors; XML",
}
@Article{Chen:2008:SSP,
author = "Haibo Chen and Xi Wu and Liwei Yuan and Binyu Zang and
Pen-chung Yew and Frederic T. Chong",
title = "From Speculation to Security: Practical and Efficient
Information Flow Tracking Using Speculative Hardware",
journal = j-COMP-ARCH-NEWS,
volume = "36",
number = "3",
pages = "401--412",
month = jun,
year = "2008",
CODEN = "CANED2",
DOI = "https://doi.org/10.1145/1394608.1382156",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
bibdate = "Wed Aug 6 08:35:03 MDT 2008",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "Dynamic information flow tracking (also known as taint
tracking) is an appealing approach to combat various
security attacks. However, the performance of
applications can severely degrade without hardware
support for tracking taints. This paper observes that
information flow tracking can be efficiently emulated
using deferred exception tracking in microprocessors
supporting speculative execution. Based on this
observation, we propose SHIFT, a low-overhead,
software-based dynamic information flow tracking system
to detect a wide range of attacks. The key idea is to
treat tainted state (describing untrusted data) as
speculative state (describing deferred exceptions).
SHIFT leverages existing architectural support for
speculative execution to track tainted state in
registers and needs to instrument only load and store
instructions to track tainted state in memory using a
bitmap, which results in significant performance
advantages. Moreover, by decoupling mechanisms for
taint tracking from security policies, SHIFT can detect
a wide range of exploits, including high-level semantic
attacks. We have implemented SHIFT using the Itanium
processor, which has support for deferred exceptions,
and by modifying GCC to instrument loads and stores. A
security assessment shows that SHIFT can detect both
low-level memory corruption exploits as well as
high-level semantic attacks with no false positives.
Performance measurements show that SHIFT incurs about
1\% overhead for server applications. The performance
slowdown for SPEC-INT2000 is 2.81X and 2.27X for
tracking at byte-level and word-level respectively.
Minor architectural improvements to the Itanium
processor (adding three simple instructions) can reduce
the performance slowdown down to 2.32X and 1.8X for
byte-level and word-level tracking, respectively.",
acknowledgement = ack-nhfb,
keywords = "deferred exception; dynamic information flow tracking;
speculative execution; taint tracking",
}
@Article{Rong:2008:RAS,
author = "Hongbo Rong and Alban Douillet and Guang R. Gao",
title = "Register allocation for software pipelined
multidimensional loops",
journal = j-TOPLAS,
volume = "30",
number = "4",
pages = "23:1--23:??",
month = jul,
year = "2008",
CODEN = "ATPSDT",
DOI = "https://doi.org/10.1145/1377492.1377498",
ISSN = "0164-0925 (print), 1558-4593 (electronic)",
bibdate = "Tue Aug 5 19:14:53 MDT 2008",
bibsource = "http://www.acm.org/pubs/contents/journals/toplas/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "This article investigates register allocation for
software pipelined multidimensional loops where the
execution of successive iterations from an {\em n\/}
-dimensional loop is overlapped. For single loop
software pipelining, the lifetimes of a loop variable
in successive iterations of the loop form a repetitive
pattern. An effective register allocation method is to
represent the pattern as a vector of lifetimes (or a
vector lifetime using Rau's terminology [Rau 1992]) and
map it to rotating registers. Unfortunately, the
software pipelined schedule of a multidimensional loop
is considerably more complex and so are the vector
lifetimes in it.\par
In this article, we develop a way to normalize and
represent the vector lifetimes, which captures their
complexity, while exposing their regularity that
enables a simple solution. The problem is formulated as
bin-packing of the multidimensional vector lifetimes on
the surface of a space-time cylinder. A metric, called
distance, is calculated either conservatively or
aggressively to guide the bin-packing process, so that
there is no overlapping between any two vector
lifetimes, and the register requirement is minimized.
This approach subsumes the classical register
allocation for software pipelined single loops as a
special case. The method has been implemented in the
ORC compiler and produced code for the IA-64
architecture. Experimental results show the
effectiveness. Several strategies for register
allocation are compared and analyzed.",
acknowledgement = ack-nhfb,
articleno = "23",
keywords = "register allocation; Software pipelining",
}
@Article{VanZee:2008:SPF,
author = "Field G. {Van Zee} and Paolo Bientinesi and Tze Meng
Low and Robert A. van de Geijn",
title = "Scalable parallelization of {FLAME} code via the
workqueuing model",
journal = j-TOMS,
volume = "34",
number = "2",
pages = "10:1--10:29",
month = mar,
year = "2008",
CODEN = "ACMSCU",
DOI = "https://doi.org/10.1145/1326548.1326552",
ISSN = "0098-3500 (print), 1557-7295 (electronic)",
bibdate = "Thu Jun 12 12:47:31 MDT 2008",
bibsource = "http://www.acm.org/pubs/contents/journals/toms/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "We discuss the OpenMP parallelization of linear
algebra algorithms that are coded using the Formal
Linear Algebra Methods Environment (FLAME) API. This
API expresses algorithms at a higher level of
abstraction, avoids the use loop and array indices, and
represents these algorithms as they are formally
derived and presented. We report on two implementations
of the workqueuing model, neither of which requires the
use of explicit indices to specify parallelism. The
first implementation uses the experimental taskq
pragma, which may influence the adoption of a similar
construct into OpenMP 3.0. The second workqueuing
implementation is domain-specific to FLAME but allows
us to illustrate the benefits of sorting tasks
according to their computational cost prior to parallel
execution. In addition, we discuss how scalable
parallelization of dense linear algebra algorithms via
OpenMP will require a two-dimensional partitioning of
operands much like a 2D data distribution is needed on
distributed memory architectures. We illustrate the
issues and solutions by discussing the parallelization
of the symmetric rank-$k$ update and report impressive
performance on an SGI system with 14 Itanium2
processors.",
acknowledgement = ack-nhfb,
articleno = "10",
keywords = "FLAME; OpenMP; parallel; scalability; SMP;
workqueuing",
}
@Article{Wang:2008:OSA,
author = "Li Wang and Xuejun Yang and Jingling Xue and Yu Deng
and Xiaobo Yan and Tao Tang and Quan Hoang Nguyen",
title = "Optimizing scientific application loops on stream
processors",
journal = j-SIGPLAN,
volume = "43",
number = "7",
pages = "161--170",
month = jul,
year = "2008",
CODEN = "SINODQ",
DOI = "https://doi.org/10.1145/1379023.1375679",
ISSN = "0362-1340 (print), 1523-2867 (print), 1558-1160
(electronic)",
ISSN-L = "0362-1340",
bibdate = "Wed Jun 18 11:05:54 MDT 2008",
bibsource = "http://portal.acm.org/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "This paper describes a graph coloring compiler
framework to allocate on-chip SRF(Stream Register File)
storage for optimizing scientific applications on
stream processors. Our framework consists of first
applying enabling optimizations such as loop unrolling
to expose stream reuse and opportunities for maximizing
parallelism, i.e., overlapping kernel execution and
memory transfers. Then the three SRF management tasks
are solved in a unified manner via graph coloring: (1)
placing streams in the SRF, (2) exploiting stream use,
and (3) maximizing parallelism. We evaluate the
performance of our compiler framework by actually
running nine representative scientific computing
kernels on our FT64 stream processor. Our preliminary
results show that compiler management achieves an
average speedup of 2.3x compared to First-Fit
allocation. In comparison with the performance results
obtained from running these benchmarks on Itanium 2, an
average speedup of 2.1x is observed.",
acknowledgement = ack-nhfb,
keywords = "data reuse; graph coloring; loop optimization;
prefetching; software-managed cache; stream processor;
streaming",
}
@Article{Quintana-Orti:2009:ULF,
author = "Enrique S. Quintana-Ort{\'\i} and Robert A. {Van De
Geijn}",
title = "Updating an {LU} Factorization with Pivoting",
journal = j-TOMS,
volume = "35",
number = "2",
pages = "11:1--11:16",
month = jul,
year = "2009",
CODEN = "ACMSCU",
DOI = "https://doi.org/10.1145/1377612.1377615",
ISSN = "0098-3500 (print), 1557-7295 (electronic)",
bibdate = "Tue Aug 5 18:13:00 MDT 2008",
bibsource = "http://www.acm.org/pubs/contents/journals/toms/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
abstract = "We show how to compute an LU factorization of a matrix
when the factors of a leading principle submatrix are
already known. The approach incorporates pivoting akin
to partial pivoting, a strategy we call {\em
incremental pivoting}. An implementation using the
Formal Linear Algebra Methods Environment (FLAME)
application programming interface (API) is described.
Experimental results demonstrate practical numerical
stability and high performance on an Intel Itanium2
processor-based server.",
acknowledgement = ack-nhfb,
articleno = "11",
keywords = "linear systems; LU factorization; pivoting; updating",
}
@Proceedings{IEEE:1997:HCI,
editor = "{IEEE}",
booktitle = "Hot Chips IX: Stanford University, Stanford,
California, August 24--26, 1997",
title = "Hot Chips {IX}: Stanford University, Stanford,
California, August 24--26, 1997",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "????",
year = "1997",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Mon Jan 08 05:05:12 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Proceedings{DeGroot:1998:PIS,
editor = "Doug DeGroot",
booktitle = "{Proceedings of the 25th International Symposium on
Computer Architecture, Barcelona, Spain, June 27--July
02, 1998}",
title = "{Proceedings of the 25th International Symposium on
Computer Architecture, Barcelona, Spain, June 27--July
02, 1998}",
publisher = pub-IEEE,
address = pub-IEEE:adr,
year = "1998",
ISBN = "0-8186-8491-7",
ISBN-13 = "978-0-8186-8491-3",
ISSN = "0163-5964 (print), 1943-5851 (electronic)",
LCCN = "????",
bibdate = "Thu Jun 09 18:59:59 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
keywords = "IMPACT EPIC; Intel IA-64; Itanium",
}
@Proceedings{ACM:1999:PASa,
editor = "ACM",
booktitle = "Proceedings of the ACM SIGPLAN '99 Conference on
Programming Language Design and Implementation (PLDI
'99), Atlanta, Georgia, 2--4 May 1999",
title = "Proceedings of the {ACM} {SIGPLAN} '99 Conference on
Programming Language Design and Implementation ({PLDI}
'99), Atlanta, Georgia, 2--4 May 1999",
volume = "34(5)",
publisher = pub-ACM,
address = pub-ACM:adr,
pages = "????",
year = "1999",
ISBN = "1-58113-094-5",
ISBN-13 = "978-1-58113-094-2",
LCCN = "????",
bibdate = "Thu Apr 27 07:12:05 2000",
bibsource = "http://www.acm.org/pubs/contents/proceedings/pldi/301122/index.html;
http://www.acm.org/pubs/contents/proceedings/pldi/301618/index.html;
http://www.cs.rutgers.edu/pldi99/program.html;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
series = j-SIGPLAN,
acknowledgement = ack-nhfb,
}
@Proceedings{IEEE:1999:HCS,
editor = "IEEE",
booktitle = "Hot Chips 11: Stanford University, Stanford,
California, August 15--17, 1999",
title = "Hot Chips 11: Stanford University, Stanford,
California, August 15--17, 1999",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "????",
year = "1999",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Mon Jan 08 05:26:43 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.hotchips.org/hotc11_index.html",
acknowledgement = ack-nhfb,
}
@Proceedings{Koren:1999:ISC,
editor = "Israel Koren and Peter Kornerup",
booktitle = "14th IEEE Symposium on Computer Arithmetic:
proceedings: April 14--16, 1999, Adelaide, Australia",
title = "14th {IEEE} Symposium on Computer Arithmetic:
proceedings: April 14--16, 1999, Adelaide, Australia",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "xi + 274",
year = "1999",
ISBN = "0-7803-5609-8, 0-7695-0116-8, 0-7695-0118-4",
ISBN-13 = "978-0-7803-5609-2, 978-0-7695-0116-1,
978-0-7695-0118-5",
ISSN = "1063-6889",
LCCN = "QA76.6 .S887 1999",
bibdate = "Mon Feb 7 07:28:26 MST 2000",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "IEEE Computer Society Order Number PR00116. IEEE Order
Plan Catalog Number 99CB36336.",
URL = "http://computer.org/conferen/home/arith/;
http://www.ecs.umass.edu/ece/arith14/program.html",
acknowledgement = ack-nhfb,
annote = "Also known as ARITH-14.",
source = "Computer arithmetic",
sponsor = "IEEE.",
}
@Proceedings{Aagaard:2000:TPH,
editor = "Mark Aagaard and John Harrison",
booktitle = "Theorem Proving in Higher Order Logics, 13th
International Conference, TPHOLs 2000, Portland,
Oregon, USA, August 14--18, 2000, Proceedings",
title = "Theorem Proving in Higher Order Logics, 13th
International Conference, {TPHOL}s 2000, Portland,
Oregon, {USA}, August 14--18, 2000, Proceedings",
volume = "1869",
publisher = pub-SV,
pages = "ix + 533",
year = "2000",
ISBN = "3-540-67863-8",
ISBN-13 = "978-3-540-67863-2",
LCCN = "QA267.A1 L43 no.1869; QA76.9.A96 T655 200",
bibdate = "Tue Feb 06 15:25:11 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
series = ser-LNCS,
acknowledgement = ack-nhfb,
}
@Proceedings{ACM:2000:PIS,
editor = "ACM",
booktitle = "Proceedings of the International Symposium on Physical
Design ({ISPD-00}), San Diego, {CA}, April 9--12,
2000",
title = "Proceedings of the International Symposium on Physical
Design ({ISPD-00}), San Diego, {CA}, April 9--12,
2000",
publisher = pub-ACM,
address = pub-ACM:adr,
year = "2000",
bibsource = "http://www.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Misc/MPG/ispd00.bib;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
}
@Proceedings{Carter:2000:LCP,
editor = "Larry Carter and Jeanne Ferrante",
booktitle = "Languages and compilers for parallel computing: 12th
International Workshop, {LCPC'99}, La Jolla, {CA},
{USA}, August 4--6, 1999; proceedings",
title = "Languages and compilers for parallel computing: 12th
International Workshop, {LCPC'99}, La Jolla, {CA},
{USA}, August 4--6, 1999; proceedings",
volume = "1863",
publisher = pub-SV,
address = pub-SV:adr,
pages = "xii + 500",
year = "2000",
ISBN = "3-540-67858-1",
ISBN-13 = "978-3-540-67858-8",
ISSN = "0302-9743 (print), 1611-3349 (electronic)",
LCCN = "QA76.58 .L36 2000",
bibdate = "Tue Feb 06 15:22:03 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
series = ser-LNCS,
acknowledgement = ack-nhfb,
keywords = "compilers (computer programs) --- congresses; parallel
processing (electronic computers) --- congresses;
programming languages (electronic computers) ---
congresses",
}
@Proceedings{IEEE:2000:HCS,
editor = "IEEE",
booktitle = "Hot Chips 12: Stanford University, Stanford,
California, August 13--15, 2000",
title = "Hot Chips 12: Stanford University, Stanford,
California, August 13--15, 2000",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "????",
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Mon Jan 08 05:26:43 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.hotchips.org/index12.html",
acknowledgement = ack-nhfb,
}
@Proceedings{NIST:2000:TAE,
editor = "{NIST}",
booktitle = "The Third {Advanced Encryption Standard} Candidate
Conference, April 13--14, 2000, New York, NY, USA",
title = "The Third {Advanced Encryption Standard} Candidate
Conference, April 13--14, 2000, New York, {NY}, {USA}",
publisher = pub-NIST,
address = pub-NIST:adr,
pages = "358",
year = "2000",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Tue Feb 06 15:28:26 2001",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://csrc.nist.gov/encryption/aes/round2/conf3/aes3conf.htm;
http://csrc.nist.gov/encryption/aes/round2/conf3/papers/AES3Proceedings-1.pdf;
http://csrc.nist.gov/encryption/aes/round2/conf3/papers/AES3Proceedings-2.pdf;
http://csrc.nist.gov/encryption/aes/round2/conf3/papers/AES3Proceedings-3.pdf;
http://csrc.nist.gov/encryption/aes/round2/conf3/papers/AES3Proceedings.pdf",
acknowledgement = ack-nhfb,
}
@Proceedings{USENIX:2000:PFW,
editor = "USENIX",
booktitle = "Proceedings of the First Workshop on Industrial
Experiences with Systems Software (WIESS 2000), October
22, 2000, Paradise Point Resort, San Diego, California,
USA",
title = "Proceedings of the First Workshop on Industrial
Experiences with Systems Software ({WIESS} 2000),
October 22, 2000, Paradise Point Resort, San Diego,
California, {USA}",
publisher = pub-USENIX,
address = pub-USENIX:adr,
pages = "84",
year = "2000",
ISBN = "1-880446-15-4",
ISBN-13 = "978-1-880446-15-7",
LCCN = "QA76.76.S95 W67 2000",
bibdate = "Wed Oct 16 05:52:48 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.usenix.org/publications/library/proceedings/osdi2000/wiess2000/",
acknowledgement = ack-nhfb,
}
@Proceedings{ACM:2001:SHP,
editor = "{ACM}",
booktitle = "SC2001: High Performance Networking and Computing.
Denver, CO, November 10--16, 2001",
title = "{SC2001}: High Performance Networking and Computing.
Denver, {CO}, November 10--16, 2001",
publisher = pub-ACM # " and " # pub-IEEE,
address = pub-ACM:adr # " and " # pub-IEEE:adr,
pages = "????",
year = "2001",
ISBN = "1-58113-293-X",
ISBN-13 = "978-1-58113-293-9",
LCCN = "????",
bibdate = "Thu Feb 21 18:29:36 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Proceedings{Kraemer:2001:SCV,
editor = "W. Kr{\"a}mer and J{\"u}rgen Wolff von Gudenberg",
booktitle = "Scientific Computing, Validated Numerics, Interval
Methods",
title = "Scientific Computing, Validated Numerics, Interval
Methods",
publisher = pub-KLUWER,
address = pub-KLUWER:adr,
pages = "ix + 398",
year = "2001",
ISBN = "0-306-46706-2",
ISBN-13 = "978-0-306-46706-6",
LCCN = "????",
bibdate = "Thu Mar 21 10:21:57 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "Scan 2000, the GAMM--IMACS International Symposium on
Scientific Computing, Computer Arithmetic, and
Validated Numerics and Interval 2000, the International
Conference on Interval Methods in Science and
Engineering were jointly held in Karlsruhe, September
19--22, 2000.",
price = "09.00 EUR / 95.00 USD / 66.50 GBP",
URL = "http://www.wkap.nl/prod/b/0-306-46706-2",
acknowledgement = ack-nhfb,
}
@Proceedings{IEEE:2002:IIS,
editor = "IEEE",
booktitle = "IEEE International Solid-State Circuits Conference
(ISSCC 2002), February 4--6, 2002, San Francisco
Marriott Hotel, San Francisco, CA, USA",
title = "{IEEE} International Solid-State Circuits Conference
({ISSCC} 2002), February 4--6, 2002, San Francisco
Marriott Hotel, San Francisco, {CA}, {USA}",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "????",
year = "2002",
ISBN = "????",
ISBN-13 = "????",
ISSN = "0743-1686",
LCCN = "????",
bibdate = "Fri Mar 22 09:00:54 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.sscs.org/isscc/",
acknowledgement = ack-nhfb,
xxnote = "Find exact title, and missing data??",
}
@Proceedings{USENIX:2002:PGT,
editor = "{USENIX}",
booktitle = "Proceedings of the General Track: 2002 USENIX Annual
Technical Conference, June 10--15, 2002, Monterey,
California, USA",
title = "Proceedings of the General Track: 2002 {USENIX} Annual
Technical Conference, June 10--15, 2002, Monterey,
California, {USA}",
publisher = pub-USENIX,
address = pub-USENIX:adr,
pages = "355",
year = "2002",
ISBN = "1-880446-00-6",
ISBN-13 = "978-1-880446-00-3",
LCCN = "QA76.8.U65 U84 2002",
bibdate = "Tue Oct 15 11:36:01 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.usenix.org/publications/library/proceedings/usenix02/",
acknowledgement = ack-nhfb,
}
@Proceedings{Anonymous:2003:CRN,
editor = "Anonymous",
booktitle = "5th Conference on Real Numbers and Computers 2003 ---
RNC5, Lyon, France, September 2003",
title = "5th Conference on Real Numbers and Computers 2003 ---
{RNC5}, Lyon, France, September 2003",
publisher = "????",
address = "????",
pages = "????",
year = "2003",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Sat Jun 25 14:57:33 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Book{Hennessy:2003:CAQ,
author = "John L. Hennessy and David A. Patterson",
booktitle = "Computer Architecture\emdash {A} Quantitative
Approach",
title = "Computer Architecture\emdash {A} Quantitative
Approach",
publisher = pub-MORGAN-KAUFMANN,
address = pub-MORGAN-KAUFMANN:adr,
edition = "Third",
pages = "xxi + 883 + A-87 + B-42 + C-1 + D-1 + E-1 + F-1 + G-1
+ H-1 + I-1 + R-22 + I-44",
year = "2003",
ISBN = "1-55860-596-7",
ISBN-13 = "978-1-55860-596-1",
LCCN = "QA76.9.A73 P377 2003",
bibdate = "Thu Sep 12 15:26:03 2002",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
price = "US\$89.95",
URL = "http://www.mkp.com/books_catalog/catalog.asp?ISBN=1-55860-596-7;
http://www.mkp.com/CA3",
}
@Proceedings{IEEE:2003:PCI,
editor = "{IEEE}",
booktitle = "{Proceedings of the 2003 CGO: the International
Symposium on Code Generation and Optimization; March
23--26, 2003, Fisherman's Wharf, San Francisco, CA,
with special emphasis on feedback-directed and runtime
optimization}",
title = "{Proceedings of the 2003 CGO: the International
Symposium on Code Generation and Optimization; March
23--26, 2003, Fisherman's Wharf, San Francisco, CA,
with special emphasis on feedback-directed and runtime
optimization}",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "xv + 347",
year = "2003",
ISBN = "0-7695-1913-X",
ISBN-13 = "978-0-7695-1913-5",
LCCN = "????",
bibdate = "Thu Jun 09 18:51:49 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "ACM Order No. 530033.",
acknowledgement = ack-nhfb,
keywords = "EPIC; Intel IA-64; Itanium",
}
@Proceedings{ACM:2004:SHP,
editor = "{ACM}",
booktitle = "{SC 2004: High Performance Computing, Networking and
Storage: Bridging communities: Proceedings of the
IEEE\slash ACM Supercomputing 2004 Conference,
Pittsburgh, PA, November 6--12, 2004}",
title = "{SC 2004: High Performance Computing, Networking and
Storage: Bridging communities: Proceedings of the
IEEE\slash ACM Supercomputing 2004 Conference,
Pittsburgh, PA, November 6--12, 2004}",
publisher = pub-ACM # " and " # pub-IEEE,
address = pub-ACM:adr # " and " # pub-IEEE:adr,
pages = "????",
year = "2004",
ISBN = "0-7695-2153-3",
ISBN-13 = "978-0-7695-2153-4",
LCCN = "????",
bibdate = "Tue Dec 27 08:08:01 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
}
@Proceedings{IEEE:2004:PIS,
editor = "IEEE",
booktitle = "{Proceedings: 37th International Symposium on
Microarchitecture, MICRO-37: 4--8 December 2004,
Portland, Oregon}",
title = "{Proceedings: 37th International Symposium on
Microarchitecture, MICRO-37: 4--8 December 2004,
Portland, Oregon}",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "xiii + 367",
year = "2004",
ISBN = "0-7695-2126-6",
ISBN-13 = "978-0-7695-2126-8",
ISSN = "1072-4451",
LCCN = "QA76.9.A73",
bibdate = "Thu Jun 09 19:05:06 2005",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
melvyl.cdlib.org:210/CDL90",
note = "IEEE Computer Society Order Number P2126. ACM Order
Number 520040.",
acknowledgement = ack-nhfb,
}
@Proceedings{IEEE:2005:PIS,
editor = "{IEEE}",
booktitle = "{Proceedings of the 17th IEEE Symposium on Computer
Arithmetic, ARITH-17, June 27--29, 2005, Cape Cod,
Massachusetts, USA}",
title = "{Proceedings of the 17th IEEE Symposium on Computer
Arithmetic, ARITH-17, June 27--29, 2005, Cape Cod,
Massachusetts, USA}",
publisher = pub-IEEE,
address = pub-IEEE:adr,
pages = "????",
year = "2005",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Tue Jun 21 19:02:16 2005",
bibsource = "http://arith17.polito.it/;
http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
acknowledgement = ack-nhfb,
xxnote = "Not yet published: check editor??",
}
@Proceedings{ACM:2006:PCC,
editor = "{ACM}",
booktitle = "{Proceedings of the 3rd conference on Computing
Frontiers, May 3--5, 2006, Ischia, Italy}",
title = "{Proceedings of the 3rd conference on Computing
Frontiers, May 3--5, 2006, Ischia, Italy}",
publisher = pub-ACM,
address = pub-ACM:adr,
year = "2006",
ISBN = "1-59593-302-6",
ISBN-13 = "978-1-59593-302-7",
LCCN = "????",
bibdate = "Tue Jun 20 06:45:04 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
note = "ACM order number 104060.",
acknowledgement = ack-nhfb,
}
@Proceedings{Anonymous:2006:PGI,
editor = "Anonymous",
title = "{Proceedings of Gelato ICE: Itanium Conference and
Expo: Spotlighting Linux on Itanium-based Platforms,
October 1--4, 2006, Biopolis, Singapore}",
pages = "????",
year = "2006",
ISBN = "????",
ISBN-13 = "????",
LCCN = "????",
bibdate = "Sat Oct 14 18:23:38 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib",
URL = "http://www.ice.gelato.org/;
http://www.ice.gelato.org/about/oct06_presentations.php",
acknowledgement = ack-nhfb,
}
@Book{Hennessy:2006:CAQ,
author = "John L. Hennessy and David A. Patterson and Andrea C.
Arpaci-Dusseau and others",
booktitle = "Computer Architecture: A Quantitative Approach",
title = "Computer Architecture: {A} Quantitative Approach",
publisher = pub-MORGAN-KAUFMANN,
address = pub-MORGAN-KAUFMANN:adrbo,
edition = "Fourth",
pages = "????",
year = "2006",
ISBN = "0-12-370490-1 (paperback)",
ISBN-13 = "978-0-12-370490-0 (paperback)",
LCCN = "QA76.9.A73 P377 2006",
bibdate = "Sat Sep 2 10:10:32 MDT 2006",
bibsource = "http://www.math.utah.edu/pub/tex/bib/intel-ia-64.bib;
z3950.loc.gov:7090/Voyager",
URL = "http://www.loc.gov/catdir/enhancements/fy0665/2006024358-d.html;
http://www.loc.gov/catdir/toc/ecip0618/2006024358.html",
acknowledgement = ack-nhfb,
subject = "Computer architecture",
}
