# bibtab

bibtype: article
filename: fparith.bib
label: Daneshbeh:2005:CUB
author: Amir K. Daneshbeh and M. Anwar Hasan
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 370--380
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.35
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Amir K. Daneshbeh and M. Anwar Hasan
title:
A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over $ mathrm GF(2^m) $

URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0370abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0370.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0370.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388201.pdf?isnumber=30205&prod=JNL&arnumber=1388201&arSt=+370&ared=+380&arAuthor=Daneshbeh%2C+A.K.%3B+Hasan%2C+M.A.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388201&count=13&index=12; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388201

rawtitle:
A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over {$ \mathrm {GF}(2^m) $}

entry:
@Article{Daneshbeh:2005:CUB,
  author =       "Amir K. Daneshbeh and M. Anwar Hasan",
  title =        "A Class of Unidirectional Bit Serial Systolic
                 Architectures for Multiplicative Inversion and Division
                 over {$ \mathrm {GF}(2^m) $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "370--380",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.35",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0370abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0370.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0370.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388201.pdf?isnumber=30205&prod=JNL&arnumber=1388201&arSt=+370&ared=+380&arAuthor=Daneshbeh%2C+A.K.%3B+Hasan%2C+M.A.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388201&count=13&index=12;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388201",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: article
filename: fparith.bib
label: Danysh:2005:AIV
author: Albert Danysh and Dimitri Tan
title: Architecture and Implementation of a Vector / SIMD Multiply-Accumulate Unit
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 284--293
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.41
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Albert Danysh and Dimitri Tan
rawtitle: Architecture and Implementation of a Vector\slash {SIMD} Multiply-Accumulate Unit
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0284abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0284.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0284.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388193.pdf?isnumber=30205&prod=JNL&arnumber=1388193&arSt=+284&ared=+293&arAuthor=Danysh%2C+A.%3B+Tan%2C+D.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388193&count=13&index=4; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388193

entry:
@Article{Danysh:2005:AIV,
  author =       "Albert Danysh and Dimitri Tan",
  title =        "Architecture and Implementation of a Vector\slash
                 {SIMD} Multiply-Accumulate Unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "284--293",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.41",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0284abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0284.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0284.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388193.pdf?isnumber=30205&prod=JNL&arnumber=1388193&arSt=+284&ared=+293&arAuthor=Danysh%2C+A.%3B+Tan%2C+D.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388193&count=13&index=4;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388193",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: manual
filename: fparith.bib
label: Daramy-Loirat:2005:CLL
title: CR-LIBM: a library of correctly rounded elementary functions in double-precision
organization: Laboratoire de l'Informatique du Parallelisme
address: Lyon, France
pages: 138
day: 16
month: sep
monthnumber: 9
year: 2005
bibdate: Thu Dec 15 16:27:30 2005
bibsource: http://lipforge.ens-lyon.fr/projects/crlibm/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.12.15 16:27:30 ???
URL: http://lipforge.ens-lyon.fr/frs/download.php/11/crlibm.pdf
acknowledgement: ack-nhfb
rawtitle: {CR-LIBM}: a library of correctly rounded elementary functions in double-precision
author:
Catherine Daramy-Loirat and David Defour and Florent de Dinechin and Matthieu Gallet and Nicolas Gast and Jean-Michel Muller

abstract:
The crlibm project aims at developing a portable, proven, correctly rounded, and efficient mathematical library (tt libm) for double precision. Current libm implementations do not always return the floating-point number that is closest to the exact mathematical result. As a consequence, different libm implementations will return different results for the same input, which prevents full portability of floating-point applications. In addition, few libraries support but the round-to-nearest mode of the IEEE754/IEC 60559 standard for floating-point arithmetic (hereafter usually referred to as the IEEE-754 standard). crlibm provides the four rounding modes: To nearest, to $ + infty $ , to $ - infty $ and to zero.

rawabstract:
The crlibm project aims at developing a portable, proven, correctly rounded, and efficient mathematical library ({\tt libm}) for double precision. Current libm implementations do not always return the floating-point number that is closest to the exact mathematical result. As a consequence, different libm implementations will return different results for the same input, which prevents full portability of floating-point applications. In addition, few libraries support but the round-to-nearest mode of the IEEE754/IEC 60559 standard for floating-point arithmetic (hereafter usually referred to as the IEEE-754 standard). crlibm provides the four rounding modes: To nearest, to $ + \infty $ , to $ - \infty $ and to zero.

rawauthor:
Catherine Daramy-Loirat and David Defour and Florent de Dinechin and Matthieu Gallet and Nicolas Gast and Jean-Michel Muller

entry:
@Manual{Daramy-Loirat:2005:CLL,
  author =       "Catherine Daramy-Loirat and David Defour and Florent
                 de Dinechin and Matthieu Gallet and Nicolas Gast and
                 Jean-Michel Muller",
  title =        "{CR-LIBM}: a library of correctly rounded elementary
                 functions in double-precision",
  organization = "Laboratoire de l'Informatique du Parall{\'e}lisme",
  address =      "Lyon, France",
  pages =        "138",
  day =          "16",
  month =        sep,
  year =         "2005",
  bibdate =      "Thu Dec 15 16:27:30 2005",
  bibsource =    "http://lipforge.ens-lyon.fr/projects/crlibm/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://lipforge.ens-lyon.fr/frs/download.php/11/crlibm.pdf",
  abstract =     "The crlibm project aims at developing a portable,
                 proven, correctly rounded, and efficient mathematical
                 library ({\tt libm}) for double precision. Current libm
                 implementations do not always return the floating-point
                 number that is closest to the exact mathematical
                 result. As a consequence, different libm
                 implementations will return different results for the
                 same input, which prevents full portability of
                 floating-point applications. In addition, few libraries
                 support but the round-to-nearest mode of the
                 IEEE754/IEC 60559 standard for floating-point
                 arithmetic (hereafter usually referred to as the
                 IEEE-754 standard). crlibm provides the four rounding
                 modes: To nearest, to $ + \infty $ , to $ - \infty $
                 and to zero.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Daumas:2005:GPU
author: Marc Daumas and Guillaume Melquiond and Cesar Munoz
title: Guaranteed Proofs Using Interval Arithmetic
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-155.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Marc Daumas and Guillaume Melquiond and C{\'e}sar Mu{\~n}oz
rawtitle: Guaranteed Proofs Using Interval Arithmetic
abstract:
This paper presents a set of tools for mechanical reasoning of numerical bounds using interval arithmetic. The tools implement two techniques for reducing decorrelation: interval splitting and Taylor's series expansions. Although the tools are designed for the proof assistant system PVS, expertise on PVS is not required. The ultimate goal of the tools is to provide guaranteed proofs of numerical properties with a minimal human-theorem prover interaction.

rawabstract:
This paper presents a set of tools for mechanical reasoning of numerical bounds using interval arithmetic. The tools implement two techniques for reducing decorrelation: interval splitting and Taylor's series expansions. Although the tools are designed for the proof assistant system PVS, expertise on PVS is not required. The ultimate goal of the tools is to provide guaranteed proofs of numerical properties with a minimal human-theorem prover interaction.

entry:
@InProceedings{Daumas:2005:GPU,
  author =       "Marc Daumas and Guillaume Melquiond and C{\'e}sar
                 Mu{\~n}oz",
  title =        "Guaranteed Proofs Using Interval Arithmetic",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-155.pdf",
  abstract =     "This paper presents a set of tools for mechanical
                 reasoning of numerical bounds using interval
                 arithmetic. The tools implement two techniques for
                 reducing decorrelation: interval splitting and Taylor's
                 series expansions. Although the tools are designed for
                 the proof assistant system PVS, expertise on PVS is not
                 required. The ultimate goal of the tools is to provide
                 guaranteed proofs of numerical properties with a
                 minimal human-theorem prover interaction.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: deDinechin:2005:MTM
author: Florent de Dinechin and Arnaud Tisserand
title: Multipartite Table Methods
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 319--330
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.54
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Florent de Dinechin and Arnaud Tisserand
rawtitle: Multipartite Table Methods
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0319abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0319.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0319.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388196.pdf?isnumber=30205&prod=JNL&arnumber=1388196&arSt=+319&ared=+330&arAuthor=de+Dinechin%2C+F.%3B+Tisserand%2C+A.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388196&count=13&index=7; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388196

abstract:
A unified view of most previous table-lookup-and-addition methods (bipartite tables, SBTM, STAM, and multipartite methods) is presented. This unified view allows a more accurate computation of the error entailed by these methods, which enables a wider design space exploration, leading to tables smaller than the best previously published ones by up to 50 percent. The synthesis of these multipartite architectures on Virtex FPGAs is also discussed. Compared to other methods involving multipliers, the multipartite approach offers the best speed/area tradeoff for precisions up to 16 bits. A reference implementation is available at http://www.ens-lyon.fr/LIP/Arenaire/.

rawabstract:
A unified view of most previous table-lookup-and-addition methods (bipartite tables, SBTM, STAM, and multipartite methods) is presented. This unified view allows a more accurate computation of the error entailed by these methods, which enables a wider design space exploration, leading to tables smaller than the best previously published ones by up to 50 percent. The synthesis of these multipartite architectures on Virtex FPGAs is also discussed. Compared to other methods involving multipliers, the multipartite approach offers the best speed/area tradeoff for precisions up to 16 bits. A reference implementation is available at http://www.ens-lyon.fr/LIP/Arenaire/.

entry:
@Article{deDinechin:2005:MTM,
  author =       "Florent de Dinechin and Arnaud Tisserand",
  title =        "Multipartite Table Methods",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "319--330",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.54",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0319abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0319.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0319.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388196.pdf?isnumber=30205&prod=JNL&arnumber=1388196&arSt=+319&ared=+330&arAuthor=de+Dinechin%2C+F.%3B+Tisserand%2C+A.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388196&count=13&index=7;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388196",
  abstract =     "A unified view of most previous
                 table-lookup-and-addition methods (bipartite tables,
                 SBTM, STAM, and multipartite methods) is presented.
                 This unified view allows a more accurate computation of
                 the error entailed by these methods, which enables a
                 wider design space exploration, leading to tables
                 smaller than the best previously published ones by up
                 to 50 percent. The synthesis of these multipartite
                 architectures on Virtex FPGAs is also discussed.
                 Compared to other methods involving multipliers, the
                 multipartite approach offers the best speed/area
                 tradeoff for precisions up to 16 bits. A reference
                 implementation is available at
                 http://www.ens-lyon.fr/LIP/Arenaire/.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2005:TPU
author: Florent de Dinechin and Alexey Ershov and Nicolas Gast
title: Towards the Post-ultimate tt libm
crossref: Montuschi:2005:PIS
pages: 288--295
year: 2005
DOI: https://doi.org/10.1109/ARITH.2005.46
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-165.pdf
keywords: ARITH-17; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin and Alexey Ershov and Nicolas Gast
rawtitle: Towards the Post-ultimate {\tt libm}
abstract:
This article presents advances on the subject of correctly rounded elementary functions since the publication of the tt libultim mathematical library developed by Ziv at IBM. This library showed that the average performance and memory overhead of correct rounding could be made negligible. However, the worst-case overhead was still a factor 1000 or more. It is shown here that, with current processor technology, this worst-case overhead can be kept within a factor of 2 to 10 of current best libms. This low overhead has very positive consequences on the techniques for implementing and proving correctly rounded functions, which are also studied. These results lift the last technical obstacles to a generalisation of (at least some) correctly rounded double precision elementary functions.

rawabstract:
This article presents advances on the subject of correctly rounded elementary functions since the publication of the {\tt libultim} mathematical library developed by Ziv at IBM. This library showed that the average performance and memory overhead of correct rounding could be made negligible. However, the worst-case overhead was still a factor 1000 or more. It is shown here that, with current processor technology, this worst-case overhead can be kept within a factor of 2 to 10 of current best libms. This low overhead has very positive consequences on the techniques for implementing and proving correctly rounded functions, which are also studied. These results lift the last technical obstacles to a generalisation of (at least some) correctly rounded double precision elementary functions.

entry:
@InProceedings{deDinechin:2005:TPU,
  author =       "Florent de Dinechin and Alexey Ershov and Nicolas
                 Gast",
  title =        "Towards the Post-ultimate {\tt libm}",
  crossref =     "Montuschi:2005:PIS",
  pages =        "288--295",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ARITH.2005.46",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-165.pdf",
  abstract =     "This article presents advances on the subject of
                 correctly rounded elementary functions since the
                 publication of the {\tt libultim} mathematical library
                 developed by Ziv at IBM. This library showed that the
                 average performance and memory overhead of correct
                 rounding could be made negligible. However, the
                 worst-case overhead was still a factor 1000 or more. It
                 is shown here that, with current processor technology,
                 this worst-case overhead can be kept within a factor of
                 2 to 10 of current best libms. This low overhead has
                 very positive consequences on the techniques for
                 implementing and proving correctly rounded functions,
                 which are also studied. These results lift the last
                 technical obstacles to a generalisation of (at least
                 some) correctly rounded double precision elementary
                 functions.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; correct rounding; floating-point
                 arithmetic",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Dou:2005:BFP
author: Y. Dou and S. Vassiliadis and G. K. Kuzmanov and G. N. Gaydadjiev
title: 64-bit floating-point FPGA matrix multiplication
crossref: ACM:2005:FAS
pages: 86--95
year: 2005
DOI: https://doi.org/10.1145/1046192.1046204
bibdate: Sat Oct 9 12:38:44 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:38:44 ???
acknowledgement: ack-nhfb
rawauthor: Y. Dou and S. Vassiliadis and G. K. Kuzmanov and G. N. Gaydadjiev
rawtitle: 64-bit floating-point {FPGA} matrix multiplication
abstract:
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algorithm, applicable for an arbitrary matrix size is proposed. The algorithm potentially enables optimum performance by exploiting the data locality and reusability incurred by the general matrix multiplication scheme and considering the limitations of the I/O bandwidth and the local storage volume. We implement a scalable linear array of processing elements (PE) supporting the proposed algorithm in the Xilinx Virtex II Pro technology. Synthesis results confirm a superior performance-area ratio compared to related recent works. Assuming the same FPGA chip, the same amount of local memory, and the same I/O bandwidth, our design outperforms related proposals by at least 1.7X and up to 18X consuming the least reconfigurable resources. A total of 39 PEs can be integrated into the xc2vp125-7 FPGA, reaching performance of, e.g., 15.6 GFLOPS with 1600 KB local memory and 400 MB/s external memory bandwidth.

rawabstract:
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algorithm, applicable for an arbitrary matrix size is proposed. The algorithm potentially enables optimum performance by exploiting the data locality and reusability incurred by the general matrix multiplication scheme and considering the limitations of the I/O bandwidth and the local storage volume. We implement a scalable linear array of processing elements (PE) supporting the proposed algorithm in the Xilinx Virtex II Pro technology. Synthesis results confirm a superior performance-area ratio compared to related recent works. Assuming the same FPGA chip, the same amount of local memory, and the same I/O bandwidth, our design outperforms related proposals by at least 1.7X and up to 18X consuming the least reconfigurable resources. A total of 39 PEs can be integrated into the xc2vp125-7 FPGA, reaching performance of, e.g., 15.6 GFLOPS with 1600 KB local memory and 400 MB/s external memory bandwidth.

entry:
@InProceedings{Dou:2005:BFP,
  author =       "Y. Dou and S. Vassiliadis and G. K. Kuzmanov and G. N.
                 Gaydadjiev",
  title =        "64-bit floating-point {FPGA} matrix multiplication",
  crossref =     "ACM:2005:FAS",
  pages =        "86--95",
  year =         "2005",
  DOI =          "https://doi.org/10.1145/1046192.1046204",
  bibdate =      "Sat Oct 9 12:38:44 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We introduce a 64-bit ANSI/IEEE Std 754-1985 floating
                 point design of a hardware matrix multiplier optimized
                 for FPGA implementations. A general block matrix
                 multiplication algorithm, applicable for an arbitrary
                 matrix size is proposed. The algorithm potentially
                 enables optimum performance by exploiting the data
                 locality and reusability incurred by the general matrix
                 multiplication scheme and considering the limitations
                 of the I/O bandwidth and the local storage volume. We
                 implement a scalable linear array of processing
                 elements (PE) supporting the proposed algorithm in the
                 Xilinx Virtex II Pro technology. Synthesis results
                 confirm a superior performance-area ratio compared to
                 related recent works. Assuming the same FPGA chip, the
                 same amount of local memory, and the same I/O
                 bandwidth, our design outperforms related proposals by
                 at least 1.7X and up to 18X consuming the least
                 reconfigurable resources. A total of 39 PEs can be
                 integrated into the xc2vp125-7 FPGA, reaching
                 performance of, e.g., 15.6 GFLOPS with 1600 KB local
                 memory and 400 MB/s external memory bandwidth.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Efstathiou:2005:EDM
author: C. Efstathiou and H. T. Vergos and G. Dimitrakopoulos and D. Nikolos
title: Efficient diminished-$1$ modulo $ 2^n + 1 $ multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 4
pages: 491--496
month: apr
monthnumber: 4
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.63
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:16 MDT 2011
bibtimestamp: 2011.07.04 16:17:16 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1401868
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: C. Efstathiou and H. T. Vergos and G. Dimitrakopoulos and D. Nikolos
rawtitle: Efficient diminished-$1$ modulo $ 2^n + 1 $ multipliers
entry:
@Article{Efstathiou:2005:EDM,
  author =       "C. Efstathiou and H. T. Vergos and G. Dimitrakopoulos
                 and D. Nikolos",
  title =        "Efficient diminished-$1$ modulo $ 2^n + 1 $
                 multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "4",
  pages =        "491--496",
  month =        apr,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.63",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:16 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1401868",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Eggert:2005:PEN
author: P. R. Eggert and D. S. Parker
title: Perturbing and evaluating numerical programs without recompilation --- the wonglediff way
journal: j-SPE
volume: 35
number: 4
pages: 313--322
day: 10
month: apr
monthnumber: 4
year: 2005
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.637
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Sat Apr 16 07:26:37 MDT 2005
bibtimestamp: 2005.04.16 07:26:37 MDT
fjournal: Software---Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 21 Dec 2004
rawauthor: P. R. Eggert and D. S. Parker
rawtitle: Perturbing and evaluating numerical programs without recompilation --- the wonglediff way
bibsource:
http://www.interscience.wiley.com/jpages/0038-0644; http://www3.interscience.wiley.com/journalfinder.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
wonglediff is a program that tests the sensitivity of arbitrary program executables or processes to changes that are introduced by a process that runs in parallel. On Unix and Linux kernels, wonglediff creates a supervisor process that runs applications and, on the fly, introduces desired changes to their process state. When execution terminates, it then summarizes the resulting changes in the output files. The technique employed has a variety of uses. This paper describes an implementation of wonglediff that checks the sensitivity of programs to random changes in the floating-point rounding modes. It runs a program several times, wongling it each time: randomly toggling the IEEE-754 rounding mode of the program as it executes. By comparing the resulting output, one gets a poor man's numerical stability analysis for the program. Although the analysis does not give any kind of guarantee about a program's stability, it can reveal genuine instability, and it does serve as a particularly useful and revealing idiot light. In our implementation, differences among the output files from the program's multiple runs are summarized in a report. This report is in fact an HTML version of the output file, with inline mark-up summarizing individual differences among the multiple instances. When viewed with a browser, the differences can be highlighted or rendered in many different ways.

keywords:
diff; IEEE-754 floating point arithmetic; numerical instability checking; random rounding; rounding modes; sensitivity analysis

rawabstract:
wonglediff is a program that tests the sensitivity of arbitrary program executables or processes to changes that are introduced by a process that runs in parallel. On Unix and Linux kernels, wonglediff creates a supervisor process that runs applications and, on the fly, introduces desired changes to their process state. When execution terminates, it then summarizes the resulting changes in the output files. The technique employed has a variety of uses. This paper describes an implementation of wonglediff that checks the sensitivity of programs to random changes in the floating-point rounding modes. It runs a program several times, wongling it each time: randomly toggling the IEEE-754 rounding mode of the program as it executes. By comparing the resulting output, one gets a poor man's numerical stability analysis for the program. Although the analysis does not give any kind of guarantee about a program's stability, it can reveal genuine instability, and it does serve as a particularly useful and revealing idiot light. In our implementation, differences among the output files from the program's multiple runs are summarized in a report. This report is in fact an HTML version of the output file, with inline mark-up summarizing individual differences among the multiple instances. When viewed with a browser, the differences can be highlighted or rendered in many different ways.

entry:
@Article{Eggert:2005:PEN,
  author =       "P. R. Eggert and D. S. Parker",
  title =        "Perturbing and evaluating numerical programs without
                 recompilation --- the wonglediff way",
  journal =      j-SPE,
  volume =       "35",
  number =       "4",
  pages =        "313--322",
  day =          "10",
  month =        apr,
  year =         "2005",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.637",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Sat Apr 16 07:26:37 MDT 2005",
  bibsource =    "http://www.interscience.wiley.com/jpages/0038-0644;
                 http://www3.interscience.wiley.com/journalfinder.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "wonglediff is a program that tests the sensitivity of
                 arbitrary program executables or processes to changes
                 that are introduced by a process that runs in parallel.
                 On Unix and Linux kernels, wonglediff creates a
                 supervisor process that runs applications and, on the
                 fly, introduces desired changes to their process state.
                 When execution terminates, it then summarizes the
                 resulting changes in the output files. The technique
                 employed has a variety of uses. This paper describes an
                 implementation of wonglediff that checks the
                 sensitivity of programs to random changes in the
                 floating-point rounding modes. It runs a program
                 several times, wongling it each time: randomly toggling
                 the IEEE-754 rounding mode of the program as it
                 executes. By comparing the resulting output, one gets a
                 poor man's numerical stability analysis for the
                 program. Although the analysis does not give any kind
                 of guarantee about a program's stability, it can reveal
                 genuine instability, and it does serve as a
                 particularly useful and revealing idiot light. In our
                 implementation, differences among the output files from
                 the program's multiple runs are summarized in a report.
                 This report is in fact an HTML version of the output
                 file, with inline mark-up summarizing individual
                 differences among the multiple instances. When viewed
                 with a browser, the differences can be highlighted or
                 rendered in many different ways.",
  acknowledgement = ack-nhfb,
  fjournal =     "Software---Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  keywords =     "diff; IEEE-754 floating point arithmetic; numerical
                 instability checking; random rounding; rounding modes;
                 sensitivity analysis",
  onlinedate =   "21 Dec 2004",
}


bibtype: article
filename: fparith.bib
label: Eleftheriou:2005:SFF
author: M. Eleftheriou and B. G. Fitch and A. Rayshubskiy and T. J. C. Ward and R. S. Germain
journal: j-IBM-JRD
volume: 49
number: 2/3
pages: 457--464
year: 2005
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Wed Jun 1 08:14:41 MDT 2005
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.01 08:14:41 MDT
URL: http://www.research.ibm.com/journal/rd/492/eleftheriou.pdf
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: M. Eleftheriou and B. G. Fitch and A. Rayshubskiy and T. J. C. Ward and R. S. Germain
title:
Scalable framework for $3$D FFTs on the Blue Gene/L supercomputer: Implementation and early performance measurements

abstract:
This paper presents results on a communications-intensive kernel, the three-dimensional fast Fourier transform (3D FFT), running on the 2,048-node Blue Gene/L (BG/L) prototype. Two implementations of the volumetric FFT algorithm were characterized, one built on the Message Passing Interface library and another built on an active packet Application Program Interface supported by the hardware bring-up environment, the BG/L advanced diagnostics environment. Preliminary performance experiments on the BG/L prototype indicate that both of our implementations scale well up to 1,024 nodes for $3$D FFTs of size $ 128 time 128 times 128 $. The performance of the volumetric FFT is also compared with that of the Fastest Fourier Transform in the West (FFTW) library. In general, the volumetric FFT outperforms a port of the FFTW Version 2.1.5 library on large-node-count partitions.

rawabstract:
This paper presents results on a communications-intensive kernel, the three-dimensional fast Fourier transform (3D FFT), running on the 2,048-node Blue Gene/L (BG/L) prototype. Two implementations of the volumetric FFT algorithm were characterized, one built on the Message Passing Interface library and another built on an active packet Application Program Interface supported by the hardware bring-up environment, the BG/L advanced diagnostics environment. Preliminary performance experiments on the BG/L prototype indicate that both of our implementations scale well up to 1,024 nodes for $3$D FFTs of size $ 128 \time 128 \times 128 $. The performance of the volumetric FFT is also compared with that of the Fastest Fourier Transform in the West (FFTW) library. In general, the volumetric FFT outperforms a port of the FFTW Version 2.1.5 library on large-node-count partitions.

rawtitle:
Scalable framework for {$3$D} {FFTs} on the {Blue Gene/L} supercomputer: Implementation and early performance measurements

entry:
@Article{Eleftheriou:2005:SFF,
  author =       "M. Eleftheriou and B. G. Fitch and A. Rayshubskiy and
                 T. J. C. Ward and R. S. Germain",
  title =        "Scalable framework for {$3$D} {FFTs} on the {Blue
                 Gene/L} supercomputer: Implementation and early
                 performance measurements",
  journal =      j-IBM-JRD,
  volume =       "49",
  number =       "2/3",
  pages =        "457--464",
  month =        "????",
  year =         "2005",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Jun 1 08:14:41 MDT 2005",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/492/eleftheriou.pdf",
  abstract =     "This paper presents results on a
                 communications-intensive kernel, the three-dimensional
                 fast Fourier transform (3D FFT), running on the
                 2,048-node Blue Gene/L (BG/L) prototype. Two
                 implementations of the volumetric FFT algorithm were
                 characterized, one built on the Message Passing
                 Interface library and another built on an active packet
                 Application Program Interface supported by the hardware
                 bring-up environment, the BG/L advanced diagnostics
                 environment. Preliminary performance experiments on the
                 BG/L prototype indicate that both of our
                 implementations scale well up to 1,024 nodes for $3$D
                 FFTs of size $ 128 \time 128 \times 128 $. The
                 performance of the volumetric FFT is also compared with
                 that of the Fastest Fourier Transform in the West
                 (FFTW) library. In general, the volumetric FFT
                 outperforms a port of the FFTW Version 2.1.5 library on
                 large-node-count partitions.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  ordernumber =  "G322-0240",
}


bibtype: article
filename: fparith.bib
label: Enenkel:2005:CMF
title: Custom math functions for molecular dynamics
journal: j-IBM-JRD
volume: 49
number: 2/3
pages: 465--474
year: 2005
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Wed Jun 1 08:14:41 MDT 2005
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.01 08:14:41 MDT
URL: http://www.research.ibm.com/journal/rd/492/enenkel.pdf
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawtitle: Custom math functions for molecular dynamics
author:
R. F. Enenkel and B. G. Fitch and R. S. Germain and F. G. Gustavson and A. Martin and M. Mendell and J. W. Pitera and M. C. Pitman and A. Rayshubskiy and F. Suits and W. C. Swope and T. J. C. Ward

abstract:
While developing the protein folding application for the IBM Blue Gene/L supercomputer, some frequently executed computational kernels were encountered. These were significantly more complex than the linear algebra kernels that are normally provided as tuned libraries with modern machines. Using regular library functions for these would have resulted in an application that exploited only 5--10% of the potential floating-point throughput of the machine. This paper is a tour of the functions encountered; they have been expressed in C++ (and could be expressed in other languages such as Fortran or C). With the help of a good optimizing compiler, floating-point efficiency is much closer to 100%. The protein folding application was initially run by the life science researchers on IBM POWER3e machines while the computer science researchers were designing and bringing up the Blue Gene/L hardware. Some of the work discussed resulted in enhanced compiler optimizations, which now improve the performance of floating-point-intensive applications compiled by the IBM VisualAgent series of compilers for POWER3, POWER4e, POWER4+, and POWER5. The implementations are offered in the hope that they may help in other implementations of molecular dynamics or in other fields of endeavor, and in the hope that others may adapt the ideas presented here to deliver additional mathematical functions at high throughput.

rawabstract:
While developing the protein folding application for the IBM Blue Gene/L supercomputer, some frequently executed computational kernels were encountered. These were significantly more complex than the linear algebra kernels that are normally provided as tuned libraries with modern machines. Using regular library functions for these would have resulted in an application that exploited only 5--10\% of the potential floating-point throughput of the machine. This paper is a tour of the functions encountered; they have been expressed in C++ (and could be expressed in other languages such as Fortran or C). With the help of a good optimizing compiler, floating-point efficiency is much closer to 100\%. The protein folding application was initially run by the life science researchers on IBM POWER3e machines while the computer science researchers were designing and bringing up the Blue Gene/L hardware. Some of the work discussed resulted in enhanced compiler optimizations, which now improve the performance of floating-point-intensive applications compiled by the IBM VisualAgent series of compilers for POWER3, POWER4e, POWER4+, and POWER5. The implementations are offered in the hope that they may help in other implementations of molecular dynamics or in other fields of endeavor, and in the hope that others may adapt the ideas presented here to deliver additional mathematical functions at high throughput.

rawauthor:
R. F. Enenkel and B. G. Fitch and R. S. Germain and F. G. Gustavson and A. Martin and M. Mendell and J. W. Pitera and M. C. Pitman and A. Rayshubskiy and F. Suits and W. C. Swope and T. J. C. Ward

entry:
@Article{Enenkel:2005:CMF,
  author =       "R. F. Enenkel and B. G. Fitch and R. S. Germain and F.
                 G. Gustavson and A. Martin and M. Mendell and J. W.
                 Pitera and M. C. Pitman and A. Rayshubskiy and F. Suits
                 and W. C. Swope and T. J. C. Ward",
  title =        "Custom math functions for molecular dynamics",
  journal =      j-IBM-JRD,
  volume =       "49",
  number =       "2/3",
  pages =        "465--474",
  month =        "????",
  year =         "2005",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Jun 1 08:14:41 MDT 2005",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/492/enenkel.pdf",
  abstract =     "While developing the protein folding application for
                 the IBM Blue Gene/L supercomputer, some frequently
                 executed computational kernels were encountered. These
                 were significantly more complex than the linear algebra
                 kernels that are normally provided as tuned libraries
                 with modern machines. Using regular library functions
                 for these would have resulted in an application that
                 exploited only 5--10\% of the potential floating-point
                 throughput of the machine. This paper is a tour of the
                 functions encountered; they have been expressed in C++
                 (and could be expressed in other languages such as
                 Fortran or C). With the help of a good optimizing
                 compiler, floating-point efficiency is much closer to
                 100\%. The protein folding application was initially
                 run by the life science researchers on IBM POWER3e
                 machines while the computer science researchers were
                 designing and bringing up the Blue Gene/L hardware.
                 Some of the work discussed resulted in enhanced
                 compiler optimizations, which now improve the
                 performance of floating-point-intensive applications
                 compiled by the IBM VisualAgent series of compilers for
                 POWER3, POWER4e, POWER4+, and POWER5. The
                 implementations are offered in the hope that they may
                 help in other implementations of molecular dynamics or
                 in other fields of endeavor, and in the hope that
                 others may adapt the ideas presented here to deliver
                 additional mathematical functions at high throughput.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  ordernumber =  "G322-0240",
}


bibtype: inproceedings
filename: fparith.bib
label: Erle:2005:DME
author: Mark Erle and Eric Schwarz and Michael Schulte
title: Decimal Multiplication With Efficient Partial Product Generation
crossref: Montuschi:2005:PIS
pages: 21--28
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-183.pdf; http://mesa.ece.wisc.edu/publications/cp_2005-07.pdf
keywords: ARITH-17; decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Mark Erle and Eric Schwarz and Michael Schulte
rawtitle: Decimal Multiplication With Efficient Partial Product Generation
abstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents a novel design for fixed-point decimal multiplication that utilizes a simple recoding scheme to produce signed-magnitude representations of the operands thereby greatly simplifying the process of generating partial products for each multiplier digit. The partial products are generated using a digit-by-digit multiplier on a word-by-digit basis, first in a signed-digit form with two digits per position, and then combined via a combinational circuit. As the signed-digit partial products are developed one at a time while traversing the recoded multiplier operand from the least significant digit to the most significant digit, each partial product is added along with the accumulated sum of previous partial products via a signed-digit adder. This work is significantly different from other work employing digit-by-digit multipliers due to the efficiency gained by restricting the range of digits throughout the multiplication process.

rawabstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents a novel design for fixed-point decimal multiplication that utilizes a simple recoding scheme to produce signed-magnitude representations of the operands thereby greatly simplifying the process of generating partial products for each multiplier digit. The partial products are generated using a digit-by-digit multiplier on a word-by-digit basis, first in a signed-digit form with two digits per position, and then combined via a combinational circuit. As the signed-digit partial products are developed one at a time while traversing the recoded multiplier operand from the least significant digit to the most significant digit, each partial product is added along with the accumulated sum of previous partial products via a signed-digit adder. This work is significantly different from other work employing digit-by-digit multipliers due to the efficiency gained by restricting the range of digits throughout the multiplication process.

entry:
@InProceedings{Erle:2005:DME,
  author =       "Mark Erle and Eric Schwarz and Michael Schulte",
  title =        "Decimal Multiplication With Efficient Partial Product
                 Generation",
  crossref =     "Montuschi:2005:PIS",
  pages =        "21--28",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-183.pdf;
                 http://mesa.ece.wisc.edu/publications/cp_2005-07.pdf",
  abstract =     "Decimal multiplication is important in many commercial
                 applications including financial analysis, banking, tax
                 calculation, currency conversion, insurance, and
                 accounting. This paper presents a novel design for
                 fixed-point decimal multiplication that utilizes a
                 simple recoding scheme to produce signed-magnitude
                 representations of the operands thereby greatly
                 simplifying the process of generating partial products
                 for each multiplier digit. The partial products are
                 generated using a digit-by-digit multiplier on a
                 word-by-digit basis, first in a signed-digit form with
                 two digits per position, and then combined via a
                 combinational circuit. As the signed-digit partial
                 products are developed one at a time while traversing
                 the recoded multiplier operand from the least
                 significant digit to the most significant digit, each
                 partial product is added along with the accumulated sum
                 of previous partial products via a signed-digit adder.
                 This work is significantly different from other work
                 employing digit-by-digit multipliers due to the
                 efficiency gained by restricting the range of digits
                 throughout the multiplication process.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; decimal floating-point arithmetic",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Etiemble:2005:CBF
author: D. Etiemble and S. Bouaziz and L. Lacassagne
crossref: IEEE:2005:PWE
pages: 61--66
year: 2005
DOI: https://doi.org/10.1109/ESTMED.2005.1518073
bibdate: Sat Oct 9 12:40:19 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:40:19 ???
acknowledgement: ack-nhfb
rawauthor: D. Etiemble and S. Bouaziz and L. Lacassagne
title:
Customizing 16-bit floating point instructions on a NIOS II processor for FPGA image and media processing

abstract:
We have implemented customized SIMD 16-bit floating point instructions on a NIOS II processor. On several image processing and media benchmarks for which the accuracy and dynamic range of this format is sufficient, a speed-up ranging from 1.5 to more than 2 is obtained versus the integer implementation. The hardware overhead remains limited and is compatible with the capacities of today's FPGAs.

rawabstract:
We have implemented customized SIMD 16-bit floating point instructions on a NIOS II processor. On several image processing and media benchmarks for which the accuracy and dynamic range of this format is sufficient, a speed-up ranging from 1.5 to more than 2 is obtained versus the integer implementation. The hardware overhead remains limited and is compatible with the capacities of today's FPGAs.

rawtitle:
Customizing 16-bit floating point instructions on a {NIOS II} processor for {FPGA} image and media processing

entry:
@InProceedings{Etiemble:2005:CBF,
  author =       "D. Etiemble and S. Bouaziz and L. Lacassagne",
  title =        "Customizing 16-bit floating point instructions on a
                 {NIOS II} processor for {FPGA} image and media
                 processing",
  crossref =     "IEEE:2005:PWE",
  pages =        "61--66",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ESTMED.2005.1518073",
  bibdate =      "Sat Oct 9 12:40:19 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We have implemented customized SIMD 16-bit floating
                 point instructions on a NIOS II processor. On several
                 image processing and media benchmarks for which the
                 accuracy and dynamic range of this format is
                 sufficient, a speed-up ranging from 1.5 to more than 2
                 is obtained versus the integer implementation. The
                 hardware overhead remains limited and is compatible
                 with the capacities of today's FPGAs.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Even:2005:PEA
author: Guy Even and Peter-M. Seidel and Warren E. Ferguson
title: A parametric error analysis of Goldschmidt's division algorithm
journal: j-J-COMP-SYS-SCI
volume: 70
number: 1
pages: 118--139
month: feb
monthnumber: 2
year: 2005
CODEN: JCSSBM
DOI: https://doi.org/10.1016/j.jcss.2004.08.004
ISSN: 0022-0000 (print), 1090-2724 (electronic) OR 00220000 (print), 10902724 (electronic)
ISSNL: 0022-0000 OR 00220000
bibdate: Tue Jan 29 15:26:56 MST 2019
bibtimestamp: 2019.01.29 15:26:56 MST
URL: http://www.sciencedirect.com/science/article/pii/S0022000004000960
fjournal: Journal of Computer and System Sciences
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00220000
rawauthor: Guy Even and Peter-M. Seidel and Warren E. Ferguson
rawtitle: A parametric error analysis of {Goldschmidt}'s division algorithm
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcompsyssci.bib

entry:
@Article{Even:2005:PEA,
  author =       "Guy Even and Peter-M. Seidel and Warren E. Ferguson",
  title =        "A parametric error analysis of {Goldschmidt}'s
                 division algorithm",
  journal =      j-J-COMP-SYS-SCI,
  volume =       "70",
  number =       "1",
  pages =        "118--139",
  month =        feb,
  year =         "2005",
  CODEN =        "JCSSBM",
  DOI =          "https://doi.org/10.1016/j.jcss.2004.08.004",
  ISSN =         "0022-0000 (print), 1090-2724 (electronic)",
  ISSN-L =       "0022-0000",
  bibdate =      "Tue Jan 29 15:26:56 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcompsyssci.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0022000004000960",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computer and System Sciences",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00220000",
}


bibtype: article
filename: fparith.bib
label: Fan:2005:FBP
author: Haining Fan and Yiqi Dai
title: Fast bit-parallel $ mathrm GF(2^n) $ multiplier for all trinomials
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 4
pages: 485--490
month: apr
monthnumber: 4
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.64
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:16 MDT 2011
bibtimestamp: 2011.07.04 16:17:16 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1401867
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Haining Fan and Yiqi Dai
rawtitle: Fast bit-parallel {$ \mathrm {GF}(2^n) $} multiplier for all trinomials
entry:
@Article{Fan:2005:FBP,
  author =       "Haining Fan and Yiqi Dai",
  title =        "Fast bit-parallel {$ \mathrm {GF}(2^n) $} multiplier
                 for all trinomials",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "4",
  pages =        "485--490",
  month =        apr,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.64",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:16 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1401867",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Fit-Florea:2005:ABE
author: A. Fit-Florea and D. W. Matula and M. A. Thornton
title: Addition-based exponentiation modulo $ 2^k $
journal: j-ELECT-LETTERS
volume: 41
number: 2
pages: 56--57
day: 20
month: jan
monthnumber: 1
year: 2005
CODEN: ELLEAK
DOI: https://doi.org/10.1049/el:20057538
ISSN: 0013-5194 (print), 1350-911X (electronic) OR 00135194 (print), 1350911X (electronic)
ISSNL: 0013-5194 OR 00135194
bibdate: Fri Jun 24 15:17:52 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 15:17:52 ???
URL: http://ieeexplore.ieee.org/iel5/2220/30332/01393468.pdf
fjournal: Electronics Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220
rawauthor: A. Fit-Florea and D. W. Matula and M. A. Thornton
rawtitle: Addition-based exponentiation modulo $ 2^k $
abstract:
A novel method for performing exponentiation modulo $ 2^k $ is described. The algorithm has a critical path consisting of $k$ dependent shift-and-add modulo $ 2^k $ operations. Although $3$ is the preferred exponent base, the algorithm can be extended easily in order to perform the general binary powering operation.

rawabstract:
A novel method for performing exponentiation modulo $ 2^k $ is described. The algorithm has a critical path consisting of $k$ dependent shift-and-add modulo $ 2^k $ operations. Although $3$ is the preferred exponent base, the algorithm can be extended easily in order to perform the general binary powering operation.

entry:
@Article{Fit-Florea:2005:ABE,
  author =       "A. Fit-Florea and D. W. Matula and M. A. Thornton",
  title =        "Addition-based exponentiation modulo $ 2^k $",
  journal =      j-ELECT-LETTERS,
  volume =       "41",
  number =       "2",
  pages =        "56--57",
  day =          "20",
  month =        jan,
  year =         "2005",
  CODEN =        "ELLEAK",
  DOI =          "https://doi.org/10.1049/el:20057538",
  ISSN =         "0013-5194 (print), 1350-911X (electronic)",
  ISSN-L =       "0013-5194",
  bibdate =      "Fri Jun 24 15:17:52 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/iel5/2220/30332/01393468.pdf",
  abstract =     "A novel method for performing exponentiation modulo $
                 2^k $ is described. The algorithm has a critical path
                 consisting of $k$ dependent shift-and-add modulo $ 2^k
                 $ operations. Although $3$ is the preferred exponent
                 base, the algorithm can be extended easily in order to
                 perform the general binary powering operation.",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics Letters",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220",
}


bibtype: techreport
filename: fparith.bib
label: Fousse:2005:MMP
author: Laurent Fousse and Guillaume Hanrot and Vincent Lefevre and Patrick Pelissier and Paul Zimmermann
title: MPFR: a Multiple-Precision Binary Floating-Point Library With Correct Rounding
type: Technical Report
number: RR-5753
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 15
month: nov
monthnumber: 11
year: 2005
bibdate: Sun Sep 10 07:26:55 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 07:26:55 ???
acknowledgement: ack-nhfb
rawtitle: {MPFR}: a Multiple-Precision Binary Floating-Point Library With Correct Rounding
URL:
ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-5753.pdf; ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-5753.ps.gz; http://www.inria.fr/rrrt/rr-5753.html

abstract:
This paper presents a multiple-precision binary floating-point library, written in the ISO C language, and based on the GNU MP library. Its particularity is to extend ideas from the IEEE-754 standard to arbitrary precision, by providing correct rounding

rawabstract:
This paper presents a multiple-precision binary floating-point library, written in the ISO C language, and based on the GNU MP library. Its particularity is to extend ideas from the IEEE-754 standard to arbitrary precision, by providing correct rounding

rawauthor:
Laurent Fousse and Guillaume Hanrot and Vincent Lef{\`e}vre and Patrick P{\'e}lissier and Paul Zimmermann

entry:
@TechReport{Fousse:2005:MMP,
  author =       "Laurent Fousse and Guillaume Hanrot and Vincent
                 Lef{\`e}vre and Patrick P{\'e}lissier and Paul
                 Zimmermann",
  title =        "{MPFR}: a Multiple-Precision Binary Floating-Point
                 Library With Correct Rounding",
  type =         "Technical Report",
  number =       "RR-5753",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "15",
  month =        nov,
  year =         "2005",
  bibdate =      "Sun Sep 10 07:26:55 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-5753.pdf;
                 ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-5753.ps.gz;
                 http://www.inria.fr/rrrt/rr-5753.html",
  abstract =     "This paper presents a multiple-precision binary
                 floating-point library, written in the ISO C language,
                 and based on the GNU MP library. Its particularity is
                 to extend ideas from the IEEE-754 standard to arbitrary
                 precision, by providing correct rounding",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Fraysse:2005:ASG
author: Valrie Fraysse and Luc Giraud and Serge Gratton and Julien Langou
journal: j-TOMS
volume: 31
number: 2
pages: 228--238
month: jun
monthnumber: 6
year: 2005
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1067967.1067970
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Jun 21 16:55:57 MDT 2005
bibsource: http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.21 16:55:57 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: Val{\'r}ie Frayss{\'e} and Luc Giraud and Serge Gratton and Julien Langou
title:
Algorithm 842: a set of GMRES routines for real and complex arithmetics on high performance computers

abstract:
In this article we describe our implementations of the GMRES algorithm for both real and complex, single and double precision arithmetics suitable for serial, shared memory and distributed memory computers. For the sake of portability, simplicity, flexibility and efficiency the GMRES solvers have been implemented in Fortran 77 using the reverse communication mechanism for the matrix-vector product, the preconditioning and the dot product computations. For distributed memory computation, several orthogonalization procedures have been implemented to reduce the cost of the dot product calculation, which is a well-known bottleneck of efficiency for the Krylov methods. Either implicit or explicit calculation of the residual at restart are possible depending on the actual cost of the matrix-vector product. Finally the implemented stopping criterion is based on a normwise backward error.

rawabstract:
In this article we describe our implementations of the GMRES algorithm for both real and complex, single and double precision arithmetics suitable for serial, shared memory and distributed memory computers. For the sake of portability, simplicity, flexibility and efficiency the GMRES solvers have been implemented in Fortran 77 using the reverse communication mechanism for the matrix-vector product, the preconditioning and the dot product computations. For distributed memory computation, several orthogonalization procedures have been implemented to reduce the cost of the dot product calculation, which is a well-known bottleneck of efficiency for the Krylov methods. Either implicit or explicit calculation of the residual at restart are possible depending on the actual cost of the matrix-vector product. Finally the implemented stopping criterion is based on a normwise backward error.

rawtitle:
{Algorithm 842}: a set of {GMRES} routines for real and complex arithmetics on high performance computers

entry:
@Article{Fraysse:2005:ASG,
  author =       "Val{\'r}ie Frayss{\'e} and Luc Giraud and Serge
                 Gratton and Julien Langou",
  title =        "{Algorithm 842}: a set of {GMRES} routines for real
                 and complex arithmetics on high performance computers",
  journal =      j-TOMS,
  volume =       "31",
  number =       "2",
  pages =        "228--238",
  month =        jun,
  year =         "2005",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1067967.1067970",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Jun 21 16:55:57 MDT 2005",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this article we describe our implementations of the
                 GMRES algorithm for both real and complex, single and
                 double precision arithmetics suitable for serial,
                 shared memory and distributed memory computers. For the
                 sake of portability, simplicity, flexibility and
                 efficiency the GMRES solvers have been implemented in
                 Fortran 77 using the reverse communication mechanism
                 for the matrix-vector product, the preconditioning and
                 the dot product computations. For distributed memory
                 computation, several orthogonalization procedures have
                 been implemented to reduce the cost of the dot product
                 calculation, which is a well-known bottleneck of
                 efficiency for the Krylov methods. Either implicit or
                 explicit calculation of the residual at restart are
                 possible depending on the actual cost of the
                 matrix-vector product. Finally the implemented stopping
                 criterion is based on a normwise backward error.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: techreport
filename: fparith.bib
label: Giles:2005:BLN
author: David E. Giles
title: Benford's Law and Naturally Occurring Prices in Certain ebaY Auctions
type: Econometrics Working Paper
number: EWP0505
institution: Department of Economics, University of Victoria
address: Victoria, BC, Canada
pages: 228--238
month: may
monthnumber: 5
year: 2005
ISSN: 1485-6441 OR 14856441
bibdate: Thu Feb 15 16:24:39 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.02.15 16:24:39 ???
URL: http://web.uvic.ca/econ/ewp0505.pdf
keywords: Benford's Law; Law of Anomalous Numbers; Zipf's Law
acknowledgement: ack-nhfb
rawauthor: David E. Giles
rawtitle: {Benford's Law} and Naturally Occurring Prices in Certain {ebaY} Auctions
abstract:
We show that certain the winning bids for certain ebaY auctions obey Benford's Law. One implication of this is that it is unlikely that these bids are subject to collusion among bidders, or ``shilling'' on the part of sellers. Parenthetically, we also show that numbers from the naturally occurring Fibonacci and Lucas sequences also obey Benford's Law.

rawabstract:
We show that certain the winning bids for certain ebaY auctions obey Benford's Law. One implication of this is that it is unlikely that these bids are subject to collusion among bidders, or ``shilling'' on the part of sellers. Parenthetically, we also show that numbers from the naturally occurring Fibonacci and Lucas sequences also obey Benford's Law.

entry:
@TechReport{Giles:2005:BLN,
  author =       "David E. Giles",
  title =        "{Benford's Law} and Naturally Occurring Prices in
                 Certain {ebaY} Auctions",
  type =         "Econometrics Working Paper",
  number =       "EWP0505",
  institution =  "Department of Economics, University of Victoria",
  address =      "Victoria, BC, Canada",
  month =        may,
  year =         "2005",
  ISSN =         "1485-6441",
  bibdate =      "Thu Feb 15 16:24:39 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://web.uvic.ca/econ/ewp0505.pdf",
  abstract =     "We show that certain the winning bids for certain ebaY
                 auctions obey Benford's Law. One implication of this is
                 that it is unlikely that these bids are subject to
                 collusion among bidders, or ``shilling'' on the part of
                 sellers. Parenthetically, we also show that numbers
                 from the naturally occurring Fibonacci and Lucas
                 sequences also obey Benford's Law.",
  acknowledgement = ack-nhfb,
  keywords =     "Benford's Law; Law of Anomalous Numbers; Zipf's Law",
}


bibtype: article
filename: fparith.bib
label: Giraud:2005:REA
author: Luc Giraud and Julien Langou and Miroslav Rozloznik and Jasper van den Eshof
title: Rounding error analysis of the classical Gram--Schmidt orthogonalization process
journal: j-NUM-MATH
volume: 101
number: 1
pages: 87--100
month: jul
monthnumber: 7
year: 2005
CODEN: NUMMA7
DOI: https://doi.org/10.1007/s00211-005-0615-4
ISSN: 0029-599X (print), 0945-3245 (electronic) OR 0029599X (print), 09453245 (electronic)
ISSNL: 0029-599X OR 0029599X
MRclass: 65F25, 65G50, 15A23
bibdate: Tue Oct 11 18:59:06 MDT 2005
bibtimestamp: 2005.10.11 18:59:06 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0029-599X&volume=101&issue=1&spage=87
fjournal: Numerische Mathematik
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/211
rawauthor: Luc Giraud and Julien Langou and Miroslav Rozlozn{\'\i}k and Jasper van den Eshof
rawtitle: Rounding error analysis of the classical {Gram--Schmidt} orthogonalization process
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0029-599X&volume=101&issue=1; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
This paper provides two results on the numerical behavior of the classical Gram--Schmidt algorithm. The first result states that, provided the normal equations associated with the initial vectors are numerically nonsingular, the loss of orthogonality of the vectors computed by the classical Gram--Schmidt algorithm depends quadratically on the condition number of the initial vectors. The second result states that, provided the initial set of vectors has numerical full rank, two iterations of the classical Gram--Schmidt algorithm are enough for ensuring the orthogonality of the computed vectors to be close to the unit roundoff level.

rawabstract:
This paper provides two results on the numerical behavior of the classical Gram--Schmidt algorithm. The first result states that, provided the normal equations associated with the initial vectors are numerically nonsingular, the loss of orthogonality of the vectors computed by the classical Gram--Schmidt algorithm depends quadratically on the condition number of the initial vectors. The second result states that, provided the initial set of vectors has numerical full rank, two iterations of the classical Gram--Schmidt algorithm are enough for ensuring the orthogonality of the computed vectors to be close to the unit roundoff level.

entry:
@Article{Giraud:2005:REA,
  author =       "Luc Giraud and Julien Langou and Miroslav
                 Rozlozn{\'\i}k and Jasper van den Eshof",
  title =        "Rounding error analysis of the classical
                 {Gram--Schmidt} orthogonalization process",
  journal =      j-NUM-MATH,
  volume =       "101",
  number =       "1",
  pages =        "87--100",
  month =        jul,
  year =         "2005",
  CODEN =        "NUMMA7",
  DOI =          "https://doi.org/10.1007/s00211-005-0615-4",
  ISSN =         "0029-599X (print), 0945-3245 (electronic)",
  ISSN-L =       "0029-599X",
  MRclass =      "65F25, 65G50, 15A23",
  bibdate =      "Tue Oct 11 18:59:06 MDT 2005",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0029-599X&volume=101&issue=1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0029-599X&volume=101&issue=1&spage=87",
  abstract =     "This paper provides two results on the numerical
                 behavior of the classical Gram--Schmidt algorithm. The
                 first result states that, provided the normal equations
                 associated with the initial vectors are numerically
                 nonsingular, the loss of orthogonality of the vectors
                 computed by the classical Gram--Schmidt algorithm
                 depends quadratically on the condition number of the
                 initial vectors. The second result states that,
                 provided the initial set of vectors has numerical full
                 rank, two iterations of the classical Gram--Schmidt
                 algorithm are enough for ensuring the orthogonality of
                 the computed vectors to be close to the unit roundoff
                 level.",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerische Mathematik",
  journal-URL =  "http://link.springer.com/journal/211",
}


bibtype: article
filename: fparith.bib
label: Glusker:2005:TCM
author: Mark Glusker and David M. Hogan and Pamela Vass
title: The Ternary Calculating Machine of Thomas Fowler
journal: j-IEEE-ANN-HIST-COMPUT
volume: 27
number: 3
pages: 4--22
month: jul
monthnumber: 7
year: 2005
CODEN: IAHCEX
DOI: https://doi.org/10.1109/MAHC.2005.49
ISSN: 1058-6180 (print), 1934-1547 (electronic) OR 10586180 (print), 19341547 (electronic)
ISSNL: 1058-6180 OR 10586180
bibdate: Mon Nov 7 18:51:49 MST 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.07 18:51:49 MST
fjournal: IEEE Annals of the History of Computing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=85
rawauthor: Mark Glusker and David M. Hogan and Pamela Vass
rawtitle: The Ternary Calculating Machine of {Thomas Fowler}
abstract:
In 1840, Thomas Fowler, a self-taught English mathematician and inventor, created a unique ternary calculating machine. Until recently, all detail of this machine was lost. A research project begun in 1997 uncovered sufficient information to enable the recreation of a physical concept model of Fowler's machine. The next step is to create a historically accurate replica.

keywords:
19th century; Augustus De Morgan; balanced ternary; base-3; calculating machine; historical reconstruction; signed ternary; ternary; Thomas Fowler

rawabstract:
In 1840, Thomas Fowler, a self-taught English mathematician and inventor, created a unique ternary calculating machine. Until recently, all detail of this machine was lost. A research project begun in 1997 uncovered sufficient information to enable the recreation of a physical concept model of Fowler's machine. The next step is to create a historically accurate replica.

entry:
@Article{Glusker:2005:TCM,
  author =       "Mark Glusker and David M. Hogan and Pamela Vass",
  title =        "The Ternary Calculating Machine of {Thomas Fowler}",
  journal =      j-IEEE-ANN-HIST-COMPUT,
  volume =       "27",
  number =       "3",
  pages =        "4--22",
  month =        jul # "\slash " # sep,
  year =         "2005",
  CODEN =        "IAHCEX",
  DOI =          "https://doi.org/10.1109/MAHC.2005.49",
  ISSN =         "1058-6180 (print), 1934-1547 (electronic)",
  ISSN-L =       "1058-6180",
  bibdate =      "Mon Nov 7 18:51:49 MST 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In 1840, Thomas Fowler, a self-taught English
                 mathematician and inventor, created a unique ternary
                 calculating machine. Until recently, all detail of this
                 machine was lost. A research project begun in 1997
                 uncovered sufficient information to enable the
                 recreation of a physical concept model of Fowler's
                 machine. The next step is to create a historically
                 accurate replica.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Annals of the History of Computing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=85",
  keywords =     "19th century; Augustus De Morgan; balanced ternary;
                 base-3; calculating machine; historical reconstruction;
                 signed ternary; ternary; Thomas Fowler",
}


bibtype: techreport
filename: fparith.bib
label: Graillat:2005:CHS
author: S. Graillat and P. Langlois and N. Louvet
title: Compensated Horner Scheme
type: Research Report
number: RR2005-04
institution: Equipe de Recherche DALI, Laboratoire LP2A, Universite de Perpignan, Via Domitia
address: Perpignan, France
pages: ii + 25
day: 24
month: jul
monthnumber: 7
year: 2005
bibdate: Fri Jan 06 07:45:03 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.01.06 07:45:03 ???
URL: http://gala.univ-perp.fr/~graillat/papers/rr2005-04.pdf
acknowledgement: ack-nhfb
rawauthor: S. Graillat and P. Langlois and N. Louvet
rawtitle: Compensated {Horner} Scheme
abstract:
We present a compensated Horner scheme, that is an accurate and fast algorithm to evaluate univariate polynomials in floating point arithmetic. The accuracy of the computed result is similar to the one given by the Horner scheme computed in twice the working precision. This compensated Horner scheme runs at least as fast as existing implementations producing the same output accuracy. We also propose to compute in pure floating point arithmetic a valid error estimate that bound the actual accuracy of the compensated evaluation. Numerical experiments involving ill-conditioned polynomials illustrate these results. All algorithms are performed at a given working precision and are portable assuming the floating point arithmetic satisfies the IEEE-754 standard.

keywords:
compensated Horner scheme; error-free transformations; extended precision; IEEE-754 floating point arithmetic; polynomial evaluation; running error bound

rawabstract:
We present a compensated Horner scheme, that is an accurate and fast algorithm to evaluate univariate polynomials in floating point arithmetic. The accuracy of the computed result is similar to the one given by the Horner scheme computed in twice the working precision. This compensated Horner scheme runs at least as fast as existing implementations producing the same output accuracy. We also propose to compute in pure floating point arithmetic a valid error estimate that bound the actual accuracy of the compensated evaluation. Numerical experiments involving ill-conditioned polynomials illustrate these results. All algorithms are performed at a given working precision and are portable assuming the floating point arithmetic satisfies the IEEE-754 standard.

entry:
@TechReport{Graillat:2005:CHS,
  author =       "S. Graillat and P. Langlois and N. Louvet",
  title =        "Compensated {Horner} Scheme",
  type =         "Research Report",
  number =       "RR2005-04",
  institution =  "{\'E}quipe de Recherche DALI, Laboratoire LP2A,
                 Universit{\'e} de Perpignan, Via Domitia",
  address =      "Perpignan, France",
  pages =        "ii + 25",
  day =          "24",
  month =        jul,
  year =         "2005",
  bibdate =      "Fri Jan 06 07:45:03 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://gala.univ-perp.fr/~graillat/papers/rr2005-04.pdf",
  abstract =     "We present a compensated Horner scheme, that is an
                 accurate and fast algorithm to evaluate univariate
                 polynomials in floating point arithmetic. The accuracy
                 of the computed result is similar to the one given by
                 the Horner scheme computed in twice the working
                 precision. This compensated Horner scheme runs at least
                 as fast as existing implementations producing the same
                 output accuracy. We also propose to compute in pure
                 floating point arithmetic a valid error estimate that
                 bound the actual accuracy of the compensated
                 evaluation. Numerical experiments involving
                 ill-conditioned polynomials illustrate these results.
                 All algorithms are performed at a given working
                 precision and are portable assuming the floating point
                 arithmetic satisfies the IEEE-754 standard.",
  acknowledgement = ack-nhfb,
  amsclass =     "65G, 65Y99",
  keywords =     "compensated Horner scheme; error-free transformations;
                 extended precision; IEEE-754 floating point arithmetic;
                 polynomial evaluation; running error bound",
}


bibtype: techreport
filename: fparith.bib
label: Graillat:2005:ICH
author: S. Graillat and P. Langlois and N. Louvet
title: Improving the compensated Horner scheme with a fused multiply and add
type: Research Report
number: RR2005-05
institution: Equipe de Recherche DALI, Laboratoire LP2A, Universite de Perpignan, Via Domitia
address: Perpignan, France
pages: ii + 25
month: nov
monthnumber: 11
year: 2005
bibdate: Sat Feb 26 18:45:17 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.26 18:45:17 ???
acknowledgement: ack-nhfb
rawauthor: S. Graillat and P. Langlois and N. Louvet
rawtitle: Improving the compensated {Horner} scheme with a fused multiply and add
entry:
@TechReport{Graillat:2005:ICH,
  author =       "S. Graillat and P. Langlois and N. Louvet",
  title =        "Improving the compensated {Horner} scheme with a fused
                 multiply and add",
  type =         "Research Report",
  number =       "RR2005-05",
  institution =  "{\'E}quipe de Recherche DALI, Laboratoire LP2A,
                 Universit{\'e} de Perpignan, Via Domitia",
  address =      "Perpignan, France",
  month =        nov,
  year =         "2005",
  bibdate =      "Sat Feb 26 18:45:17 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Guizzo:2005:IRS
author: E. Guizzo
title: IBM reclaims supercomputer lead
journal: j-IEEE-SPECTRUM
volume: 42
number: 2
pages: 15--16
month: feb
monthnumber: 2
year: 2005
CODEN: IEESAM
DOI: https://doi.org/10.1109/MSPEC.2005.1389501
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Thu Sep 01 16:25:09 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.01 16:25:09 ???
fjournal: IEEE Spectrum
keywords: 70 Tflops; floating-point arithmetic; IBM Glue Gene/L
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: E. Guizzo
rawtitle: {IBM} reclaims supercomputer lead
entry:
@Article{Guizzo:2005:IRS,
  author =       "E. Guizzo",
  title =        "{IBM} reclaims supercomputer lead",
  journal =      j-IEEE-SPECTRUM,
  volume =       "42",
  number =       "2",
  pages =        "15--16",
  month =        feb,
  year =         "2005",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/MSPEC.2005.1389501",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Thu Sep 01 16:25:09 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "70 Tflops; floating-point arithmetic; IBM Glue
                 Gene/L",
}


bibtype: inproceedings
filename: fparith.bib
label: Haijun:2005:ROT
author: Sun Haijun and Shao Zhibiao and Zom Gang and Zhao Ning
title: The research on optimization techniques of 32-bit floating-point RISC microprocessor
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 63--66
year: 2005
DOI: https://doi.org/10.1109/iwvdvt.2005.1504465
bibdate: Wed Dec 13 09:49:47 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.13 09:49:47 ???
keywords: XJ-1 processor
acknowledgement: ack-nhfb
rawauthor: Sun Haijun and Shao Zhibiao and Zom Gang and Zhao Ning
rawtitle: The research on optimization techniques of 32-bit floating-point {RISC} microprocessor
booktitle:
Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 28--30 May 2005

rawbooktitle:
Proceedings of {2005 IEEE International Workshop on VLSI Design and Video Technology, 28--30 May 2005}

entry:
@InProceedings{Haijun:2005:ROT,
  author =       "Sun Haijun and Shao Zhibiao and Zom Gang and Zhao
                 Ning",
  booktitle =    "Proceedings of {2005 IEEE International Workshop on
                 VLSI Design and Video Technology, 28--30 May 2005}",
  title =        "The research on optimization techniques of 32-bit
                 floating-point {RISC} microprocessor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "63--66",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/iwvdvt.2005.1504465",
  bibdate =      "Wed Dec 13 09:49:47 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "XJ-1 processor",
}


bibtype: book
filename: fparith.bib
label: Hally:2005:EBS
author: Mike Hally
title: Electronic Brains: Stories from the Dawn of the Computer Age
publisher: pub-JOSEPH-HENRY
address: pub-JOSEPH-HENRY:adr
pages: xxiii + 275
year: 2005
ISBN: 0-309-09630-8 (hardcover) OR 0309096308 (hardcover)
ISBN13: 978-0-309-09630-0 (hardcover) OR 9780309096300 (hardcover)
LCCN: QA76.17 .H35 2005
bibdate: Wed Aug 9 07:02:58 MDT 2023
bibsource: fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.08.09 07:02:58 MDT
subject: Computers; History; Ordinateurs; Histoire; Computers.; Computers.
acknowledgement: ack-nhfb
rawauthor: Mike Hally
rawtitle: Electronic Brains: Stories from the Dawn of the Computer Age
URL:
http://catdir.loc.gov/catdir/toc/ecip0514/2005016583.html; http://library.ccsu.edu/help/spcoll/oconnell/index.htm

abstract:
By the 1960s, IBM, once a manufacturer of mechanical tabulators, had beaten all rivals and dominated the world computer market. But IBM came late to the race. From the 1930s to the 1950s, small independent teams on four continents worked on the development of the very first modern computers --- practical, electronic, multipurpose, digital machines with memory for data and programs. From interviews with surviving members of those original pioneering teams, the author builds up a picture of the eccentric, obsessive and fiercely loyal men and women who laid the foundations for the computerized world we now live in, and re-creates the atmosphere of those early days.

TOC:
From ABC to ENIAC UNIVAC Saviour of the Census Saluting the Moose When Britain Led the Computing World LEO the Lyons Computer So Then We Took the Roof Off Wizards of Oz Water on the Brain It's Not About Being First: the Rise and Rise of IBM Arithmetic Technical bits

rawabstract:
By the 1960s, IBM, once a manufacturer of mechanical tabulators, had beaten all rivals and dominated the world computer market. But IBM came late to the race. From the 1930s to the 1950s, small independent teams on four continents worked on the development of the very first modern computers --- practical, electronic, multipurpose, digital machines with memory for data and programs. From interviews with surviving members of those original pioneering teams, the author builds up a picture of the eccentric, obsessive and fiercely loyal men and women who laid the foundations for the computerized world we now live in, and re-creates the atmosphere of those early days.

rawTOC:
From ABC to ENIAC \\ UNIVAC \\ Saviour of the Census \\ Saluting the Moose \\ When Britain Led the Computing World \\ LEO the Lyons Computer \\ So Then We Took the Roof Off \\ Wizards of Oz \\ Water on the Brain \\ It's Not About Being First: the Rise and Rise of IBM \\ Arithmetic \\ Technical bits

entry:
@Book{Hally:2005:EBS,
  author =       "Mike Hally",
  title =        "Electronic Brains: Stories from the Dawn of the
                 Computer Age",
  publisher =    pub-JOSEPH-HENRY,
  address =      pub-JOSEPH-HENRY:adr,
  pages =        "xxiii + 275",
  year =         "2005",
  ISBN =         "0-309-09630-8 (hardcover)",
  ISBN-13 =      "978-0-309-09630-0 (hardcover)",
  LCCN =         "QA76.17 .H35 2005",
  bibdate =      "Wed Aug 9 07:02:58 MDT 2023",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://catdir.loc.gov/catdir/toc/ecip0514/2005016583.html;
                 http://library.ccsu.edu/help/spcoll/oconnell/index.htm",
  abstract =     "By the 1960s, IBM, once a manufacturer of mechanical
                 tabulators, had beaten all rivals and dominated the
                 world computer market. But IBM came late to the race.
                 From the 1930s to the 1950s, small independent teams on
                 four continents worked on the development of the very
                 first modern computers --- practical, electronic,
                 multipurpose, digital machines with memory for data and
                 programs. From interviews with surviving members of
                 those original pioneering teams, the author builds up a
                 picture of the eccentric, obsessive and fiercely loyal
                 men and women who laid the foundations for the
                 computerized world we now live in, and re-creates the
                 atmosphere of those early days.",
  acknowledgement = ack-nhfb,
  subject =      "Computers; History; Ordinateurs; Histoire; Computers.;
                 Computers.",
  tableofcontents = "From ABC to ENIAC \\
                 UNIVAC \\
                 Saviour of the Census \\
                 Saluting the Moose \\
                 When Britain Led the Computing World \\
                 LEO the Lyons Computer \\
                 So Then We Took the Roof Off \\
                 Wizards of Oz \\
                 Water on the Brain \\
                 It's Not About Being First: the Rise and Rise of IBM
                 \\
                 Arithmetic \\
                 Technical bits",
}


bibtype: book
filename: fparith.bib
label: Hanss:2005:AFA
author: Michael Hanss
title: Applied fuzzy arithmetic: an introduction with engineering applications
publisher: pub-SV
address: pub-SV:adr
pages: xiii + 256
year: 2005
ISBN: 3-540-24201-5 OR 3540242015
ISBN13: 978-3-540-24201-7 OR 9783540242017
LCCN: QA248.5 .H36 2005
bibdate: Mon Oct 29 18:21:47 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2007.10.29 18:21:47 MDT
URL: http://www.loc.gov/catdir/enhancements/fy0662/2004117177-d.html
subject: Fuzzy arithmetic; Fuzzy logic
acknowledgement: ack-nhfb
rawauthor: Michael Hanss
rawtitle: Applied fuzzy arithmetic: an introduction with engineering applications
entry:
@Book{Hanss:2005:AFA,
  author =       "Michael Hanss",
  title =        "Applied fuzzy arithmetic: an introduction with
                 engineering applications",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "xiii + 256",
  year =         "2005",
  ISBN =         "3-540-24201-5",
  ISBN-13 =      "978-3-540-24201-7",
  LCCN =         "QA248.5 .H36 2005",
  bibdate =      "Mon Oct 29 18:21:47 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  URL =          "http://www.loc.gov/catdir/enhancements/fy0662/2004117177-d.html",
  acknowledgement = ack-nhfb,
  subject =      "Fuzzy arithmetic; Fuzzy logic",
}


bibtype: inproceedings
filename: fparith.bib
label: Hariri:2005:SMS
author: A. Hariri and K. Navi and R. Rastegar
title: A Simplified Modulo $ (2^n - 1) $ Squaring Scheme for Residue Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 615--618
year: 2005
DOI: https://doi.org/10.1109/EURCON.2005.1630004
ISBN: 1-4244-0049-X OR 142440049X
ISBN13: 978-1-4244-0049-2 OR 9781424400492
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Hariri and K. Navi and R. Rastegar
rawtitle: A Simplified Modulo $ (2^n - 1) $ Squaring Scheme for Residue Number System
booktitle:
EUROCON 2005, The International Conference on ``Computer as a Tool'': proceedings: Belgrade, Serbia and Montenegro: November 21--24, 2005

rawbooktitle:
{EUROCON 2005, The International Conference on ``Computer as a Tool'': proceedings: Belgrade, Serbia and Montenegro: November 21--24, 2005}

entry:
@InProceedings{Hariri:2005:SMS,
  author =       "A. Hariri and K. Navi and R. Rastegar",
  booktitle =    "{EUROCON 2005, The International Conference on
                 ``Computer as a Tool'': proceedings: Belgrade, Serbia
                 and Montenegro: November 21--24, 2005}",
  title =        "A Simplified Modulo $ (2^n - 1) $ Squaring Scheme for
                 Residue Number System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "615--618",
  year =         "2005",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/EURCON.2005.1630004",
  ISBN =         "1-4244-0049-X",
  ISBN-13 =      "978-1-4244-0049-2",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Residue Number System (RNS) is a valuable tool for
                 fast and parallel arithmetic and has a variety of
                 applications in digital signal processing, fault
                 tolerant systems, etc. One of the most fundamental
                 moduli in Residue Number System is modulo (2
                 \ldots{})",
}


bibtype: inproceedings
filename: fparith.bib
label: Harris:2005:IUS
author: David Harris and Ram Krishnamurthy and Mark Anders and Sanu Mathew and Steven Hsu
title: An Improved Unified Scalable Radix-$2$ Montgomery Multiplier
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-109.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: David Harris and Ram Krishnamurthy and Mark Anders and Sanu Mathew and Steven Hsu
rawtitle: An Improved Unified Scalable Radix-$2$ {Montgomery} Multiplier
abstract:
This paper describes an improved version of the Tenca-Koc unified scalable radix-2 Montgomery multiplier with half the latency for small and moderate precision operands and half the queue memory requirement. Like the Tenca-Koc multiplier, this design is reconfigurable to accept any input precision in either $ mathrm GF(p) $ or $ mathrm GF(2 n) $ up to the size of the on-chip memory. An FPGA implementation can perform 1024-bit modular exponentiation in 16 ms using 5598 4-input lookup tables, making it the fastest unified scalable design yet reported.

rawabstract:
This paper describes an improved version of the Tenca-Ko{\c{c}} unified scalable radix-2 Montgomery multiplier with half the latency for small and moderate precision operands and half the queue memory requirement. Like the Tenca-Ko{\c{c}} multiplier, this design is reconfigurable to accept any input precision in either $ \mathrm {GF}(p) $ or $ \mathrm {GF}(2 n) $ up to the size of the on-chip memory. An FPGA implementation can perform 1024-bit modular exponentiation in 16 ms using 5598 4-input lookup tables, making it the fastest unified scalable design yet reported.

entry:
@InProceedings{Harris:2005:IUS,
  author =       "David Harris and Ram Krishnamurthy and Mark Anders and
                 Sanu Mathew and Steven Hsu",
  title =        "An Improved Unified Scalable Radix-$2$ {Montgomery}
                 Multiplier",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-109.pdf",
  abstract =     "This paper describes an improved version of the
                 Tenca-Ko{\c{c}} unified scalable radix-2 Montgomery
                 multiplier with half the latency for small and moderate
                 precision operands and half the queue memory
                 requirement. Like the Tenca-Ko{\c{c}} multiplier, this
                 design is reconfigurable to accept any input precision
                 in either $ \mathrm {GF}(p) $ or $ \mathrm {GF}(2 n) $
                 up to the size of the on-chip memory. An FPGA
                 implementation can perform 1024-bit modular
                 exponentiation in 16 ms using 5598 4-input lookup
                 tables, making it the fastest unified scalable design
                 yet reported.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "7",
}


bibtype: inproceedings
filename: fparith.bib
label: He:2005:MAF
author: Hu He and Zheng Li and Yihe Sun
title: Multiply-add fused float point unit with on-fly denormalized number processing
crossref: IEEE:2005:MSC
pages: 1466--1468
year: 2005
DOI: https://doi.org/10.1109/MWSCAS.2005.1594389
bibdate: Sun Feb 20 10:45:46 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 10:45:46 ???
acknowledgement: ack-nhfb
rawauthor: Hu He and Zheng Li and Yihe Sun
rawtitle: Multiply-add fused float point unit with on-fly denormalized number processing
abstract:
Denormalized numbers are the most difficult type of numbers to implement in float-point units. They are so complex that many designs avoid handling them in hardware. The denormalized number processing cost two much extra clock cycle in software implementation. In this paper, an on-fly floating point denormalized number processing implemented in a multiply-add-fused (MAF) with little extra latency is presented. The denormalized number processing is embedded in a popular MAF data path and fused with the MAF smoothly by representing the denormalized number. The extra latency introduced by the denormalized number processing is cost by the denormalized number detection.

rawabstract:
Denormalized numbers are the most difficult type of numbers to implement in float-point units. They are so complex that many designs avoid handling them in hardware. The denormalized number processing cost two much extra clock cycle in software implementation. In this paper, an on-fly floating point denormalized number processing implemented in a multiply-add-fused (MAF) with little extra latency is presented. The denormalized number processing is embedded in a popular MAF data path and fused with the MAF smoothly by representing the denormalized number. The extra latency introduced by the denormalized number processing is cost by the denormalized number detection.

entry:
@InProceedings{He:2005:MAF,
  author =       "Hu He and Zheng Li and Yihe Sun",
  title =        "Multiply-add fused float point unit with on-fly
                 denormalized number processing",
  crossref =     "IEEE:2005:MSC",
  pages =        "1466--1468",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/MWSCAS.2005.1594389",
  bibdate =      "Sun Feb 20 10:45:46 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Denormalized numbers are the most difficult type of
                 numbers to implement in float-point units. They are so
                 complex that many designs avoid handling them in
                 hardware. The denormalized number processing cost two
                 much extra clock cycle in software implementation. In
                 this paper, an on-fly floating point denormalized
                 number processing implemented in a multiply-add-fused
                 (MAF) with little extra latency is presented. The
                 denormalized number processing is embedded in a popular
                 MAF data path and fused with the MAF smoothly by
                 representing the denormalized number. The extra latency
                 introduced by the denormalized number processing is
                 cost by the denormalized number detection.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hernandez:2005:ACN
author: M. A. Hernandez and N. Romero
title: Accelerated convergence in Newton's method for approximating square roots
journal: j-J-COMPUT-APPL-MATH
volume: 177
number: 1
pages: 225--229
day: 1
month: may
monthnumber: 5
year: 2005
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:00:04 MST 2017
bibtimestamp: 2017.02.25 13:00:04 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042704004315
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: M. A. Hern{\'a}ndez and N. Romero
rawtitle: Accelerated convergence in {Newton}'s method for approximating square roots
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib

entry:
@Article{Hernandez:2005:ACN,
  author =       "M. A. Hern{\'a}ndez and N. Romero",
  title =        "Accelerated convergence in {Newton}'s method for
                 approximating square roots",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "177",
  number =       "1",
  pages =        "225--229",
  day =          "1",
  month =        may,
  year =         "2005",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:00:04 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042704004315",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: incollection
filename: fparith.bib
label: Huang:2005:EMP
author: Liusheng Huang and Hong Zhong and Hong Shen and Yonglong Luo
editor: Hong Shen and Koji Nakano
title: An Efficient Multiple-Precision Division Algorithm
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 971--974
year: 2005
DOI: https://doi.org/10.1109/PDCAT.2005.79
ISBN: 0-7695-2405-2 OR 0769524052
ISBN13: 978-0-7695-2405-4 OR 9780769524054
LCCN: QA76.58 .I5752 2005
bibdate: Mon Dec 09 14:30:16 2013
bibtimestamp: 2013.12.09 14:30:16 ???
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/servlet/opac?punumber=10544
bookpages: xxvi + 1091
rawauthor: Liusheng Huang and Hong Zhong and Hong Shen and Yonglong Luo
raweditor: Hong Shen and Koji Nakano
rawtitle: An Efficient Multiple-Precision Division Algorithm
booktitle:
Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, 2005. PDCAT 2005: 5--8 December 2005, Dalian, China

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib

note:
The authors present an integer-division algorithm that runs three to five times faster than Knuth's 1981 original. However, there is an error in the renormalization algorithm that is corrected in cite Mukhopadhyay:2014:EMP, while retaining the speedup.

rawbooktitle:
{Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, 2005. PDCAT 2005: 5--8 December 2005, Dalian, China}

rawnote:
The authors present an integer-division algorithm that runs three to five times faster than Knuth's 1981 original. However, there is an error in the renormalization algorithm that is corrected in \cite{Mukhopadhyay:2014:EMP}, while retaining the speedup.

entry:
@InCollection{Huang:2005:EMP,
  author =       "Liusheng Huang and Hong Zhong and Hong Shen and
                 Yonglong Luo",
  editor =       "Hong Shen and Koji Nakano",
  booktitle =    "{Sixth International Conference on Parallel and
                 Distributed Computing, Applications and Technologies,
                 2005. PDCAT 2005: 5--8 December 2005, Dalian, China}",
  title =        "An Efficient Multiple-Precision Division Algorithm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "xxvi + 1091",
  pages =        "971--974",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/PDCAT.2005.79",
  ISBN =         "0-7695-2405-2",
  ISBN-13 =      "978-0-7695-2405-4",
  LCCN =         "QA76.58 .I5752 2005",
  bibdate =      "Mon Dec 09 14:30:16 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib",
  note =         "The authors present an integer-division algorithm that
                 runs three to five times faster than Knuth's 1981
                 original. However, there is an error in the
                 renormalization algorithm that is corrected in
                 \cite{Mukhopadhyay:2014:EMP}, while retaining the
                 speedup.",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/servlet/opac?punumber=10544",
}


bibtype: article
filename: fparith.bib
label: Huang:2005:HPL
author: Zhijun Huang and Milos D. Ercegovac
title: High-Performance Low-Power Left-to-Right Array Multiplier Design
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 272--283
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.51
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:15 MDT 2011
bibtimestamp: 2011.07.04 16:17:15 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Zhijun Huang and Milo{\v{s}} D. Ercegovac
rawtitle: High-Performance Low-Power Left-to-Right Array Multiplier Design
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0272abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0272.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0272.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388192.pdf?isnumber=30205&prod=JNL&arnumber=1388192&arSt=+272&ared=+283&arAuthor=Zhijun+Huang%3B+Ercegovac%2C+M.D.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388192&count=13&index=3; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388192

entry:
@Article{Huang:2005:HPL,
  author =       "Zhijun Huang and Milo{\v{s}} D. Ercegovac",
  title =        "High-Performance Low-Power Left-to-Right Array
                 Multiplier Design",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "272--283",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.51",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:15 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0272abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0272.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0272.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388192.pdf?isnumber=30205&prod=JNL&arnumber=1388192&arSt=+272&ared=+283&arAuthor=Zhijun+Huang%3B+Ercegovac%2C+M.D.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388192&count=13&index=3;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388192",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: inproceedings
filename: fparith.bib
label: Jacobi:2005:AFV
author: C. Jacobi and K. Weber and V. Paruthi and J. Baumgartner
title: Automatic formal verification of fused-multiply-add FPUs
crossref: IEEE:2005:DAT
volume: 2
pages: 1298--1303
year: 2005
DOI: https://doi.org/10.1109/DATE.2005.75
bibdate: Sun Feb 20 09:57:04 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 09:57:04 ???
acknowledgement: ack-nhfb
rawauthor: C. Jacobi and K. Weber and V. Paruthi and J. Baumgartner
rawtitle: Automatic formal verification of fused-multiply-add {FPUs}
abstract:
In this paper we describe a fully-automated methodology for formal verification of fused-multiply-add floating point units (FPU). Our methodology verifies an implementation FPU against a simple reference model derived from the processor's architectural specification, which may include all aspects of the IEEE specification including denormal operands and exceptions. Our strategy uses a combination of BDD- and SAT-based symbolic simulation. To make this verification task tractable, we use a combination of case-splitting, multiplier isolation, and automatic model reduction techniques. The case-splitting is defined only in terms of the reference model, which makes this approach easily portable to new designs. The methodology is directly applicable to multi-GHz industrial implementation models (e.g., HDL or gate-level circuit representations) that contain all details of the high-performance transistor-level model, such as aggressive pipelining, clocking, etc. Experimental results are provided to demonstrate the computational efficiency of this approach.

rawabstract:
In this paper we describe a fully-automated methodology for formal verification of fused-multiply-add floating point units (FPU). Our methodology verifies an implementation FPU against a simple reference model derived from the processor's architectural specification, which may include all aspects of the IEEE specification including denormal operands and exceptions. Our strategy uses a combination of BDD- and SAT-based symbolic simulation. To make this verification task tractable, we use a combination of case-splitting, multiplier isolation, and automatic model reduction techniques. The case-splitting is defined only in terms of the reference model, which makes this approach easily portable to new designs. The methodology is directly applicable to multi-GHz industrial implementation models (e.g., HDL or gate-level circuit representations) that contain all details of the high-performance transistor-level model, such as aggressive pipelining, clocking, etc. Experimental results are provided to demonstrate the computational efficiency of this approach.

entry:
@InProceedings{Jacobi:2005:AFV,
  author =       "C. Jacobi and K. Weber and V. Paruthi and J.
                 Baumgartner",
  title =        "Automatic formal verification of fused-multiply-add
                 {FPUs}",
  crossref =     "IEEE:2005:DAT",
  volume =       "2",
  pages =        "1298--1303",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/DATE.2005.75",
  bibdate =      "Sun Feb 20 09:57:04 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper we describe a fully-automated
                 methodology for formal verification of
                 fused-multiply-add floating point units (FPU). Our
                 methodology verifies an implementation FPU against a
                 simple reference model derived from the processor's
                 architectural specification, which may include all
                 aspects of the IEEE specification including denormal
                 operands and exceptions. Our strategy uses a
                 combination of BDD- and SAT-based symbolic simulation.
                 To make this verification task tractable, we use a
                 combination of case-splitting, multiplier isolation,
                 and automatic model reduction techniques. The
                 case-splitting is defined only in terms of the
                 reference model, which makes this approach easily
                 portable to new designs. The methodology is directly
                 applicable to multi-GHz industrial implementation
                 models (e.g., HDL or gate-level circuit
                 representations) that contain all details of the
                 high-performance transistor-level model, such as
                 aggressive pipelining, clocking, etc. Experimental
                 results are provided to demonstrate the computational
                 efficiency of this approach.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Kahan:2005:BTG
author: William Kahan
title: A Brief Tutorial on Gradual Underflow
pages: 15
day: 8
month: jul
monthnumber: 7
year: 2005
bibdate: Fri Jul 15 11:38:13 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.15 11:38:13 ???
note: Prepared for ARITH 17, Tues. 28 June 2005, and subsequently augmented.
URL: http://www.cs.berkeley.edu/~wkahan/ARITH_17U.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web lecture notes.
rawauthor: William Kahan
rawnote: Prepared for ARITH 17, Tues. 28 June 2005, and subsequently augmented.
rawtitle: A Brief Tutorial on Gradual Underflow
entry:
@Misc{Kahan:2005:BTG,
  author =       "William Kahan",
  title =        "A Brief Tutorial on Gradual Underflow",
  howpublished = "World-Wide Web lecture notes.",
  pages =        "15",
  day =          "8",
  month =        jul,
  year =         "2005",
  bibdate =      "Fri Jul 15 11:38:13 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Prepared for ARITH 17, Tues. 28 June 2005, and
                 subsequently augmented.",
  URL =          "http://www.cs.berkeley.edu/~wkahan/ARITH_17U.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: manual
filename: fparith.bib
label: Kahan:2005:DP
author: William Kahan
title: A Demonstration of Presubstitution for $ infty / infty $
pages: 10
day: 5
month: jul
monthnumber: 7
year: 2005
bibdate: Fri Jul 15 11:47:46 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.15 11:47:46 ???
URL: http://www.cs.berkeley.edu/~wkahan/Grail.pdf
acknowledgement: ack-nhfb
rawauthor: William Kahan
rawtitle: A Demonstration of Presubstitution for $ \infty / \infty $
entry:
@Manual{Kahan:2005:DP,
  author =       "William Kahan",
  title =        "A Demonstration of Presubstitution for $ \infty /
                 \infty $",
  pages =        "10",
  day =          "5",
  month =        jul,
  year =         "2005",
  bibdate =      "Fri Jul 15 11:47:46 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.berkeley.edu/~wkahan/Grail.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Kahan:2005:FPA
author: William Kahan
title: Floating-Point Arithmetic Besieged by ``Business Decisions''
pages: 28
day: 5
month: jul
monthnumber: 7
year: 2005
bibdate: Fri Jul 15 12:07:31 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.15 12:07:31 ???
URL: http://www.cs.berkeley.edu/~wkahan/ARITH_17.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web lecture notes.
rawauthor: William Kahan
rawtitle: Floating-Point Arithmetic Besieged by {``Business} Decisions''
note:
A Keynote Address, prepared for the IEEE-Sponsored ARITH 17 Symposium on Computer Arithmetic, delivered on Mon. 27 June 2005 in Hyannis, Massachusetts.

rawnote:
A Keynote Address, prepared for the IEEE-Sponsored ARITH 17 Symposium on Computer Arithmetic, delivered on Mon. 27 June 2005 in Hyannis, Massachusetts.

entry:
@Misc{Kahan:2005:FPA,
  author =       "William Kahan",
  title =        "Floating-Point Arithmetic Besieged by {``Business}
                 Decisions''",
  howpublished = "World-Wide Web lecture notes.",
  pages =        "28",
  day =          "5",
  month =        jul,
  year =         "2005",
  bibdate =      "Fri Jul 15 12:07:31 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "A Keynote Address, prepared for the IEEE-Sponsored
                 ARITH 17 Symposium on Computer Arithmetic, delivered on
                 Mon. 27 June 2005 in Hyannis, Massachusetts.",
  URL =          "http://www.cs.berkeley.edu/~wkahan/ARITH_17.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kahan:2005:OQD
author: William Kahan and Dan Zuras
title: An Open Question to Developers of Numerical Software
journal: j-COMPUTER
volume: 38
number: 5
pages: 91--94
month: may
monthnumber: 5
year: 2005
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Wed May 04 15:33:06 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.05.04 15:33:06 ???
fjournal: Computer
subject: Are signaling NaNs needed?
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
rawauthor: William Kahan and Dan Zuras
rawtitle: An Open Question to Developers of Numerical Software
URL:
http://csdl.computer.org/comp/mags/co/2005/05/r5091abs.htm; http://csdl.computer.org/comp/mags/co/2005/05/r5toc.htm; http://csdl.computer.org/dl/mags/co/2005/05/r5091.pdf

entry:
@Article{Kahan:2005:OQD,
  author =       "William Kahan and Dan Zuras",
  title =        "An Open Question to Developers of Numerical Software",
  journal =      j-COMPUTER,
  volume =       "38",
  number =       "5",
  pages =        "91--94",
  month =        may,
  year =         "2005",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Wed May 04 15:33:06 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/mags/co/2005/05/r5091abs.htm;
                 http://csdl.computer.org/comp/mags/co/2005/05/r5toc.htm;
                 http://csdl.computer.org/dl/mags/co/2005/05/r5091.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  subject =      "Are signaling NaNs needed?",
}


bibtype: article
filename: fparith.bib
label: Kaihara:2005:HAM
author: M. E. Kaihara and N. Takagi
title: A hardware algorithm for modular multiplication / division
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 1
pages: 12--21 54
month: jan
monthnumber: 1
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.1(410)
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:14 MDT 2011
bibtimestamp: 2011.07.04 16:17:14 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1362636
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. E. Kaihara and N. Takagi
rawtitle: A hardware algorithm for modular multiplication\slash division
entry:
@Article{Kaihara:2005:HAM,
  author =       "M. E. Kaihara and N. Takagi",
  title =        "A hardware algorithm for modular multiplication\slash
                 division",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "1",
  pages =        "12--21 54",
  month =        jan,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.1(410)",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:14 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1362636",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: Karlsson:2005:IIL
author: Kent Karlsson
title: ISO / IEC 10967, Language Independent Arithmetic (LIA)
pages: 12--21 54
day: 31
month: oct
monthnumber: 10
year: 2005
bibdate: Sat Dec 17 10:42:52 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.12.17 10:42:52 ???
acknowledgement: ack-nhfb
howpublished: Wikipedia article
rawauthor: Kent Karlsson
rawtitle: {ISO\slash IEC 10967, Language Independent Arithmetic (LIA)}
URL:
http://en.wikipedia.org/wiki/ISO/IEC_10967; http://www.open-std.org/JTC1/SC22/WG11/docs/n364.pdf; http://www.open-std.org/JTC1/SC22/WG11/docs/n462.pdf; http://www.open-std.org/jtc1/sc22/wg11/docs/n490.pdf

abstract:
ISO/IEC 10967, Language independent arithmetic (LIA), is a series of standards on computer arithmetic. It is compatible with IEC 60559 (more known as IEEE 754 or IEC 559), and indeed much of the specifications in parts 2 and 3 are for IEEE 754 special values (though such values are not required).par LIA currently consists of three parts:par begin itemize item [Part 1] Integer and floating point arithmetic, first edition published 1994. item [Part 2] Elementary numerical functions, first edition published 2001. item [Part 3] Complex integer and floating point arithmetic and complex elementary numerical functions, first edition is now (2005) in FDIS stage. end itemize

rawabstract:
ISO/IEC 10967, Language independent arithmetic (LIA), is a series of standards on computer arithmetic. It is compatible with IEC 60559 (more known as IEEE 754 or IEC 559), and indeed much of the specifications in parts 2 and 3 are for IEEE 754 special values (though such values are not required).\par LIA currently consists of three parts:\par \begin{itemize} \item[Part 1] Integer and floating point arithmetic, first edition published 1994. \item[Part 2] Elementary numerical functions, first edition published 2001. \item[Part 3] Complex integer and floating point arithmetic and complex elementary numerical functions, first edition is now (2005) in FDIS stage. \end{itemize}

entry:
@Misc{Karlsson:2005:IIL,
  author =       "Kent Karlsson",
  title =        "{ISO\slash IEC 10967, Language Independent Arithmetic
                 (LIA)}",
  howpublished = "Wikipedia article",
  day =          "31",
  month =        oct,
  year =         "2005",
  bibdate =      "Sat Dec 17 10:42:52 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://en.wikipedia.org/wiki/ISO/IEC_10967;
                 http://www.open-std.org/JTC1/SC22/WG11/docs/n364.pdf;
                 http://www.open-std.org/JTC1/SC22/WG11/docs/n462.pdf;
                 http://www.open-std.org/jtc1/sc22/wg11/docs/n490.pdf",
  abstract =     "ISO/IEC 10967, Language independent arithmetic (LIA),
                 is a series of standards on computer arithmetic. It is
                 compatible with IEC 60559 (more known as IEEE 754 or
                 IEC 559), and indeed much of the specifications in
                 parts 2 and 3 are for IEEE 754 special values (though
                 such values are not required).\par

                 LIA currently consists of three parts:\par
                 \begin{itemize}

                 \item[Part 1] Integer and floating point arithmetic,
                 first edition published 1994.

                 \item[Part 2] Elementary numerical functions, first
                 edition published 2001.

                 \item[Part 3] Complex integer and floating point
                 arithmetic and complex elementary numerical functions,
                 first edition is now (2005) in FDIS
                 stage.

                 \end{itemize}",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kenney:2005:HSM
author: R. D. Kenney and M. J. Schulte
title: High-Speed Multioperand Decimal Adders
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 8
pages: 953--963
month: aug
monthnumber: 8
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.129
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:18 MDT 2011
bibtimestamp: 2011.07.04 16:17:18 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. D. Kenney and M. J. Schulte
rawtitle: High-Speed Multioperand Decimal Adders
URL:
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453497; http://mesa.ece.wisc.edu/publications/cp_2005-04.pdf

abstract:
There is increasing interest in hardware support for decimal arithmetic as a result of recent growth in commercial, financial, and Internet-based applications. Consequently, new specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic. This paper introduces and analyzes three techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Two of the techniques speculate BCD correction values and correct intermediate results while adding the input operands. The first speculates over one addition. The second speculates over two additions. The third technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next more significant digit. Multioperand adder designs are constructed and synthesized for four to 16 input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to several previous techniques for high-speed decimal addition.

keywords:
computer arithmetic; decimal arithmetic; decimal floating-point arithmetic; hardware designs; multioperand adders

rawabstract:
There is increasing interest in hardware support for decimal arithmetic as a result of recent growth in commercial, financial, and Internet-based applications. Consequently, new specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic. This paper introduces and analyzes three techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Two of the techniques speculate BCD correction values and correct intermediate results while adding the input operands. The first speculates over one addition. The second speculates over two additions. The third technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next more significant digit. Multioperand adder designs are constructed and synthesized for four to 16 input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to several previous techniques for high-speed decimal addition.

entry:
@Article{Kenney:2005:HSM,
  author =       "R. D. Kenney and M. J. Schulte",
  title =        "High-Speed Multioperand Decimal Adders",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "8",
  pages =        "953--963",
  month =        aug,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.129",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:18 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453497;
                 http://mesa.ece.wisc.edu/publications/cp_2005-04.pdf",
  abstract =     "There is increasing interest in hardware support for
                 decimal arithmetic as a result of recent growth in
                 commercial, financial, and Internet-based applications.
                 Consequently, new specifications for decimal
                 floating-point arithmetic have been added to the draft
                 revision of the IEEE-754 Standard for Floating-Point
                 Arithmetic. This paper introduces and analyzes three
                 techniques for performing fast decimal addition on
                 multiple binary coded decimal (BCD) operands. Two of
                 the techniques speculate BCD correction values and
                 correct intermediate results while adding the input
                 operands. The first speculates over one addition. The
                 second speculates over two additions. The third
                 technique uses a binary carry-save adder tree and
                 produces a binary sum. Combinational logic is then used
                 to correct the sum and determine the carry into the
                 next more significant digit. Multioperand adder designs
                 are constructed and synthesized for four to 16 input
                 operands. Analyses are performed on the synthesis
                 results and the merits of each technique are discussed.
                 Finally, these techniques are compared to several
                 previous techniques for high-speed decimal addition.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "computer arithmetic; decimal arithmetic; decimal
                 floating-point arithmetic; hardware designs;
                 multioperand adders",
}


bibtype: article
filename: fparith.bib
label: Khabbazian:2005:NMA
author: M. Khabbazian and T. A. Gulliver and V. K. Bhargava
title: A new minimal average weight representation for left-to-right point multiplication methods
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 11
pages: 1454--1459
month: nov
monthnumber: 11
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.173
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:19 MDT 2011
bibtimestamp: 2011.07.04 16:17:19 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1514423
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Khabbazian and T. A. Gulliver and V. K. Bhargava
rawtitle: A new minimal average weight representation for left-to-right point multiplication methods
entry:
@Article{Khabbazian:2005:NMA,
  author =       "M. Khabbazian and T. A. Gulliver and V. K. Bhargava",
  title =        "A new minimal average weight representation for
                 left-to-right point multiplication methods",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "11",
  pages =        "1454--1459",
  month =        nov,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.173",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:19 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1514423",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: techreport
filename: fparith.bib
label: Klarer:2005:DTC
author: Robert Klarer
title: Decimal Types for C++: Second Draft
type: Report
number: C22/WG21/N1839 J16/05-0099
institution: IBM Canada, Ltd.
address: Toronto, ON, Canada
pages: 1454--1459
day: 24
month: jun
monthnumber: 6
year: 2005
bibdate: Thu Mar 02 10:47:15 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.02 10:47:15 ???
URL: http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2005/n1839.html
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Robert Klarer
rawtitle: Decimal Types for {C++}: Second Draft
entry:
@TechReport{Klarer:2005:DTC,
  author =       "Robert Klarer",
  title =        "Decimal Types for {C++}: Second Draft",
  type =         "Report",
  number =       "C22/WG21/N1839 J16/05-0099",
  institution =  "IBM Canada, Ltd.",
  address =      "Toronto, ON, Canada",
  day =          "24",
  month =        jun,
  year =         "2005",
  bibdate =      "Thu Mar 02 10:47:15 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2005/n1839.html",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Kornerup:2005:DSS
author: Peter Kornerup
title: Digit Selection for SRT Division and Square Root
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 294--303
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.47
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:15 MDT 2011
bibtimestamp: 2011.07.04 16:17:15 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Peter Kornerup
rawtitle: Digit Selection for {SRT} Division and Square Root
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0294abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0294.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0294.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388194.pdf?isnumber=30205&prod=JNL&arnumber=1388194&arSt=+294&ared=+303&arAuthor=Kornerup%2C+P.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388194&count=13&index=5; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388194

entry:
@Article{Kornerup:2005:DSS,
  author =       "Peter Kornerup",
  title =        "Digit Selection for {SRT} Division and Square Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "294--303",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.47",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:15 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0294abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0294.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0294.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388194.pdf?isnumber=30205&prod=JNL&arnumber=1388194&arSt=+294&ared=+303&arAuthor=Kornerup%2C+P.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388194&count=13&index=5;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388194",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
  summary =      "The quotient digit selection in the SRT division
                 algorithm is based on a few most significant bits of
                 the remainder and divisor, where the remainder is
                 usually represented in a redundant representation. The
                 number of leading bits needed depends on \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:2005:LGD
author: Peter Kornerup and Jean-Michel Muller
title: Leading Guard Digits in Finite Precision Redundant Representations
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Fri Jun 24 20:32:32 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 20:32:32 ???
URL: http://www.imada.sdu.dk/~kornerup/papers/red-add.pdf
keywords: ARITH-17; Leading guard digits; Multi-operand additions; Redundant representations
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and Jean-Michel Muller
rawtitle: Leading Guard Digits in Finite Precision Redundant Representations
abstract:
Redundant number representations are generally used to allow constant time additions, based on the fact that only bounded carry-ripples take place. But carries may ripple out into positions which may not be needed to represent the final value of the result, and thus a certain amount of leading guard digits are needed to correctly determine the result. Also when cancellation during subtractions occur, there may be nonzero digits in positions not needed to represent the result of the calculation. It is shown here that for normal redundant digit sets with radix greater than two, a single guard digit is sufficient to determine the value of such an arbitrary length prefix of leading non-zero digits. This is also the case for the unsigned carry-save representation, whereas two guard digits are necessary and sufficient for additions in the binary signed-digit and 2's complement carry-save representations.

rawabstract:
Redundant number representations are generally used to allow constant time additions, based on the fact that only bounded carry-ripples take place. But carries may ripple out into positions which may not be needed to represent the final value of the result, and thus a certain amount of leading guard digits are needed to correctly determine the result. Also when cancellation during subtractions occur, there may be nonzero digits in positions not needed to represent the result of the calculation. It is shown here that for normal redundant digit sets with radix greater than two, a single guard digit is sufficient to determine the value of such an arbitrary length prefix of leading non-zero digits. This is also the case for the unsigned carry-save representation, whereas two guard digits are necessary and sufficient for additions in the binary signed-digit and 2's complement carry-save representations.

entry:
@InProceedings{Kornerup:2005:LGD,
  author =       "Peter Kornerup and Jean-Michel Muller",
  title =        "Leading Guard Digits in Finite Precision Redundant
                 Representations",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Fri Jun 24 20:32:32 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.imada.sdu.dk/~kornerup/papers/red-add.pdf",
  abstract =     "Redundant number representations are generally used to
                 allow constant time additions, based on the fact that
                 only bounded carry-ripples take place. But carries may
                 ripple out into positions which may not be needed to
                 represent the final value of the result, and thus a
                 certain amount of leading guard digits are needed to
                 correctly determine the result. Also when cancellation
                 during subtractions occur, there may be nonzero digits
                 in positions not needed to represent the result of the
                 calculation. It is shown here that for normal redundant
                 digit sets with radix greater than two, a single guard
                 digit is sufficient to determine the value of such an
                 arbitrary length prefix of leading non-zero digits.
                 This is also the case for the unsigned carry-save
                 representation, whereas two guard digits are necessary
                 and sufficient for additions in the binary signed-digit
                 and 2's complement carry-save representations.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; Leading guard digits; Multi-operand
                 additions; Redundant representations",
  pagecount =    "6",
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:2005:RCN
author: Peter Kornerup and Jean-Michel Muller
booktitle: Proceedings of the International Meeting on Automated Compliance Systems (IMACS'05), July 2005
title: RN-coding of numbers: Definition and some properties
pages: ??--??
year: 2005
bibdate: Sun Jun 19 14:24:12 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.19 14:24:12 ???
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and Jean-Michel Muller
rawbooktitle: Proceedings of the International Meeting on Automated Compliance Systems {(IMACS'05)}, July 2005
rawtitle: {RN}-coding of numbers: Definition and some properties
URL:
https://www.researchgate.net/publication/243786550_RN-coding_of_numbers_definition_and_some_properties

entry:
@InProceedings{Kornerup:2005:RCN,
  author =       "Peter Kornerup and Jean-Michel Muller",
  booktitle =    "Proceedings of the International Meeting on Automated
                 Compliance Systems {(IMACS'05)}, July 2005",
  title =        "{RN}-coding of numbers: Definition and some
                 properties",
  publisher =    "????",
  address =      "????",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Sun Jun 19 14:24:12 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.researchgate.net/publication/243786550_RN-coding_of_numbers_definition_and_some_properties",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:2005:SPR
author: Peter Kornerup and David Matula
title: Single Precision Reciprocals by Multipartite Table Lookup
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-177.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and David Matula
rawtitle: Single Precision Reciprocals by Multipartite Table Lookup
abstract:
We develop the foundations for confirming monotonicity of a multi-term reciprocal function approximation. We introduce the concept of operand recoding to improve the accuracy of multipartite approximation. The results are applied to provide a proposed four-partite reciprocal implementation with total table size $ approx 27 $ Kbytes, that yields an IEEE standard, single precision sized format (24 bit) reciprocal instruction, that is a one-ulp monotonic reciprocal.

rawabstract:
We develop the foundations for confirming monotonicity of a multi-term reciprocal function approximation. We introduce the concept of operand recoding to improve the accuracy of multipartite approximation. The results are applied to provide a proposed four-partite reciprocal implementation with total table size $ \approx 27 $ Kbytes, that yields an IEEE standard, single precision sized format (24 bit) reciprocal instruction, that is a one-ulp monotonic reciprocal.

entry:
@InProceedings{Kornerup:2005:SPR,
  author =       "Peter Kornerup and David Matula",
  title =        "Single Precision Reciprocals by Multipartite Table
                 Lookup",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-177.pdf",
  abstract =     "We develop the foundations for confirming monotonicity
                 of a multi-term reciprocal function approximation. We
                 introduce the concept of operand recoding to improve
                 the accuracy of multipartite approximation. The results
                 are applied to provide a proposed four-partite
                 reciprocal implementation with total table size $
                 \approx 27 $ Kbytes, that yields an IEEE standard,
                 single precision sized format (24 bit) reciprocal
                 instruction, that is a one-ulp monotonic reciprocal.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "9",
}


bibtype: article
filename: fparith.bib
label: Kulikova:2005:CAS
author: A. A. Kulikova and Yu. V. Prokhorov
title: Completely Asymmetric Stable Laws and Benford's Law
journal: j-THEORY-PROBAB-APPL
volume: 49
number: 1
pages: 163--169
month: mar
monthnumber: 3
year: 2005
CODEN: TPRBAU
ISSN: 0040-585X (print), 1095-7219 (electronic) OR 0040585X (print), 10957219 (electronic)
ISSNL: 0040-585X OR 0040585X
bibdate: Thu Jul 7 19:15:48 MDT 2005
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/TVP/49/1; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.07 19:15:48 MDT
URL: http://epubs.siam.org/sam-bin/dbq/article/98094
fjournal: Theory of Probability and its Applications
keywords: Benford's Law; Zipf's Law
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/tvp
rawauthor: A. A. Kulikova and Yu. V. Prokhorov
rawtitle: Completely Asymmetric Stable Laws and {Benford's Law}
entry:
@Article{Kulikova:2005:CAS,
  author =       "A. A. Kulikova and Yu. V. Prokhorov",
  title =        "Completely Asymmetric Stable Laws and {Benford's
                 Law}",
  journal =      j-THEORY-PROBAB-APPL,
  volume =       "49",
  number =       "1",
  pages =        "163--169",
  month =        mar,
  year =         "2005",
  CODEN =        "TPRBAU",
  ISSN =         "0040-585X (print), 1095-7219 (electronic)",
  ISSN-L =       "0040-585X",
  bibdate =      "Thu Jul 7 19:15:48 MDT 2005",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/TVP/49/1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://epubs.siam.org/sam-bin/dbq/article/98094",
  acknowledgement = ack-nhfb,
  fjournal =     "Theory of Probability and its Applications",
  journal-URL =  "http://epubs.siam.org/tvp",
  keywords =     "Benford's Law; Zipf's Law",
}


bibtype: article
filename: fparith.bib
label: Lang:2005:HTC
author: Tomas Lang and Elisardo Antelo
title: High-Throughput CORDIC-Based Geometry Operations for $3$D Computer Graphics
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 347--361
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.53
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Tom{\'a}s Lang and Elisardo Antelo
rawtitle: High-Throughput {CORDIC}-Based Geometry Operations for {$3$D} Computer Graphics
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0347abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0347.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0347.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388199.pdf?isnumber=30205&prod=JNL&arnumber=1388199&arSt=+347&ared=+361&arAuthor=Lang%2C+T.%3B+Antelo%2C+E.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388199&count=13&index=10; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388199

abstract:
Graphics processors require strong arithmetic support to perform computational kernels over data streams. Because of the current implementation using the basic arithmetic operations, the algorithms are given in algebraic terms. However, since the operations are really of a geometric nature, it seems to us that more flexibility in the implementation is obtained if the description is given in a high-level geometrical form. As a consequence of this line of thought, this paper is an attempt to reconsider some kernels in a graphics processor to obtain implementations that are potentially more scalable than just replicating the modules used in conventional implementations. We present the formulation of representative 3D computer graphics operations in terms of CORDIC-type primitives. Then, we briefly outline a stream processor based on CORDIC-type modules to efficiently implement these graphic operations. We perform a rough comparison with current implementations and conclude that the CORDIC-based alternative might be attractive.

rawabstract:
Graphics processors require strong arithmetic support to perform computational kernels over data streams. Because of the current implementation using the basic arithmetic operations, the algorithms are given in algebraic terms. However, since the operations are really of a geometric nature, it seems to us that more flexibility in the implementation is obtained if the description is given in a high-level geometrical form. As a consequence of this line of thought, this paper is an attempt to reconsider some kernels in a graphics processor to obtain implementations that are potentially more scalable than just replicating the modules used in conventional implementations. We present the formulation of representative 3D computer graphics operations in terms of CORDIC-type primitives. Then, we briefly outline a stream processor based on CORDIC-type modules to efficiently implement these graphic operations. We perform a rough comparison with current implementations and conclude that the CORDIC-based alternative might be attractive.

entry:
@Article{Lang:2005:HTC,
  author =       "Tom{\'a}s Lang and Elisardo Antelo",
  title =        "High-Throughput {CORDIC}-Based Geometry Operations for
                 {$3$D} Computer Graphics",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "347--361",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.53",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0347abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0347.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0347.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388199.pdf?isnumber=30205&prod=JNL&arnumber=1388199&arSt=+347&ared=+361&arAuthor=Lang%2C+T.%3B+Antelo%2C+E.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388199&count=13&index=10;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388199",
  abstract =     "Graphics processors require strong arithmetic support
                 to perform computational kernels over data streams.
                 Because of the current implementation using the basic
                 arithmetic operations, the algorithms are given in
                 algebraic terms. However, since the operations are
                 really of a geometric nature, it seems to us that more
                 flexibility in the implementation is obtained if the
                 description is given in a high-level geometrical form.
                 As a consequence of this line of thought, this paper is
                 an attempt to reconsider some kernels in a graphics
                 processor to obtain implementations that are
                 potentially more scalable than just replicating the
                 modules used in conventional implementations. We
                 present the formulation of representative 3D computer
                 graphics operations in terms of CORDIC-type primitives.
                 Then, we briefly outline a stream processor based on
                 CORDIC-type modules to efficiently implement these
                 graphic operations. We perform a rough comparison with
                 current implementations and conclude that the
                 CORDIC-based alternative might be attractive.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: techreport
filename: fparith.bib
label: Langlois:2005:STS
author: P. Langlois and N. Louvet
title: Solving Triangular Systems More Accurately and Efficiently
type: Research Report
number: RR2005-02
institution: Equipe de Recherche DALI, Laboratoire LP2A, Universite de Perpignan, Via Domitia
address: Perpignan, France
pages: 15
day: 9
month: may
monthnumber: 5
year: 2005
bibdate: Fri Jan 06 07:54:13 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.01.06 07:54:13 ???
URL: http://webdali.univ-perp.fr/RR/rr2005-02.pdf
acknowledgement: ack-nhfb
rawauthor: P. Langlois and N. Louvet
rawtitle: Solving Triangular Systems More Accurately and Efficiently
abstract:
We present a new algorithm that solves linear triangular systems accurately and efficiently. By accurately, we mean that this algorithm should yield a solution as accurate as the one computed in twice the working precision. By efficiently, we mean that its implementation should run faster than the corresponding XBLAS routine with the same output accuracy.

keywords:
error-free transformations; extended precision; IEEE-754 floating point arithmetic; substitution algorithm; triangular linear system; XBLAS

rawabstract:
We present a new algorithm that solves linear triangular systems accurately and efficiently. By accurately, we mean that this algorithm should yield a solution as accurate as the one computed in twice the working precision. By efficiently, we mean that its implementation should run faster than the corresponding XBLAS routine with the same output accuracy.

entry:
@TechReport{Langlois:2005:STS,
  author =       "P. Langlois and N. Louvet",
  title =        "Solving Triangular Systems More Accurately and
                 Efficiently",
  type =         "Research Report",
  number =       "RR2005-02",
  institution =  "{\'E}quipe de Recherche DALI, Laboratoire LP2A,
                 Universit{\'e} de Perpignan, Via Domitia",
  address =      "Perpignan, France",
  pages =        "15",
  day =          "9",
  month =        may,
  year =         "2005",
  bibdate =      "Fri Jan 06 07:54:13 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://webdali.univ-perp.fr/RR/rr2005-02.pdf",
  abstract =     "We present a new algorithm that solves linear
                 triangular systems accurately and efficiently. By
                 accurately, we mean that this algorithm should yield a
                 solution as accurate as the one computed in twice the
                 working precision. By efficiently, we mean that its
                 implementation should run faster than the corresponding
                 XBLAS routine with the same output accuracy.",
  acknowledgement = ack-nhfb,
  keywords =     "error-free transformations; extended precision;
                 IEEE-754 floating point arithmetic; substitution
                 algorithm; triangular linear system; XBLAS",
}


bibtype: techreport
filename: fparith.bib
label: Lauter:2005:BBB
author: Christoph Quirin Lauter
title: Basic building blocks for a triple-double intermediate format
type: Technical Report
number: RR-5702
institution: Inria
pages: iii + 67 + i
year: 2005
bibdate: Sat Apr 01 08:05:25 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.04.01 08:05:25 ???
URL: http://hal.inria.fr/inria-00070314; https://hal.inria.fr/inria-00070314/document
keywords: correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Christoph Quirin Lauter
rawtitle: Basic building blocks for a triple-double intermediate format
abstract:
The implementation of correctly rounded elementary functions needs high intermediate accuracy before final rounding. This accuracy can be provided by (pseudo-) expansions of size three, i.e. a triple-double format. The report presents all basic operators for such a format. Triple-double numbers can be redundant. A renormalization procedure is presented and proven. Elementary functions' implementations need addition and multiplication sequences. These operators must take operands in double, double-double and triple-double format. The results must be accordingly in one of the formats. Several procedures are presented. Proofs are given for their accuracy bounds. Intermediate triple-double results must finally be correctly rounded to double precision. Two effective rounding sequences are presented, one for round-to-nearest mode, one for the directed rounding modes. Their complete proofs constitute half of the report.

rawabstract:
The implementation of correctly rounded elementary functions needs high intermediate accuracy before final rounding. This accuracy can be provided by (pseudo-) expansions of size three, i.e. a triple-double format. The report presents all basic operators for such a format. Triple-double numbers can be redundant. A renormalization procedure is presented and proven. Elementary functions' implementations need addition and multiplication sequences. These operators must take operands in double, double-double and triple-double format. The results must be accordingly in one of the formats. Several procedures are presented. Proofs are given for their accuracy bounds. Intermediate triple-double results must finally be correctly rounded to double precision. Two effective rounding sequences are presented, one for round-to-nearest mode, one for the directed rounding modes. Their complete proofs constitute half of the report.

entry:
@TechReport{Lauter:2005:BBB,
  author =       "Christoph Quirin Lauter",
  title =        "Basic building blocks for a triple-double intermediate
                 format",
  type =         "Technical Report",
  number =       "RR-5702",
  institution =  "Inria",
  address =      "????",
  pages =        "iii + 67 + i",
  year =         "2005",
  bibdate =      "Sat Apr 01 08:05:25 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://hal.inria.fr/inria-00070314;
                 https://hal.inria.fr/inria-00070314/document",
  abstract =     "The implementation of correctly rounded elementary
                 functions needs high intermediate accuracy before final
                 rounding. This accuracy can be provided by (pseudo-)
                 expansions of size three, i.e. a triple-double format.
                 The report presents all basic operators for such a
                 format. Triple-double numbers can be redundant. A
                 renormalization procedure is presented and proven.
                 Elementary functions' implementations need addition and
                 multiplication sequences. These operators must take
                 operands in double, double-double and triple-double
                 format. The results must be accordingly in one of the
                 formats. Several procedures are presented. Proofs are
                 given for their accuracy bounds. Intermediate
                 triple-double results must finally be correctly rounded
                 to double precision. Two effective rounding sequences
                 are presented, one for round-to-nearest mode, one for
                 the directed rounding modes. Their complete proofs
                 constitute half of the report.",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; floating-point arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Lawlor:2005:PDP
author: Orion Lawlor and Hari Govind and Isaac Dooley and Michael Breitenfeld and Laxmikant Kale
title: Performance Degradation in the Presence of Subnormal Floating-Point Values
pages: iii + 67 + i
year: 2005
bibdate: Sat Mar 04 17:10:07 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.04 17:10:07 ???
URL: http://charm.cs.uiuc.edu/presentations/OSIHPA/html/
acknowledgement: ack-nhfb
rawauthor: Orion Lawlor and Hari Govind and Isaac Dooley and Michael Breitenfeld and Laxmikant Kale
rawtitle: Performance Degradation in the Presence of Subnormal Floating-Point Values
howpublished:
World-Wide Web slides from the Workshop on Operating System Interfaces in High Performance Applications 2005

entry:
@Misc{Lawlor:2005:PDP,
  author =       "Orion Lawlor and Hari Govind and Isaac Dooley and
                 Michael Breitenfeld and Laxmikant Kale",
  title =        "Performance Degradation in the Presence of Subnormal
                 Floating-Point Values",
  howpublished = "World-Wide Web slides from the Workshop on Operating
                 System Interfaces in High Performance Applications
                 2005",
  year =         "2005",
  bibdate =      "Sat Mar 04 17:10:07 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://charm.cs.uiuc.edu/presentations/OSIHPA/html/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Lee:2005:LCB
author: Chiou-Yng Lee and Jenn-Shyong Horng and I-Chang Jou and Erl-Huei Lu
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 9
pages: 1061--1070
month: sep
monthnumber: 9
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.147
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:18 MDT 2011
bibtimestamp: 2011.07.04 16:17:18 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1471668
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Chiou-Yng Lee and Jenn-Shyong Horng and I-Chang Jou and Erl-Huei Lu
title:
Low-complexity bit-parallel systolic Montgomery multipliers for special classes of $ mathrm GF(2^m) $

rawtitle:
Low-complexity bit-parallel systolic {Montgomery} multipliers for special classes of {$ \mathrm {GF}(2^m) $}

entry:
@Article{Lee:2005:LCB,
  author =       "Chiou-Yng Lee and Jenn-Shyong Horng and I-Chang Jou
                 and Erl-Huei Lu",
  title =        "Low-complexity bit-parallel systolic {Montgomery}
                 multipliers for special classes of {$ \mathrm {GF}(2^m)
                 $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "9",
  pages =        "1061--1070",
  month =        sep,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.147",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:18 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1471668",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Lee:2005:OHF
author: D.-U. Lee and A. A. Gaffar and O. Mencer and W. Luk
title: Optimizing hardware function evaluation
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 12
pages: 1520--1531
month: dec
monthnumber: 12
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.201
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:04:26 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:04:26 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D.-U. Lee and A. A. Gaffar and O. Mencer and W. Luk
rawtitle: Optimizing hardware function evaluation
abstract:
We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation $ f(x) $ typically consists of range reduction and the actual evaluation on a small convenient interval such as $ [0, pi / 2) $ for $ sin (x) $. We investigate the impact of hardware function evaluation with range reduction for a given range and precision of $x$ and $ f(x) $ on area and speed. An automated bit-width optimization technique for minimizing the sizes of the operators in the data paths is also proposed. We explore a vast design space for fixed-point $ sin (x) $, $ log (x) $, and $ sqrt x $ accurate to one unit in the last place using MATLAB and ASC, a stream compiler for field-programmable gate arrays (FPGAs). In this study, we implement over 2,000 placed-and-routed FPGA designs, resulting in over 100 million application-specific integrated circuit (ASIC) equivalent gates. We provide optimal function evaluation results for range and precision combinations between 8 and 48 bits.

keywords:
application specific integrated circuits; application-specific integrated circuit equivalent gates; ASC; ASIC; automated bit-width optimization technique; circuit optimisation; computer arithmetic; elementary function approximation; field programmable gate arrays; field-programmable gate arrays; fixed point arithmetic; fixed-point arithmetic; FPGA; hardware function evaluation optimisation; logic design; MATLAB; minimax approximation; range reduction; stream compiler

rawabstract:
We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation $ f(x) $ typically consists of range reduction and the actual evaluation on a small convenient interval such as $ [0, \pi / 2) $ for $ \sin (x) $. We investigate the impact of hardware function evaluation with range reduction for a given range and precision of $x$ and $ f(x) $ on area and speed. An automated bit-width optimization technique for minimizing the sizes of the operators in the data paths is also proposed. We explore a vast design space for fixed-point $ \sin (x) $, $ \log (x) $, and $ \sqrt {x} $ accurate to one unit in the last place using MATLAB and ASC, a stream compiler for field-programmable gate arrays (FPGAs). In this study, we implement over 2,000 placed-and-routed FPGA designs, resulting in over 100 million application-specific integrated circuit (ASIC) equivalent gates. We provide optimal function evaluation results for range and precision combinations between 8 and 48 bits.

entry:
@Article{Lee:2005:OHF,
  author =       "D.-U. Lee and A. A. Gaffar and O. Mencer and W. Luk",
  title =        "Optimizing hardware function evaluation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "12",
  pages =        "1520--1531",
  month =        dec,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.201",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:04:26 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a methodology and an automated system for
                 function evaluation unit generation. Our system selects
                 the best function evaluation hardware for a given
                 function, accuracy requirements, technology mapping,
                 and optimization metrics, such as area, throughput, and
                 latency. Function evaluation $ f(x) $ typically
                 consists of range reduction and the actual evaluation
                 on a small convenient interval such as $ [0, \pi / 2) $
                 for $ \sin (x) $. We investigate the impact of hardware
                 function evaluation with range reduction for a given
                 range and precision of $x$ and $ f(x) $ on area and
                 speed. An automated bit-width optimization technique
                 for minimizing the sizes of the operators in the data
                 paths is also proposed. We explore a vast design space
                 for fixed-point $ \sin (x) $, $ \log (x) $, and $ \sqrt
                 {x} $ accurate to one unit in the last place using
                 MATLAB and ASC, a stream compiler for
                 field-programmable gate arrays (FPGAs). In this study,
                 we implement over 2,000 placed-and-routed FPGA designs,
                 resulting in over 100 million application-specific
                 integrated circuit (ASIC) equivalent gates. We provide
                 optimal function evaluation results for range and
                 precision combinations between 8 and 48 bits.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "application specific integrated circuits;
                 application-specific integrated circuit equivalent
                 gates; ASC; ASIC; automated bit-width optimization
                 technique; circuit optimisation; computer arithmetic;
                 elementary function approximation; field programmable
                 gate arrays; field-programmable gate arrays; fixed
                 point arithmetic; fixed-point arithmetic; FPGA;
                 hardware function evaluation optimisation; logic
                 design; MATLAB; minimax approximation; range reduction;
                 stream compiler",
}


bibtype: article
filename: fparith.bib
label: Lefevre:2005:GMP
author: Vincent Lefevre
title: The Generic Multiple-Precision Floating-Point Addition With Exact Rounding (as in the MPFR Library)
journal: arXiv.org
pages: ??--??
day: 11
month: may
monthnumber: 5
year: 2005
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/cs/0505027
subject: Data Structures and Algorithms (cs.DS)
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre
abstract:
We study the multiple-precision addition of two positive floating-point numbers in base 2, with exact rounding, as specified in the MPFR library, i.e. where each number has its own precision. We show how the best possible complexity (up to a constant factor that depends on the implementation) can be obtain.

rawtitle:
The Generic Multiple-Precision Floating-Point Addition With Exact Rounding (as in the {MPFR} Library)

entry:
@Article{Lefevre:2005:GMP,
  author =       "Vincent Lef{\`e}vre",
  title =        "The Generic Multiple-Precision Floating-Point Addition
                 With Exact Rounding (as in the {MPFR} Library)",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "11",
  month =        may,
  year =         "2005",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/cs/0505027",
  abstract =     "We study the multiple-precision addition of two
                 positive floating-point numbers in base 2, with exact
                 rounding, as specified in the MPFR library, i.e. where
                 each number has its own precision. We show how the best
                 possible complexity (up to a constant factor that
                 depends on the implementation) can be obtain.",
  acknowledgement = ack-nhfb,
  subject =      "Data Structures and Algorithms (cs.DS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Lefevre:2005:NRD
author: Vincent Lefevre
title: New Results on the Distance Between a Segment and $ mathbb Z^2 $. Application to the Exact Rounding
crossref: Montuschi:2005:PIS
pages: 68--75
year: 2005
DOI: https://doi.org/10.1109/ARITH.2005.32
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-147.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre
abstract:
This paper presents extensions to Lefevre's algorithm that computes a lower bound on the distance between a segment and a regular grid $ Z^2 $. This algorithm and, in particular, the extensions are useful in the search for worst cases for the exact rounding of unary elementary functions or base-conversion functions. The proof that is presented here is simpler and less technical than the original proof. This paper also gives benchmark results with various optimization parameters, explanations of these results, and an application to base conversion.

rawabstract:
This paper presents extensions to Lef{\'e}vre's algorithm that computes a lower bound on the distance between a segment and a regular grid $ Z^2 $. This algorithm and, in particular, the extensions are useful in the search for worst cases for the exact rounding of unary elementary functions or base-conversion functions. The proof that is presented here is simpler and less technical than the original proof. This paper also gives benchmark results with various optimization parameters, explanations of these results, and an application to base conversion.

rawtitle:
New Results on the Distance Between a Segment and {$ \mathbb {Z}^2 $}. Application to the Exact Rounding

entry:
@InProceedings{Lefevre:2005:NRD,
  author =       "Vincent Lef{\`e}vre",
  title =        "New Results on the Distance Between a Segment and {$
                 \mathbb {Z}^2 $}. Application to the Exact Rounding",
  crossref =     "Montuschi:2005:PIS",
  pages =        "68--75",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ARITH.2005.32",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-147.pdf",
  abstract =     "This paper presents extensions to Lef{\'e}vre's
                 algorithm that computes a lower bound on the distance
                 between a segment and a regular grid $ Z^2 $. This
                 algorithm and, in particular, the extensions are useful
                 in the search for worst cases for the exact rounding of
                 unary elementary functions or base-conversion
                 functions. The proof that is presented here is simpler
                 and less technical than the original proof. This paper
                 also gives benchmark results with various optimization
                 parameters, explanations of these results, and an
                 application to base conversion.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2005:HIA
author: L. Li and A. Fit-Florea and M. A. Thornton and D. W. Matula
crossref: IEEE:2005:ICS
pages: ??--??
year: 2005
bibdate: Fri Jun 24 15:56:30 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 15:56:30 ???
acknowledgement: ack-nhfb
rawauthor: L. Li and A. Fit-Florea and M. A. Thornton and D. W. Matula
title:
Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo-$ 2^k $

rawtitle:
Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo-$ 2^k $

entry:
@InProceedings{Li:2005:HIA,
  author =       "L. Li and A. Fit-Florea and M. A. Thornton and D. W.
                 Matula",
  title =        "Hardware Implementation of an Additive Bit-Serial
                 Algorithm for the Discrete Logarithm Modulo-$ 2^k $",
  crossref =     "IEEE:2005:ICS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Fri Jun 24 15:56:30 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2005:NBI
author: L. Li and A. Fit-Florea and M. A. Thornton and D. W. Matula
title: A New Binary Integer Number System with Simplified Hardware Support
crossref: IEEE:2005:PII
pages: ??--??
year: 2005
bibdate: Fri Jun 24 15:58:49 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 15:58:49 ???
note: Submitted.
acknowledgement: ack-nhfb
rawauthor: L. Li and A. Fit-Florea and M. A. Thornton and D. W. Matula
rawnote: Submitted.
rawtitle: A New Binary Integer Number System with Simplified Hardware Support
entry:
@InProceedings{Li:2005:NBI,
  author =       "L. Li and A. Fit-Florea and M. A. Thornton and D. W.
                 Matula",
  title =        "A New Binary Integer Number System with Simplified
                 Hardware Support",
  crossref =     "IEEE:2005:PII",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Fri Jun 24 15:58:49 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Submitted.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Li:2005:RPE
author: C. Li and S. Pion and C. K. Yap
title: Recent progress in exact geometric computation
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 85--111
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.006
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Thu Oct 17 10:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 10:09:18 ???
fjournal: Journal of Logic and Algebraic Programming
remark: Special issue on Practical development of exact real number computation.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: C. Li and S. Pion and C. K. Yap
rawtitle: Recent progress in exact geometric computation
entry:
@Article{Li:2005:RPE,
  author =       "C. Li and S. Pion and C. K. Yap",
  title =        "Recent progress in exact geometric computation",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "85--111",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.006",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Thu Oct 17 10:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  remark =       "Special issue on Practical development of exact real
                 number computation.",
}


bibtype: article
filename: fparith.bib
label: Lorencz:2005:SFA
author: Robert Lorencz and Josef Hlavac
title: Subtraction-free Almost Montgomery Inverse algorithm
journal: j-INFO-PROC-LETT
volume: 94
number: 1
pages: 11--14
day: 15
month: apr
monthnumber: 4
year: 2005
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Thu Mar 31 18:41:00 MDT 2011
bibtimestamp: 2011.03.31 18:41:00 MDT
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: R{\'o}bert L{\'o}rencz and Josef Hlav{\'a}{\v{c}}
rawtitle: Subtraction-free {Almost Montgomery Inverse} algorithm
bibsource:
http://www.sciencedirect.com/science/journal/00200190; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Lorencz:2005:SFA,
  author =       "R{\'o}bert L{\'o}rencz and Josef Hlav{\'a}{\v{c}}",
  title =        "Subtraction-free {Almost Montgomery Inverse}
                 algorithm",
  journal =      j-INFO-PROC-LETT,
  volume =       "94",
  number =       "1",
  pages =        "11--14",
  day =          "15",
  month =        apr,
  year =         "2005",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Thu Mar 31 18:41:00 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/00200190;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: article
filename: fparith.bib
label: Lorenz:2005:VTB
author: J. Lorenz and S. Kral and F. Franchetti and C. W. Ueberhuber
title: Vectorization techniques for the Blue Gene/L double FPU
journal: j-IBM-JRD
volume: 49
number: 2/3
pages: 437--446
year: 2005
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Wed Jun 1 08:14:41 MDT 2005
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.01 08:14:41 MDT
URL: http://www.research.ibm.com/journal/rd/492/lorenz.pdf
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: J. Lorenz and S. Kral and F. Franchetti and C. W. Ueberhuber
rawtitle: Vectorization techniques for the {Blue Gene/L} double {FPU}
abstract:
This paper presents vectorization techniques tailored to meet the specifics of the two-way single-instruction multiple-data (SIMD) double-precision floating-point unit (FPU), which is a core element of the node application-specific integrated circuit (ASIC) chips of the IBM 360-teraflops Blue Gene/L supercomputer. This paper focuses on the general-purpose basic-block vectorization and optimization methods as they are incorporated in the Vienna MAP vectorizer and optimizer. The innovative technologies presented here, which have consistently delivered superior performance and portability across a wide range of platforms, were carried over to prototypes of Blue Gene/L and joined with the automatic performance-tuning system known as Fastest Fourier Transform in the West (FFTW). FFTW performance-optimization facilities working with the compiler technologies presented in this paper are able to produce vectorized fast Fourier transform (FFT) codes that are tuned automatically to single Blue Gene/L processors and are up to 80% faster than the best-performing scalar FFT codes generated by FFTW.

rawabstract:
This paper presents vectorization techniques tailored to meet the specifics of the two-way single-instruction multiple-data (SIMD) double-precision floating-point unit (FPU), which is a core element of the node application-specific integrated circuit (ASIC) chips of the IBM 360-teraflops Blue Gene/L supercomputer. This paper focuses on the general-purpose basic-block vectorization and optimization methods as they are incorporated in the Vienna MAP vectorizer and optimizer. The innovative technologies presented here, which have consistently delivered superior performance and portability across a wide range of platforms, were carried over to prototypes of Blue Gene/L and joined with the automatic performance-tuning system known as Fastest Fourier Transform in the West (FFTW). FFTW performance-optimization facilities working with the compiler technologies presented in this paper are able to produce vectorized fast Fourier transform (FFT) codes that are tuned automatically to single Blue Gene/L processors and are up to 80\% faster than the best-performing scalar FFT codes generated by FFTW.

entry:
@Article{Lorenz:2005:VTB,
  author =       "J. Lorenz and S. Kral and F. Franchetti and C. W.
                 Ueberhuber",
  title =        "Vectorization techniques for the {Blue Gene/L} double
                 {FPU}",
  journal =      j-IBM-JRD,
  volume =       "49",
  number =       "2/3",
  pages =        "437--446",
  month =        "????",
  year =         "2005",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Jun 1 08:14:41 MDT 2005",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/492/lorenz.pdf",
  abstract =     "This paper presents vectorization techniques tailored
                 to meet the specifics of the two-way single-instruction
                 multiple-data (SIMD) double-precision floating-point
                 unit (FPU), which is a core element of the node
                 application-specific integrated circuit (ASIC) chips of
                 the IBM 360-teraflops Blue Gene/L supercomputer. This
                 paper focuses on the general-purpose basic-block
                 vectorization and optimization methods as they are
                 incorporated in the Vienna MAP vectorizer and
                 optimizer. The innovative technologies presented here,
                 which have consistently delivered superior performance
                 and portability across a wide range of platforms, were
                 carried over to prototypes of Blue Gene/L and joined
                 with the automatic performance-tuning system known as
                 Fastest Fourier Transform in the West (FFTW). FFTW
                 performance-optimization facilities working with the
                 compiler technologies presented in this paper are able
                 to produce vectorized fast Fourier transform (FFT)
                 codes that are tuned automatically to single Blue
                 Gene/L processors and are up to 80\% faster than the
                 best-performing scalar FFT codes generated by FFTW.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  ordernumber =  "G322-0240",
}


bibtype: inproceedings
filename: fparith.bib
label: Macchetti:2005:QPH
author: Marco Macchetti and Luigi Dadda
title: Quasi-Pipelined Hash Circuits
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-149.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Marco Macchetti and Luigi Dadda
rawtitle: Quasi-Pipelined Hash Circuits
abstract:
Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on the class of dedicated hash functions, whose general construction is presented; the peculiar arrangement of sequential and combinational units makes the application of pipelining techniques to these constructions not trivial. We formalize here an optimization technique called quasipipelining, whose goal is to optimize the critical path and thus to increase the clock frequency in dedicated hardware implementations. The SHA-2 algorithm has been previously examined by Dadda et al., with specific versions of quasipipelining; here, a full generalization of the technique is presented, along with application to the SHA-1 algorithm. Quasi-pipelining could be as well applied to future hashing algorithms, provided they are designed along the same lines as those of the SHA family.

rawabstract:
Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on the class of dedicated hash functions, whose general construction is presented; the peculiar arrangement of sequential and combinational units makes the application of pipelining techniques to these constructions not trivial. We formalize here an optimization technique called quasipipelining, whose goal is to optimize the critical path and thus to increase the clock frequency in dedicated hardware implementations. The SHA-2 algorithm has been previously examined by Dadda et al., with specific versions of quasipipelining; here, a full generalization of the technique is presented, along with application to the SHA-1 algorithm. Quasi-pipelining could be as well applied to future hashing algorithms, provided they are designed along the same lines as those of the SHA family.

entry:
@InProceedings{Macchetti:2005:QPH,
  author =       "Marco Macchetti and Luigi Dadda",
  title =        "Quasi-Pipelined Hash Circuits",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-149.pdf",
  abstract =     "Hash functions are an important cryptographic
                 primitive. They are used to obtain a fixed-size
                 fingerprint, or hash value, of an arbitrary long
                 message. We focus particularly on the class of
                 dedicated hash functions, whose general construction is
                 presented; the peculiar arrangement of sequential and
                 combinational units makes the application of pipelining
                 techniques to these constructions not trivial. We
                 formalize here an optimization technique called
                 quasipipelining, whose goal is to optimize the critical
                 path and thus to increase the clock frequency in
                 dedicated hardware implementations. The SHA-2 algorithm
                 has been previously examined by Dadda et al., with
                 specific versions of quasipipelining; here, a full
                 generalization of the technique is presented, along
                 with application to the SHA-1 algorithm.
                 Quasi-pipelining could be as well applied to future
                 hashing algorithms, provided they are designed along
                 the same lines as those of the SHA family.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Markstein:2005:FSM
author: Peter Markstein
title: A Fast-Start Method for Computing the Inverse Tangent
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-112.pdf
keywords: ARITH-17; IA-64; Itanium-2
acknowledgement: ack-nhfb
rawauthor: Peter Markstein
rawtitle: A Fast-Start Method for Computing the Inverse Tangent
abstract:
In a search for an algorithm to compute $ atan (x) $ which has both low latency and few floating point instructions, an interesting variant of familiar trigonometry formulas was discovered that allow the start of argument reduction to commence before any references to tables stored in memory are needed. Low latency makes the method suitable for a closed subroutine, and few floating point operations make the method advantageous for a software-pipelined implementation.

rawabstract:
In a search for an algorithm to compute $ \atan (x) $ which has both low latency and few floating point instructions, an interesting variant of familiar trigonometry formulas was discovered that allow the start of argument reduction to commence before any references to tables stored in memory are needed. Low latency makes the method suitable for a closed subroutine, and few floating point operations make the method advantageous for a software-pipelined implementation.

entry:
@InProceedings{Markstein:2005:FSM,
  author =       "Peter Markstein",
  title =        "A Fast-Start Method for Computing the Inverse
                 Tangent",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-112.pdf",
  abstract =     "In a search for an algorithm to compute $ \atan (x) $
                 which has both low latency and few floating point
                 instructions, an interesting variant of familiar
                 trigonometry formulas was discovered that allow the
                 start of argument reduction to commence before any
                 references to tables stored in memory are needed. Low
                 latency makes the method suitable for a closed
                 subroutine, and few floating point operations make the
                 method advantageous for a software-pipelined
                 implementation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; IA-64; Itanium-2",
  pagecount =    "6",
}


bibtype: techreport
filename: fparith.bib
label: Marques:2005:BIF
author: Osni A. Marques and E. Jason Riedy and Christof Vomel
title: Benefits of IEEE-754 Features in Modern Symmetric Tridiagonal Eigensolvers
type: LAPACK Working Note
number: 172
institution: Computer Science Division, University of California, Berkeley
address: Berkeley, CA, USA
pages: 22
day: 30
month: sep
monthnumber: 9
year: 2005
MRclass: 15A18, 15A23.
bibdate: Mon Mar 20 12:18:56 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.20 12:18:56 ???
note: Also issued as Technical Report UCB//CSD-05-1414.
URL: http://www.netlib.org/lapack/lawnspdf/lawn172.pdf
acknowledgement: ack-nhfb
rawauthor: Osni A. Marques and E. Jason Riedy and Christof V{\"o}mel
rawnote: Also issued as Technical Report UCB//CSD-05-1414.
rawtitle: Benefits of {IEEE-754} Features in Modern Symmetric Tridiagonal Eigensolvers
abstract:
Bisection is one of the most common methods used to compute the eigenvalues of symmetric tridiagonal matrices. Bisection relies on the Sturm count: for a given shift $ sigma $, the number of negative pivots in the factorization $ T sigma I = L D L^T $ equals the number of eigenvalues of $T$ that are smaller than $ sigma $. In IEEE-754 arithmetic, the value $ infty $ permits the computation to continue past a zero pivot, producing a correct Sturm count when $T$ is unreduced. Demmel and Li showed in the 90s that using $ infty $ rather than testing for zero pivots within the loop could improve performance significantly on certain architectures. When eigenvalues are to be computed to high relative accuracy, it is often preferable to work with $ L D L^T $ factorizations instead of the original tridiagonal $T$, see for example the MRRR algorithm. In these cases, the Sturm count has to be computed from $ L D L^T $. The differential stationary and progressive qds algorithms are the methods of choice. While it seems trivial to replace $T$ by $ L D L^T $, in reality these algorithms are more complicated: in IEEE-754 arithmetic, a zero pivot produces an overflow, followed by an invalid exception (NaN), that renders the Sturm count incorrect. We present alternative, safe formulations that are guaranteed to produce the correct result. Benchmarking these algorithms on a variety of platforms shows that the original formulation without tests is always faster provided no exception occurs. The transforms see speed-ups of up to $ 2.6 times $ over the careful formulations. Tests on industrial matrices show that encountering exceptions in practice is rare. This leads to the following design: First, compute the Sturm count by the fast but unsafe algorithm. Then, if an exception occurred, recompute the count by a safe, slower alternative. The new Sturm count algorithms improve the speed of bisection by up to $ 2 times $ on our test matrices. Furthermore, unlike the traditional tiny-pivot substitution, proper use of IEEE-754 features provides a careful formulation that imposes no input range restrictions.

keywords:
differential qds algorithms; IEEE-754 arithmetic; IEEE-754 performance; LAPACK; MRRR algorithm; NaN arithmetic

rawabstract:
Bisection is one of the most common methods used to compute the eigenvalues of symmetric tridiagonal matrices. Bisection relies on the Sturm count: for a given shift $ \sigma $, the number of negative pivots in the factorization $ T \sigma I = L D L^T $ equals the number of eigenvalues of $T$ that are smaller than $ \sigma $. In IEEE-754 arithmetic, the value $ \infty $ permits the computation to continue past a zero pivot, producing a correct Sturm count when $T$ is unreduced. Demmel and Li showed in the 90s that using $ \infty $ rather than testing for zero pivots within the loop could improve performance significantly on certain architectures. When eigenvalues are to be computed to high relative accuracy, it is often preferable to work with $ L D L^T $ factorizations instead of the original tridiagonal $T$, see for example the MRRR algorithm. In these cases, the Sturm count has to be computed from $ L D L^T $. The differential stationary and progressive qds algorithms are the methods of choice. While it seems trivial to replace $T$ by $ L D L^T $, in reality these algorithms are more complicated: in IEEE-754 arithmetic, a zero pivot produces an overflow, followed by an invalid exception (NaN), that renders the Sturm count incorrect. We present alternative, safe formulations that are guaranteed to produce the correct result. Benchmarking these algorithms on a variety of platforms shows that the original formulation without tests is always faster provided no exception occurs. The transforms see speed-ups of up to $ 2.6 \times $ over the careful formulations. Tests on industrial matrices show that encountering exceptions in practice is rare. This leads to the following design: First, compute the Sturm count by the fast but unsafe algorithm. Then, if an exception occurred, recompute the count by a safe, slower alternative. The new Sturm count algorithms improve the speed of bisection by up to $ 2 \times $ on our test matrices. Furthermore, unlike the traditional tiny-pivot substitution, proper use of IEEE-754 features provides a careful formulation that imposes no input range restrictions.

entry:
@TechReport{Marques:2005:BIF,
  author =       "Osni A. Marques and E. Jason Riedy and Christof
                 V{\"o}mel",
  title =        "Benefits of {IEEE-754} Features in Modern Symmetric
                 Tridiagonal Eigensolvers",
  type =         "LAPACK Working Note",
  number =       "172",
  institution =  "Computer Science Division, University of California,
                 Berkeley",
  address =      "Berkeley, CA, USA",
  pages =        "22",
  day =          "30",
  month =        sep,
  year =         "2005",
  MRclass =      "15A18, 15A23.",
  bibdate =      "Mon Mar 20 12:18:56 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Also issued as Technical Report UCB//CSD-05-1414.",
  URL =          "http://www.netlib.org/lapack/lawnspdf/lawn172.pdf",
  abstract =     "Bisection is one of the most common methods used to
                 compute the eigenvalues of symmetric tridiagonal
                 matrices. Bisection relies on the Sturm count: for a
                 given shift $ \sigma $, the number of negative pivots
                 in the factorization $ T \sigma I = L D L^T $ equals
                 the number of eigenvalues of $T$ that are smaller than
                 $ \sigma $. In IEEE-754 arithmetic, the value $ \infty
                 $ permits the computation to continue past a zero
                 pivot, producing a correct Sturm count when $T$ is
                 unreduced. Demmel and Li showed in the 90s that using $
                 \infty $ rather than testing for zero pivots within the
                 loop could improve performance significantly on certain
                 architectures.

                 When eigenvalues are to be computed to high relative
                 accuracy, it is often preferable to work with $ L D L^T
                 $ factorizations instead of the original tridiagonal
                 $T$, see for example the MRRR algorithm. In these
                 cases, the Sturm count has to be computed from $ L D
                 L^T $. The differential stationary and progressive qds
                 algorithms are the methods of choice.

                 While it seems trivial to replace $T$ by $ L D L^T $,
                 in reality these algorithms are more complicated: in
                 IEEE-754 arithmetic, a zero pivot produces an overflow,
                 followed by an invalid exception (NaN), that renders
                 the Sturm count incorrect.

                 We present alternative, safe formulations that are
                 guaranteed to produce the correct result.

                 Benchmarking these algorithms on a variety of platforms
                 shows that the original formulation without tests is
                 always faster provided no exception occurs. The
                 transforms see speed-ups of up to $ 2.6 \times $ over
                 the careful formulations.

                 Tests on industrial matrices show that encountering
                 exceptions in practice is rare. This leads to the
                 following design: First, compute the Sturm count by the
                 fast but unsafe algorithm. Then, if an exception
                 occurred, recompute the count by a safe, slower
                 alternative. The new Sturm count algorithms improve the
                 speed of bisection by up to $ 2 \times $ on our test
                 matrices. Furthermore, unlike the traditional
                 tiny-pivot substitution, proper use of IEEE-754
                 features provides a careful formulation that imposes no
                 input range restrictions.",
  acknowledgement = ack-nhfb,
  keywords =     "differential qds algorithms; IEEE-754 arithmetic;
                 IEEE-754 performance; LAPACK; MRRR algorithm; NaN
                 arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Matula:2005:TLS
author: David Matula and Alex Fit-Florea and Mitchell Thornton
title: Table Lookup Structures for Multiplicative Inverses Modulo $ 2^k $
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-160.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: David Matula and Alex Fit-Florea and Mitchell Thornton
rawtitle: Table Lookup Structures for Multiplicative Inverses Modulo $ 2^k $
abstract:
We introduce an inheritance property and related table lookup structures applicable to simplified evaluation of the modular operations ``multiplicative inverse'', ``discrete log'', and ``exponential residue'' in the particular modulus $ 2^k $. Regarding applications, we describe an integer representation system of Benschop for transforming integer multiplications into additions which benefits from our table lookup function evaluation procedures.par We focus herein on the multiplicative inverse modulo $ 2^k $ to exhibit simplifications in hardware implementations realized from the inheritance property. A table lookup structure given by a bit string that can be interpreted with reference to a binary tree is described and analyzed. Using observed symmetries, the lookup structure size is reduced allowing a novel direct lookup process for multiplicative inverses for all 16-bit odd integers to be obtained from a table of size less than two KBytes. The 16-bit multiplicative inverse operation is also applicable for providing a seed inverse for obtaining 32/64-bit multiplicative inverses by one/two iterations of a known quadratic refinement algorithm.

rawabstract:
We introduce an inheritance property and related table lookup structures applicable to simplified evaluation of the modular operations ``multiplicative inverse'', ``discrete log'', and ``exponential residue'' in the particular modulus $ 2^k $. Regarding applications, we describe an integer representation system of Benschop for transforming integer multiplications into additions which benefits from our table lookup function evaluation procedures.\par We focus herein on the multiplicative inverse modulo $ 2^k $ to exhibit simplifications in hardware implementations realized from the inheritance property. A table lookup structure given by a bit string that can be interpreted with reference to a binary tree is described and analyzed. Using observed symmetries, the lookup structure size is reduced allowing a novel direct lookup process for multiplicative inverses for all 16-bit odd integers to be obtained from a table of size less than two KBytes. The 16-bit multiplicative inverse operation is also applicable for providing a seed inverse for obtaining 32/64-bit multiplicative inverses by one/two iterations of a known quadratic refinement algorithm.

entry:
@InProceedings{Matula:2005:TLS,
  author =       "David Matula and Alex Fit-Florea and Mitchell
                 Thornton",
  title =        "Table Lookup Structures for Multiplicative Inverses
                 Modulo $ 2^k $",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-160.pdf",
  abstract =     "We introduce an inheritance property and related table
                 lookup structures applicable to simplified evaluation
                 of the modular operations ``multiplicative inverse'',
                 ``discrete log'', and ``exponential residue'' in the
                 particular modulus $ 2^k $. Regarding applications, we
                 describe an integer representation system of Benschop
                 for transforming integer multiplications into additions
                 which benefits from our table lookup function
                 evaluation procedures.\par We focus herein on the
                 multiplicative inverse modulo $ 2^k $ to exhibit
                 simplifications in hardware implementations realized
                 from the inheritance property. A table lookup structure
                 given by a bit string that can be interpreted with
                 reference to a binary tree is described and analyzed.
                 Using observed symmetries, the lookup structure size is
                 reduced allowing a novel direct lookup process for
                 multiplicative inverses for all 16-bit odd integers to
                 be obtained from a table of size less than two KBytes.
                 The 16-bit multiplicative inverse operation is also
                 applicable for providing a seed inverse for obtaining
                 32/64-bit multiplicative inverses by one/two iterations
                 of a known quadratic refinement algorithm.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: McCann:2005:SDA
author: Mark McCann and Nicholas Pippenger
title: SRT Division Algorithms as Dynamical Systems
journal: j-SIAM-J-COMPUT
volume: 34
number: 6
pages: 1279--1301
month: dec
monthnumber: 12
year: 2005
CODEN: SMJCAT
DOI: https://doi.org/10.1137/S009753970444106X
ISSN: 0097-5397 (print), 1095-7111 (electronic) OR 00975397 (print), 10957111 (electronic)
ISSNL: 0097-5397 OR 00975397
MRclass: 68W40, 37E05
bibdate: Fri Dec 30 06:20:35 MST 2005
bibtimestamp: 2005.12.30 06:20:35 MST
URL: http://epubs.siam.org/sam-bin/dbq/article/44106
fjournal: SIAM Journal on Computing
keywords: SRT division, ergodic, Bernoulli, dynamical systems, entropy
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sicomp
rawauthor: Mark McCann and Nicholas Pippenger
rawtitle: {SRT} Division Algorithms as Dynamical Systems
bibsource:
http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/34/6; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Sweeney--Robertson--Tocher (SRT) division, as it was discovered in the late 1950s, represented an important improvement in the speed of division algorithms for computers at the time. A variant of SRT division is still commonly implemented in computers today. Although some bounds on the performance of the original SRT division method were obtained, a great many questions remained unanswered. In this paper, the original version of SRT division is described as a dynamical system. This enables us to bring modern dynamical systems theory, a relatively new development in mathematics, to bear on an older problem. In doing so, we are able to show that SRT division is ergodic, and is even Bernoulli, for all real divisors and dividends. With the Bernoulli property, we are able to use entropy to prove that the natural extensions of SRT division are isomorphic by way of the Kolmogorov--Ornstein theorem. We demonstrate how our methods and results can be applied to a much larger class of division algorithms.

rawabstract:
Sweeney--Robertson--Tocher (SRT) division, as it was discovered in the late 1950s, represented an important improvement in the speed of division algorithms for computers at the time. A variant of SRT division is still commonly implemented in computers today. Although some bounds on the performance of the original SRT division method were obtained, a great many questions remained unanswered. In this paper, the original version of SRT division is described as a dynamical system. This enables us to bring modern dynamical systems theory, a relatively new development in mathematics, to bear on an older problem. In doing so, we are able to show that SRT division is ergodic, and is even Bernoulli, for all real divisors and dividends. With the Bernoulli property, we are able to use entropy to prove that the natural extensions of SRT division are isomorphic by way of the Kolmogorov--Ornstein theorem. We demonstrate how our methods and results can be applied to a much larger class of division algorithms.

entry:
@Article{McCann:2005:SDA,
  author =       "Mark McCann and Nicholas Pippenger",
  title =        "{SRT} Division Algorithms as Dynamical Systems",
  journal =      j-SIAM-J-COMPUT,
  volume =       "34",
  number =       "6",
  pages =        "1279--1301",
  month =        dec,
  year =         "2005",
  CODEN =        "SMJCAT",
  DOI =          "https://doi.org/10.1137/S009753970444106X",
  ISSN =         "0097-5397 (print), 1095-7111 (electronic)",
  ISSN-L =       "0097-5397",
  MRclass =      "68W40, 37E05",
  bibdate =      "Fri Dec 30 06:20:35 MST 2005",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/34/6;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://epubs.siam.org/sam-bin/dbq/article/44106",
  abstract =     "Sweeney--Robertson--Tocher (SRT) division, as it was
                 discovered in the late 1950s, represented an important
                 improvement in the speed of division algorithms for
                 computers at the time. A variant of SRT division is
                 still commonly implemented in computers today. Although
                 some bounds on the performance of the original SRT
                 division method were obtained, a great many questions
                 remained unanswered. In this paper, the original
                 version of SRT division is described as a dynamical
                 system. This enables us to bring modern dynamical
                 systems theory, a relatively new development in
                 mathematics, to bear on an older problem. In doing so,
                 we are able to show that SRT division is ergodic, and
                 is even Bernoulli, for all real divisors and dividends.
                 With the Bernoulli property, we are able to use entropy
                 to prove that the natural extensions of SRT division
                 are isomorphic by way of the Kolmogorov--Ornstein
                 theorem. We demonstrate how our methods and results can
                 be applied to a much larger class of division
                 algorithms.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Computing",
  journal-URL =  "http://epubs.siam.org/sicomp",
  keywords =     "SRT division, ergodic, Bernoulli, dynamical systems,
                 entropy",
}


bibtype: inproceedings
filename: fparith.bib
label: Mei:2005:LZA
author: Xiao-Lu Mei
title: Leading zero anticipation for latency improvement in floating-point fused multiply-add units
crossref: Tang:2005:AIC
pages: 53--56
year: 2005
DOI: https://doi.org/10.1109/ICASIC.2005.1611267
bibdate: Sun Feb 20 09:52:59 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 09:52:59 ???
acknowledgement: ack-nhfb
rawauthor: Xiao-Lu Mei
rawtitle: Leading zero anticipation for latency improvement in floating-point fused multiply-add units
abstract:
The leading zero anticipation (LZA) is vital in the floating-point fused multiply-add (FMA) units. The general LZA algorithms can only deal with 2 operands. It increases the critical path delay of high performance floating-point FMA units. The paper presents a novel LZA algorithm to deal with 3 operands directly and implemented the 106-bit leading zero anticipator in the high performance floating-point FMA with the general LZA algorithm and the proposed LZA algorithm respectively. Compared with the general leading zero anticipator, the proposed leading zero anticipator can reduce the delay of the critical path by 16.67% and reduce the area by 19.63% approximately.

rawabstract:
The leading zero anticipation (LZA) is vital in the floating-point fused multiply-add (FMA) units. The general LZA algorithms can only deal with 2 operands. It increases the critical path delay of high performance floating-point FMA units. The paper presents a novel LZA algorithm to deal with 3 operands directly and implemented the 106-bit leading zero anticipator in the high performance floating-point FMA with the general LZA algorithm and the proposed LZA algorithm respectively. Compared with the general leading zero anticipator, the proposed leading zero anticipator can reduce the delay of the critical path by 16.67\% and reduce the area by 19.63\% approximately.

entry:
@InProceedings{Mei:2005:LZA,
  author =       "Xiao-Lu Mei",
  title =        "Leading zero anticipation for latency improvement in
                 floating-point fused multiply-add units",
  crossref =     "Tang:2005:AIC",
  pages =        "53--56",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ICASIC.2005.1611267",
  bibdate =      "Sun Feb 20 09:52:59 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The leading zero anticipation (LZA) is vital in the
                 floating-point fused multiply-add (FMA) units. The
                 general LZA algorithms can only deal with 2 operands.
                 It increases the critical path delay of high
                 performance floating-point FMA units. The paper
                 presents a novel LZA algorithm to deal with 3 operands
                 directly and implemented the 106-bit leading zero
                 anticipator in the high performance floating-point FMA
                 with the general LZA algorithm and the proposed LZA
                 algorithm respectively. Compared with the general
                 leading zero anticipator, the proposed leading zero
                 anticipator can reduce the delay of the critical path
                 by 16.67\% and reduce the area by 19.63\%
                 approximately.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Menissier-Morain:2005:APR
author: Valerie Menissier-Morain
title: Arbitrary precision real arithmetic: design and algorithms
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 13--39
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.003
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Thu Oct 17 10:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 10:09:18 ???
fjournal: Journal of Logic and Algebraic Programming
remark: Special issue on Practical development of exact real number computation.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: Val{\'e}rie M{\'e}nissier-Morain
rawtitle: Arbitrary precision real arithmetic: design and algorithms
entry:
@Article{Menissier-Morain:2005:APR,
  author =       "Val{\'e}rie M{\'e}nissier-Morain",
  title =        "Arbitrary precision real arithmetic: design and
                 algorithms",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "13--39",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.003",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Thu Oct 17 10:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  remark =       "Special issue on Practical development of exact real
                 number computation.",
}


bibtype: article
filename: fparith.bib
label: Mitra:2005:BFP
author: Abhijit Mitra and Mrityunjoy Chakraborty and Hideaki Sakai
journal: j-IEEE-TRANS-SIG-PROC
volume: 53
number: 12
pages: 4536--4544
year: 2005
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
MRclass: Database Expansion Item
MRnumber: MR2246666
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: Abhijit Mitra and Mrityunjoy Chakraborty and Hideaki Sakai
title:
A block floating-point treatment to the LMS algorithm: efficient realization and a roundoff error analysis

rawtitle:
A block floating-point treatment to the {LMS} algorithm: efficient realization and a roundoff error analysis

entry:
@Article{Mitra:2005:BFP,
  author =       "Abhijit Mitra and Mrityunjoy Chakraborty and Hideaki
                 Sakai",
  title =        "A block floating-point treatment to the {LMS}
                 algorithm: efficient realization and a roundoff error
                 analysis",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "53",
  number =       "12",
  pages =        "4536--4544",
  year =         "2005",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  MRclass =      "Database Expansion Item",
  MRnumber =     "MR2246666",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
}


bibtype: book
filename: fparith.bib
label: Mitzenmacher:2005:PCI
author: Michael Mitzenmacher and Eli Upfal
title: Probability and Computing: an Introduction to Randomized Algorithms and Probabilistic Analysis
publisher: pub-CAMBRIDGE
address: pub-CAMBRIDGE:adr
pages: xvi + 352
year: 2005
DOI: https://doi.org/10.1017/cbo9780511813603
ISBN: 0-521-83540-2 (print), 0-511-81360-0 (e-book) OR 0521835402 (print), 0511813600 (ebook)
LCCN: QA274 .M574 2005
bibdate: Fri Sep 22 17:57:47 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 17:57:47 ???
subject: Algorithms; Probabilities; Stochastic analysis; Algorithmes; Probabilites; Analyse stochastique
acknowledgement: ack-nhfb
rawauthor: Michael Mitzenmacher and Eli Upfal
rawtitle: Probability and Computing: an Introduction to Randomized Algorithms and Probabilistic Analysis
ISBN13:
978-0-521-83540-4 (print), 978-0-511-81360-3 (e-book) OR 9780521835404 (print), 9780511813603 (ebook)

TOC:
Events and probability Discrete random variables and expectation Moments and deviations Chernoff bounds Balls, bins and random graphs The probabilistic method Markov chains and random walks Continuous distributions and the Poisson process Entropy, randomness, and information The Monte Carlo method Coupling of Markov chains Martingales Pairwise independence and universal hash functions Balanced allocations

rawTOC:
Events and probability \\ Discrete random variables and expectation \\ Moments and deviations \\ Chernoff bounds \\ Balls, bins and random graphs \\ The probabilistic method \\ Markov chains and random walks \\ Continuous distributions and the Poisson process \\ Entropy, randomness, and information \\ The Monte Carlo method \\ Coupling of Markov chains \\ Martingales \\ Pairwise independence and universal hash functions \\ Balanced allocations

entry:
@Book{Mitzenmacher:2005:PCI,
  author =       "Michael Mitzenmacher and Eli Upfal",
  title =        "Probability and Computing: an Introduction to
                 Randomized Algorithms and Probabilistic Analysis",
  publisher =    pub-CAMBRIDGE,
  address =      pub-CAMBRIDGE:adr,
  pages =        "xvi + 352",
  year =         "2005",
  DOI =          "https://doi.org/10.1017/cbo9780511813603",
  ISBN =         "0-521-83540-2 (print), 0-511-81360-0 (e-book)",
  ISBN-13 =      "978-0-521-83540-4 (print), 978-0-511-81360-3
                 (e-book)",
  LCCN =         "QA274 .M574 2005",
  bibdate =      "Fri Sep 22 17:57:47 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  subject =      "Algorithms; Probabilities; Stochastic analysis;
                 Algorithmes; Probabilit{\'e}s; Analyse stochastique",
  tableofcontents = "Events and probability \\
                 Discrete random variables and expectation \\
                 Moments and deviations \\
                 Chernoff bounds \\
                 Balls, bins and random graphs \\
                 The probabilistic method \\
                 Markov chains and random walks \\
                 Continuous distributions and the Poisson process \\
                 Entropy, randomness, and information \\
                 The Monte Carlo method \\
                 Coupling of Markov chains \\
                 Martingales \\
                 Pairwise independence and universal hash functions \\
                 Balanced allocations",
}


bibtype: article
filename: fparith.bib
label: Montgomery:2005:FSS
author: Peter L. Montgomery
title: Five, Six, and Seven-Term Karatsuba-Like Formulae
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 362--369
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.49
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Peter L. Montgomery
rawtitle: Five, Six, and Seven-Term {Karatsuba}-Like Formulae
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0362abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0362.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0362.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388200.pdf?isnumber=30205&prod=JNL&arnumber=1388200&arSt=+362&ared=+369&arAuthor=Montgomery%2C+P.L.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388200&count=13&index=11; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388200

abstract:
The Karatsuba--Ofman algorithm starts with a way to multiply two 2-term (i.e., linear) polynomials using three scalar multiplications. There is also a way to multiply two 3-term (i.e., quadratic) polynomials using six scalar multiplications. These are used within recursive constructions to multiply two higher-degree polynomials in subquadratic time. We present division-free formulae, which multiply two 5-term polynomials with 13 scalar multiplications, two 6-term polynomials with 17 scalar multiplications, and two 7-term polynomials with 22 scalar multiplications. These formulae may be mixed with the 2-term and 3-term formulae within recursive constructions, leading to improved bounds for many other degrees. Using only the 6-term formula leads to better asymptotic performance than standard Karatsuba. The new formulae work in any characteristic, but simplify in characteristic 2. We describe their application to elliptic curve arithmetic over binary fields. We include some timing data.

rawabstract:
The Karatsuba--Ofman algorithm starts with a way to multiply two 2-term (i.e., linear) polynomials using three scalar multiplications. There is also a way to multiply two 3-term (i.e., quadratic) polynomials using six scalar multiplications. These are used within recursive constructions to multiply two higher-degree polynomials in subquadratic time. We present division-free formulae, which multiply two 5-term polynomials with 13 scalar multiplications, two 6-term polynomials with 17 scalar multiplications, and two 7-term polynomials with 22 scalar multiplications. These formulae may be mixed with the 2-term and 3-term formulae within recursive constructions, leading to improved bounds for many other degrees. Using only the 6-term formula leads to better asymptotic performance than standard Karatsuba. The new formulae work in any characteristic, but simplify in characteristic 2. We describe their application to elliptic curve arithmetic over binary fields. We include some timing data.

entry:
@Article{Montgomery:2005:FSS,
  author =       "Peter L. Montgomery",
  title =        "Five, Six, and Seven-Term {Karatsuba}-Like Formulae",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "362--369",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.49",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0362abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0362.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0362.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388200.pdf?isnumber=30205&prod=JNL&arnumber=1388200&arSt=+362&ared=+369&arAuthor=Montgomery%2C+P.L.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388200&count=13&index=11;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388200",
  abstract =     "The Karatsuba--Ofman algorithm starts with a way to
                 multiply two 2-term (i.e., linear) polynomials using
                 three scalar multiplications. There is also a way to
                 multiply two 3-term (i.e., quadratic) polynomials using
                 six scalar multiplications. These are used within
                 recursive constructions to multiply two higher-degree
                 polynomials in subquadratic time. We present
                 division-free formulae, which multiply two 5-term
                 polynomials with 13 scalar multiplications, two 6-term
                 polynomials with 17 scalar multiplications, and two
                 7-term polynomials with 22 scalar multiplications.
                 These formulae may be mixed with the 2-term and 3-term
                 formulae within recursive constructions, leading to
                 improved bounds for many other degrees. Using only the
                 6-term formula leads to better asymptotic performance
                 than standard Karatsuba. The new formulae work in any
                 characteristic, but simplify in characteristic 2. We
                 describe their application to elliptic curve arithmetic
                 over binary fields. We include some timing data.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: inproceedings
filename: fparith.bib
label: Morris:2005:FBF
author: G. Morris and V. Prasanna
title: An FPGA-based floating-point Jacobi iterative solver
crossref: Bein:2005:PIS
pages: 420--427
year: 2005
DOI: https://doi.org/10.1109/ISPAN.2005.18
bibdate: Sat Oct 9 12:54:52 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:54:52 ???
acknowledgement: ack-nhfb
rawauthor: G. Morris and V. Prasanna
rawtitle: An {FPGA}-based floating-point {Jacobi} iterative solver
abstract:
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated circuits --- as hardware `hidden' from the end user. Several high performance computing vendors offer parallel reconfigurable computers employing user-programmable FPGAs. These exciting new architectures allow end-users to, in effect, create reconfigurable coprocessors targeting the computationally intensive parts of each problem. The increased capability of contemporary FPGAs coupled with the embarrassingly parallel nature of the Jacobi iterative method make the Jacobi method an ideal candidate for hardware acceleration. This paper introduces a parameterized design for a deeply pipelined, highly parallelized IEEE 64-bit floating-point version of the Jacobi method. A Jacobi circuit is implemented using a Xilinx Virtex-II Pro as the target FPGA device. Implementation statistics and performance estimates are presented.

rawabstract:
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated circuits --- as hardware `hidden' from the end user. Several high performance computing vendors offer parallel reconfigurable computers employing user-programmable FPGAs. These exciting new architectures allow end-users to, in effect, create reconfigurable coprocessors targeting the computationally intensive parts of each problem. The increased capability of contemporary FPGAs coupled with the embarrassingly parallel nature of the Jacobi iterative method make the Jacobi method an ideal candidate for hardware acceleration. This paper introduces a parameterized design for a deeply pipelined, highly parallelized IEEE 64-bit floating-point version of the Jacobi method. A Jacobi circuit is implemented using a Xilinx Virtex-II Pro as the target FPGA device. Implementation statistics and performance estimates are presented.

entry:
@InProceedings{Morris:2005:FBF,
  author =       "G. Morris and V. Prasanna",
  title =        "An {FPGA}-based floating-point {Jacobi} iterative
                 solver",
  crossref =     "Bein:2005:PIS",
  pages =        "420--427",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ISPAN.2005.18",
  bibdate =      "Sat Oct 9 12:54:52 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Within the parallel computing domain, field
                 programmable gate arrays (FPGA) are no longer
                 restricted to their traditional role as substitutes for
                 application-specific integrated circuits --- as
                 hardware `hidden' from the end user. Several high
                 performance computing vendors offer parallel
                 reconfigurable computers employing user-programmable
                 FPGAs. These exciting new architectures allow end-users
                 to, in effect, create reconfigurable coprocessors
                 targeting the computationally intensive parts of each
                 problem. The increased capability of contemporary FPGAs
                 coupled with the embarrassingly parallel nature of the
                 Jacobi iterative method make the Jacobi method an ideal
                 candidate for hardware acceleration. This paper
                 introduces a parameterized design for a deeply
                 pipelined, highly parallelized IEEE 64-bit
                 floating-point version of the Jacobi method. A Jacobi
                 circuit is implemented using a Xilinx Virtex-II Pro as
                 the target FPGA device. Implementation statistics and
                 performance estimates are presented.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Mueller:2005:VFP
title: The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-151.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawtitle: The Vector Floating-Point Unit in a Synergistic Processor Element of a {CELL} Processor
author:
Silvia M. Mueller and Christian Jacobi and Hwa-Joon Oh and Kevin D. Tran and Cottier Scott and Brad W. Michael and Hiroo Nishikawa and Yonetaro Totsuka and Tatsuya Namatame and Naoka Yano and Takashi Machida and Sang H. Dhong

abstract:
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and integer operations and 2-way SIMD double precision operations. The design required a high-frequency, low latency, power and area efficiency with primary application to the multimedia streaming workloads, such as 3D graphics. The FPU has 3 different latencies, optimizing the performance critical single precision FMA operations, which are executed with a 6-cycle latency at an 11FO4 cycle time. The latency includes the global forwarding of the result. These challenging performance, power, and area goals were achieved through the co-design of architecture and implementation with optimizations at all levels of the design. This paper focuses on the logical and algorithmic aspects of the FPU we developed, to achieve these goals.

rawabstract:
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and integer operations and 2-way SIMD double precision operations. The design required a high-frequency, low latency, power and area efficiency with primary application to the multimedia streaming workloads, such as 3D graphics. The FPU has 3 different latencies, optimizing the performance critical single precision FMA operations, which are executed with a 6-cycle latency at an 11FO4 cycle time. The latency includes the global forwarding of the result. These challenging performance, power, and area goals were achieved through the co-design of architecture and implementation with optimizations at all levels of the design. This paper focuses on the logical and algorithmic aspects of the FPU we developed, to achieve these goals.

rawauthor:
Silvia M. Mueller and Christian Jacobi and Hwa-Joon Oh and Kevin D. Tran and Cottier Scott and Brad W. Michael and Hiroo Nishikawa and Yonetaro Totsuka and Tatsuya Namatame and Naoka Yano and Takashi Machida and Sang H. Dhong

entry:
@InProceedings{Mueller:2005:VFP,
  author =       "Silvia M. Mueller and Christian Jacobi and Hwa-Joon Oh
                 and Kevin D. Tran and Cottier Scott and Brad W. Michael
                 and Hiroo Nishikawa and Yonetaro Totsuka and Tatsuya
                 Namatame and Naoka Yano and Takashi Machida and Sang H.
                 Dhong",
  title =        "The Vector Floating-Point Unit in a Synergistic
                 Processor Element of a {CELL} Processor",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-151.pdf",
  abstract =     "The floating-point unit in the Synergistic Processor
                 Element of the 1st generation multi-core CELL Processor
                 is described. The FPU supports 4-way SIMD single
                 precision and integer operations and 2-way SIMD double
                 precision operations. The design required a
                 high-frequency, low latency, power and area efficiency
                 with primary application to the multimedia streaming
                 workloads, such as 3D graphics. The FPU has 3 different
                 latencies, optimizing the performance critical single
                 precision FMA operations, which are executed with a
                 6-cycle latency at an 11FO4 cycle time. The latency
                 includes the global forwarding of the result. These
                 challenging performance, power, and area goals were
                 achieved through the co-design of architecture and
                 implementation with optimizations at all levels of the
                 design. This paper focuses on the logical and
                 algorithmic aspects of the FPU we developed, to achieve
                 these goals.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "9",
}


bibtype: techreport
filename: fparith.bib
label: Muller:2005:D
author: Jean-Michel Muller
title: On the Definition of tt ulp(x)
type: Rapport de recherche
number: LIP RR2005-09, INRIA RR-5504
institution: Laboratoire de l'Informatique du Parallelisme
address: Lyon, France
pages: 19
month: feb
monthnumber: 2
year: 2005
ISSN: 0249-6399 OR 02496399
bibdate: Wed Jun 24 22:44:21 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.24 22:44:21 ???
URL: ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-5504.pdf
keywords: computer arithmetic; floating-point arithmetic; ULP; unit in the last place
acknowledgement: ack-nhfb
rawauthor: Jean-Michel Muller
rawtitle: On the Definition of {\tt ulp(x)}
abstract:
Function ulp (acronym for emph unit in the last place) is frequently used for expressing errors in floating-point computations. We present several previously suggested definitions of that function, and analyse some of their properties.

rawabstract:
Function ulp (acronym for \emph{unit in the last place}) is frequently used for expressing errors in floating-point computations. We present several previously suggested definitions of that function, and analyse some of their properties.

entry:
@TechReport{Muller:2005:D,
  author =       "Jean-Michel Muller",
  title =        "On the Definition of {\tt ulp(x)}",
  type =         "Rapport de recherche",
  number =       "LIP RR2005-09, INRIA RR-5504",
  institution =  "Laboratoire de l'Informatique du Parall{\'e}lisme",
  address =      "Lyon, France",
  pages =        "19",
  month =        feb,
  year =         "2005",
  ISSN =         "0249-6399",
  bibdate =      "Wed Jun 24 22:44:21 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-5504.pdf",
  abstract =     "Function ulp (acronym for \emph{unit in the last
                 place}) is frequently used for expressing errors in
                 floating-point computations. We present several
                 previously suggested definitions of that function, and
                 analyse some of their properties.",
  acknowledgement = ack-nhfb,
  keywords =     "computer arithmetic; floating-point arithmetic; ULP;
                 unit in the last place",
}


bibtype: inproceedings
filename: fparith.bib
label: Muller:2005:DCS
author: Jean-Michel Muller and Arnaud Tisserand and Benoit de Dinechin and Christophe Monat
title: Division by Constant for the ST100 DSP Microprocessor
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-133.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Jean-Michel Muller and Arnaud Tisserand and Benoit de Dinechin and Christophe Monat
rawtitle: Division by Constant for the {ST100 DSP} Microprocessor
abstract:
Algorithms for Euclidean (i.e., integer) division by a constant operation are presented. They allow fast computation for some values of the divisor (known at compile time) or also when both quotient and modulus are required. These algorithms are based on the multiply-accumulate instruction and the 40-bit arithmetic available in DSPs such as the ST100 DSP from STMicroelectronics. The results are demonstrated in the case of standard speech coding applications.

rawabstract:
Algorithms for Euclidean (i.e., integer) division by a constant operation are presented. They allow fast computation for some values of the divisor (known at compile time) or also when both quotient and modulus are required. These algorithms are based on the multiply-accumulate instruction and the 40-bit arithmetic available in DSPs such as the ST100 DSP from STMicroelectronics. The results are demonstrated in the case of standard speech coding applications.

entry:
@InProceedings{Muller:2005:DCS,
  author =       "Jean-Michel Muller and Arnaud Tisserand and Benoit de
                 Dinechin and Christophe Monat",
  title =        "Division by Constant for the {ST100 DSP}
                 Microprocessor",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-133.pdf",
  abstract =     "Algorithms for Euclidean (i.e., integer) division by a
                 constant operation are presented. They allow fast
                 computation for some values of the divisor (known at
                 compile time) or also when both quotient and modulus
                 are required. These algorithms are based on the
                 multiply-accumulate instruction and the 40-bit
                 arithmetic available in DSPs such as the ST100 DSP from
                 STMicroelectronics. The results are demonstrated in the
                 case of standard speech coding applications.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "7",
}


bibtype: article
filename: fparith.bib
label: Muller:2005:GEI
author: Norbert Muller and Martin Escardo and Paul Zimmermann
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 1--2
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.001
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Thu Oct 17 10:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 10:09:18 ???
fjournal: Journal of Logic and Algebraic Programming
remark: Special issue on Practical development of exact real number computation.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: Norbert M{\"u}ller and Martin Escardo and Paul Zimmermann
title:
Guest editors' introduction: Special issue on practical development of exact real number computation

rawtitle:
Guest editors' introduction: Special issue on practical development of exact real number computation

entry:
@Article{Muller:2005:GEI,
  author =       "Norbert M{\"u}ller and Martin Escardo and Paul
                 Zimmermann",
  title =        "Guest editors' introduction: Special issue on
                 practical development of exact real number
                 computation",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "1--2",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.001",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Thu Oct 17 10:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  remark =       "Special issue on Practical development of exact real
                 number computation.",
}


bibtype: article
filename: fparith.bib
label: Muscedere:2005:ETB
author: Roberto Muscedere and Vassil Dimitrov and Graham A. Jullien and William C. Miller
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 257--271
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.48
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Roberto Muscedere and Vassil Dimitrov and Graham A. Jullien and William C. Miller
title:
Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-Up Tables

URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0257abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0257.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0257.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388191.pdf?isnumber=30205&prod=JNL&arnumber=1388191&arSt=+257&ared=+271&arAuthor=Muscedere%2C+R.%3B+Dimitrov%2C+V.%3B+Jullien%2C+G.A.%3B+Miller%2C+W.C.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388191&count=13&index=2; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388191

rawtitle:
Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-Up Tables

entry:
@Article{Muscedere:2005:ETB,
  author =       "Roberto Muscedere and Vassil Dimitrov and Graham A.
                 Jullien and William C. Miller",
  title =        "Efficient Techniques for Binary-to-Multidigit
                 Multidimensional Logarithmic Number System Conversion
                 Using Range-Addressable Look-Up Tables",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "257--271",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.48",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0257abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0257.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0257.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388191.pdf?isnumber=30205&prod=JNL&arnumber=1388191&arSt=+257&ared=+271&arAuthor=Muscedere%2C+R.%3B+Dimitrov%2C+V.%3B+Jullien%2C+G.A.%3B+Miller%2C+W.C.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388191&count=13&index=2;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388191",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: article
filename: fparith.bib
label: Muscedere:2005:LPT
author: Roberto Muscedere and Vassil Dimitrov and Graham Jullien and William Miller
journal: j-EURASIP-J-ADV-SIGNAL-PROCESS
volume: 1
pages: 3015--3025
year: 2005
DOI: https://doi.org/10.1155/ASP.2005.3015
ISSN: 1110-8657 (print), 1687-0433 (electronic) OR 11108657 (print), 16870433 (electronic)
ISSNL: 1110-8657 OR 11108657
bibdate: Fri Aug 8 08:37:33 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.08 08:37:33 ???
fjournal: EURASIP Journal on Advances in Signal Processing
acknowledgement: ack-nhfb
ajournal: EURASIP J. Appl. Signal Process.
articleno: 326504
journalURL: https://asp-eurasipjournals.springeropen.com/
rawauthor: Roberto Muscedere and Vassil Dimitrov and Graham Jullien and William Miller
title:
A low-power two-digit multi-dimensional logarithmic number system filterbank architecture for a digital hearing aid

abstract:
This paper addresses the implementation of a filterbank for digital hearing aids using a multi-dimensional logarithmic number system (MDLNS). The MDLNS, which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and the ability to use multiple MDLNS components or digits. The logarithmic properties of the MDLNS also allow for reduced complexity multiplication and large dynamic range, and a multiple-digit MDLNS provides a considerable reduction in hardware complexity compared to a conventional LNS approach. We discuss an improved design for a two-digit 2D MDLNS filterbank implementation which reduces power and area by over two times compared to the original design.

rawabstract:
This paper addresses the implementation of a filterbank for digital hearing aids using a multi-dimensional logarithmic number system (MDLNS). The MDLNS, which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and the ability to use multiple MDLNS components or digits. The logarithmic properties of the MDLNS also allow for reduced complexity multiplication and large dynamic range, and a multiple-digit MDLNS provides a considerable reduction in hardware complexity compared to a conventional LNS approach. We discuss an improved design for a two-digit 2D MDLNS filterbank implementation which reduces power and area by over two times compared to the original design.

rawtitle:
A low-power two-digit multi-dimensional logarithmic number system filterbank architecture for a digital hearing aid

entry:
@Article{Muscedere:2005:LPT,
  author =       "Roberto Muscedere and Vassil Dimitrov and Graham
                 Jullien and William Miller",
  title =        "A low-power two-digit multi-dimensional logarithmic
                 number system filterbank architecture for a digital
                 hearing aid",
  journal =      j-EURASIP-J-ADV-SIGNAL-PROCESS,
  volume =       "1",
  pages =        "3015--3025",
  year =         "2005",
  DOI =          "https://doi.org/10.1155/ASP.2005.3015",
  ISSN =         "1110-8657 (print), 1687-0433 (electronic)",
  ISSN-L =       "1110-8657",
  bibdate =      "Fri Aug 8 08:37:33 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper addresses the implementation of a
                 filterbank for digital hearing aids using a
                 multi-dimensional logarithmic number system (MDLNS).
                 The MDLNS, which has similar properties to the
                 classical logarithmic number system (LNS), provides
                 more degrees of freedom than the LNS by virtue of
                 having two, or more, orthogonal bases and the ability
                 to use multiple MDLNS components or digits. The
                 logarithmic properties of the MDLNS also allow for
                 reduced complexity multiplication and large dynamic
                 range, and a multiple-digit MDLNS provides a
                 considerable reduction in hardware complexity compared
                 to a conventional LNS approach. We discuss an improved
                 design for a two-digit 2D MDLNS filterbank
                 implementation which reduces power and area by over two
                 times compared to the original design.",
  acknowledgement = ack-nhfb,
  ajournal =     "EURASIP J. Appl. Signal Process.",
  articleno =    "326504",
  fjournal =     "EURASIP Journal on Advances in Signal Processing",
  journal-URL =  "https://asp-eurasipjournals.springeropen.com/",
}


bibtype: article
filename: fparith.bib
label: Newman:2005:PLP
author: M. E. J. Newman
title: Power laws, Pareto distributions and Zipf's law
journal: j-CONTEMP-PHYS
volume: 46
number: 5
pages: 323--351
month: sep
monthnumber: 9
year: 2005
CODEN: CTPHAF
DOI: https://doi.org/10.1080/00107510500052444
ISSN: 0010-7514 (print), 1366-5812 (electronic) OR 00107514 (print), 13665812 (electronic)
ISSNL: 0010-7514 OR 00107514
bibdate: Thu Feb 18 20:07:22 MST 2016
bibtimestamp: 2016.02.18 20:07:22 MST
fjournal: Contemporary Physics
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/tcph20
rawauthor: M. E. J. Newman
rawtitle: Power laws, {Pareto} distributions and {Zipf}'s law
bibsource:
https://www.math.utah.edu/pub/tex/bib/benfords-law.bib; https://www.math.utah.edu/pub/tex/bib/contempphys.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
When the probability of measuring a particular value of some quantity varies inversely as a power of that value, the quantity is said to follow a power law, also known variously as Zipf's law or the Pareto distribution. Power laws appear widely in physics, biology, earth and planetary sciences, economics and finance, computer science, demography and the social sciences. For instance, the distributions of the sizes of cities, earthquakes, forest fires, solar flares, moon craters and people's personal fortunes all appear to follow power laws. The origin of power-law behaviour has been a topic of debate in the scientific community for more than a century. Here we review some of the empirical evidence for the existence of power-law forms and the theories proposed to explain them.

keywords:
Benford's Law; critical phenomena; Legendre beta function; Pareto distribution; percolation; phase transitions; power-law distributions; random walks; Riemann zeta function; scale-free distributions; Yule process; Zipf's Law

remark:
This article is an excellent survey of continuous and discrete distributions that follow a power law, and some that do not. It is well worth reading.

subject:
astrophysics; atomic and nuclear physics; chemical physics; computational physics; condensed matter physics; environmental physics; experimental physics; general physics; particle and high energy physics; plasma physics; space science; theoretical physics

rawabstract:
When the probability of measuring a particular value of some quantity varies inversely as a power of that value, the quantity is said to follow a power law, also known variously as Zipf's law or the Pareto distribution. Power laws appear widely in physics, biology, earth and planetary sciences, economics and finance, computer science, demography and the social sciences. For instance, the distributions of the sizes of cities, earthquakes, forest fires, solar flares, moon craters and people's personal fortunes all appear to follow power laws. The origin of power-law behaviour has been a topic of debate in the scientific community for more than a century. Here we review some of the empirical evidence for the existence of power-law forms and the theories proposed to explain them.

entry:
@Article{Newman:2005:PLP,
  author =       "M. E. J. Newman",
  title =        "Power laws, {Pareto} distributions and {Zipf}'s law",
  journal =      j-CONTEMP-PHYS,
  volume =       "46",
  number =       "5",
  pages =        "323--351",
  month =        sep,
  year =         "2005",
  CODEN =        "CTPHAF",
  DOI =          "https://doi.org/10.1080/00107510500052444",
  ISSN =         "0010-7514 (print), 1366-5812 (electronic)",
  ISSN-L =       "0010-7514",
  bibdate =      "Thu Feb 18 20:07:22 MST 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/benfords-law.bib;
                 https://www.math.utah.edu/pub/tex/bib/contempphys.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "When the probability of measuring a particular value
                 of some quantity varies inversely as a power of that
                 value, the quantity is said to follow a power law, also
                 known variously as Zipf's law or the Pareto
                 distribution. Power laws appear widely in physics,
                 biology, earth and planetary sciences, economics and
                 finance, computer science, demography and the social
                 sciences. For instance, the distributions of the sizes
                 of cities, earthquakes, forest fires, solar flares,
                 moon craters and people's personal fortunes all appear
                 to follow power laws. The origin of power-law behaviour
                 has been a topic of debate in the scientific community
                 for more than a century. Here we review some of the
                 empirical evidence for the existence of power-law forms
                 and the theories proposed to explain them.",
  acknowledgement = ack-nhfb,
  fjournal =     "Contemporary Physics",
  journal-URL =  "http://www.tandfonline.com/loi/tcph20",
  keywords =     "Benford's Law; critical phenomena; Legendre beta
                 function; Pareto distribution; percolation; phase
                 transitions; power-law distributions; random walks;
                 Riemann zeta function; scale-free distributions; Yule
                 process; Zipf's Law",
  remark =       "This article is an excellent survey of continuous and
                 discrete distributions that follow a power law, and
                 some that do not. It is well worth reading.",
  subject =      "astrophysics; atomic and nuclear physics; chemical
                 physics; computational physics; condensed matter
                 physics; environmental physics; experimental physics;
                 general physics; particle and high energy physics;
                 plasma physics; space science; theoretical physics",
}


bibtype: article
filename: fparith.bib
label: Nguyen:2005:FPL
author: P. Nguyen and D. Stehle
title: Floating-Point LLL Revisited
journal: j-LECT-NOTES-COMP-SCI
volume: 3494
pages: 215--233
year: 2005
CODEN: LNCSD9
DOI: https://doi.org/10.1007/11426639_13
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Fri Jun 24 14:51:11 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 14:51:11 ???
fjournal: Lecture Notes in Computer Science
keywords: $L^3$; Lattice Reduction; LLL; Public-Key Cryptanalysis
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: P. Nguyen and D. Stehle
rawtitle: Floating-Point {LLL} Revisited
abstract:
The Lenstra-Lenstra-Lovasz lattice basis reduction algorithm (LLL or $ L^3 $) is a very popular tool in public-key cryptanalysis and in many other fields. Given an integer $d$-dimensional lattice basis with vectors of norm less than $B$ in an $n$-dimensional space, $ L^3 $ outputs a so-called $ L^3 $-reduced basis in polynomial time $ O(d^5 n log ^3 B) $, using arithmetic operations on integers of bit-length $ O(d l o g B) $. This worst-case complexity is problematic for lattices arising in cryptanalysis where $d$ or/and $ log B $ are often large. As a result, the original $ L^3 $ is almost never used in practice. Instead, one applies floating-point variants of $ L^3 $, where the long-integer arithmetic required by Gram--Schmidt orthogonalisation (central in $ L^3 $) is replaced by floating-point arithmetic. Unfortunately, this is known to be unstable in the worst-case: the usual floating-point $ L^3 $ is not even guaranteed to terminate, and the output basis may not be $ L^3 $-reduced at all. In this article, we introduce the $ L^2 $ algorithm, a new and natural floating-point variant of $ L^3 $ which provably outputs $ L^3 $-reduced bases in polynomial time $ O(d^4 n (d + log B) log B) $. This is the first $ L^3 $ algorithm whose running time (without fast integer arithmetic) provably grows only quadratically with respect to $ log B $, like the well-known Euclidean and Gaussian algorithms, which it generalizes.

rawabstract:
The Lenstra-Lenstra-Lov{\'a}sz lattice basis reduction algorithm (LLL or $ L^3 $) is a very popular tool in public-key cryptanalysis and in many other fields. Given an integer $d$-dimensional lattice basis with vectors of norm less than $B$ in an $n$-dimensional space, $ L^3 $ outputs a so-called $ L^3 $-reduced basis in polynomial time $ O(d^5 n \log^3 B) $, using arithmetic operations on integers of bit-length $ O(d l o g B) $. This worst-case complexity is problematic for lattices arising in cryptanalysis where $d$ or/and $ \log B $ are often large. As a result, the original $ L^3 $ is almost never used in practice. Instead, one applies floating-point variants of $ L^3 $, where the long-integer arithmetic required by Gram--Schmidt orthogonalisation (central in $ L^3 $) is replaced by floating-point arithmetic. Unfortunately, this is known to be unstable in the worst-case: the usual floating-point $ L^3 $ is not even guaranteed to terminate, and the output basis may not be $ L^3 $-reduced at all. In this article, we introduce the $ L^2 $ algorithm, a new and natural floating-point variant of $ L^3 $ which provably outputs $ L^3 $-reduced bases in polynomial time $ O(d^4 n (d + \log B) \log B) $. This is the first $ L^3 $ algorithm whose running time (without fast integer arithmetic) provably grows only quadratically with respect to $ \log B $, like the well-known Euclidean and Gaussian algorithms, which it generalizes.

entry:
@Article{Nguyen:2005:FPL,
  author =       "P. Nguyen and D. Stehle",
  title =        "Floating-Point {LLL} Revisited",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "3494",
  pages =        "215--233",
  year =         "2005",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/11426639_13",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Fri Jun 24 14:51:11 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Lenstra-Lenstra-Lov{\'a}sz lattice basis reduction
                 algorithm (LLL or $ L^3 $) is a very popular tool in
                 public-key cryptanalysis and in many other fields.
                 Given an integer $d$-dimensional lattice basis with
                 vectors of norm less than $B$ in an $n$-dimensional
                 space, $ L^3 $ outputs a so-called $ L^3 $-reduced
                 basis in polynomial time $ O(d^5 n \log^3 B) $, using
                 arithmetic operations on integers of bit-length $ O(d l
                 o g B) $. This worst-case complexity is problematic for
                 lattices arising in cryptanalysis where $d$ or/and $
                 \log B $ are often large. As a result, the original $
                 L^3 $ is almost never used in practice. Instead, one
                 applies floating-point variants of $ L^3 $, where the
                 long-integer arithmetic required by Gram--Schmidt
                 orthogonalisation (central in $ L^3 $) is replaced by
                 floating-point arithmetic. Unfortunately, this is known
                 to be unstable in the worst-case: the usual
                 floating-point $ L^3 $ is not even guaranteed to
                 terminate, and the output basis may not be $ L^3
                 $-reduced at all. In this article, we introduce the $
                 L^2 $ algorithm, a new and natural floating-point
                 variant of $ L^3 $ which provably outputs $ L^3
                 $-reduced bases in polynomial time $ O(d^4 n (d + \log
                 B) \log B) $. This is the first $ L^3 $ algorithm whose
                 running time (without fast integer arithmetic) provably
                 grows only quadratically with respect to $ \log B $,
                 like the well-known Euclidean and Gaussian algorithms,
                 which it generalizes.",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "$L^3$; Lattice Reduction; LLL; Public-Key
                 Cryptanalysis",
}


bibtype: inproceedings
filename: fparith.bib
label: Oberman:2005:HPA
author: Stuart Oberman and Michael Siu
title: A High-Performance Area-Efficient Multifunction Interpolator
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-164.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Stuart Oberman and Michael Siu
rawtitle: A High-Performance Area-Efficient Multifunction Interpolator
abstract:
This paper presents the algorithms and implementation of a high-performance functional unit used for multiple interpolation applications. Graphics processing units (GPUs) frequently perform two classes of floating point interpolation within programmable shaders: per-pixel attribute interpolation and transcendental function approximation. We present a design that efficiently performs both classes of interpolation on a shared functional unit. Enhanced minimax approximations with quadratic interpolation minimize lookup-table sizes and datapath widths for fully-pipelined function approximation. Rectangular multipliers support both sign-magnitude and two's complement inputs of variable widths. Superpipelining is used throughout the design to increase operating frequency and interpolation throughput while maximizing area efficiency.

rawabstract:
This paper presents the algorithms and implementation of a high-performance functional unit used for multiple interpolation applications. Graphics processing units (GPUs) frequently perform two classes of floating point interpolation within programmable shaders: per-pixel attribute interpolation and transcendental function approximation. We present a design that efficiently performs both classes of interpolation on a shared functional unit. Enhanced minimax approximations with quadratic interpolation minimize lookup-table sizes and datapath widths for fully-pipelined function approximation. Rectangular multipliers support both sign-magnitude and two's complement inputs of variable widths. Superpipelining is used throughout the design to increase operating frequency and interpolation throughput while maximizing area efficiency.

entry:
@InProceedings{Oberman:2005:HPA,
  author =       "Stuart Oberman and Michael Siu",
  title =        "A High-Performance Area-Efficient Multifunction
                 Interpolator",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-164.pdf",
  abstract =     "This paper presents the algorithms and implementation
                 of a high-performance functional unit used for multiple
                 interpolation applications. Graphics processing units
                 (GPUs) frequently perform two classes of floating point
                 interpolation within programmable shaders: per-pixel
                 attribute interpolation and transcendental function
                 approximation. We present a design that efficiently
                 performs both classes of interpolation on a shared
                 functional unit. Enhanced minimax approximations with
                 quadratic interpolation minimize lookup-table sizes and
                 datapath widths for fully-pipelined function
                 approximation. Rectangular multipliers support both
                 sign-magnitude and two's complement inputs of variable
                 widths. Superpipelining is used throughout the design
                 to increase operating frequency and interpolation
                 throughput while maximizing area efficiency.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Ogita:2005:ASD
author: Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
title: Accurate Sum and Dot Product
journal: j-SIAM-J-SCI-COMP
volume: 26
number: 6
pages: 1955--1988
month: nov
monthnumber: 11
year: 2005
CODEN: SJOCE3
DOI: https://doi.org/10.1137/030601818
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
MRclass: 5-04, 65G99, 65-04
bibdate: Mon Nov 21 14:52:48 MST 2005
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/26/6; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.21 14:52:48 MST
URL: http://epubs.siam.org/sam-bin/dbq/article/60181
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
rawtitle: Accurate Sum and Dot Product
abstract:
Algorithms for summation and dot product of floating-point numbers are presented which are fast in terms of measured computing time. We show that the computed results are as accurate as if computed in twice or K-fold working precision, $ K ge 3 $. For twice the working precision our algorithms for summation and dot product are some 40% faster than the corresponding XBLAS routines while sharing similar error estimates. Our algorithms are widely applicable because they require only addition, subtraction, and multiplication of floating-point numbers in the same working precision as the given data. Higher precision is unnecessary, algorithms are straight loops without branch, and no access to mantissa or exponent is necessary.

keywords:
accurate dot product; accurate floating-point summation; fast algorithms; high precision; verified error bounds

rawabstract:
Algorithms for summation and dot product of floating-point numbers are presented which are fast in terms of measured computing time. We show that the computed results are as accurate as if computed in twice or K-fold working precision, $ K \ge 3 $. For twice the working precision our algorithms for summation and dot product are some 40\% faster than the corresponding XBLAS routines while sharing similar error estimates. Our algorithms are widely applicable because they require only addition, subtraction, and multiplication of floating-point numbers in the same working precision as the given data. Higher precision is unnecessary, algorithms are straight loops without branch, and no access to mantissa or exponent is necessary.

entry:
@Article{Ogita:2005:ASD,
  author =       "Takeshi Ogita and Siegfried M. Rump and Shin'ichi
                 Oishi",
  title =        "Accurate Sum and Dot Product",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "26",
  number =       "6",
  pages =        "1955--1988",
  month =        nov,
  year =         "2005",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/030601818",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  MRclass =      "5-04, 65G99, 65-04",
  bibdate =      "Mon Nov 21 14:52:48 MST 2005",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/26/6;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://epubs.siam.org/sam-bin/dbq/article/60181",
  abstract =     "Algorithms for summation and dot product of
                 floating-point numbers are presented which are fast in
                 terms of measured computing time. We show that the
                 computed results are as accurate as if computed in
                 twice or K-fold working precision, $ K \ge 3 $. For
                 twice the working precision our algorithms for
                 summation and dot product are some 40\% faster than the
                 corresponding XBLAS routines while sharing similar
                 error estimates. Our algorithms are widely applicable
                 because they require only addition, subtraction, and
                 multiplication of floating-point numbers in the same
                 working precision as the given data. Higher precision
                 is unnecessary, algorithms are straight loops without
                 branch, and no access to mantissa or exponent is
                 necessary.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate dot product; accurate floating-point
                 summation; fast algorithms; high precision; verified
                 error bounds",
}


bibtype: inproceedings
filename: fparith.bib
label: Oh:2005:FPS
booktitle: 2005 Symposium on VLSI Circuits, June 16--18th, 2005, Rhiga Royal Hotel Kyoto, Kyoto, Japan
publisher: pub-IEEE
address: pub-IEEE:adr
pages: ??--??
year: 2005
bibdate: Fri Jun 24 14:35:04 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 14:35:04 ???
note: Paper 2.4
URL: http://www.vlsisymposium.org/circuits/technical.html
acknowledgement: ack-nhfb
rawbooktitle: {2005 Symposium on VLSI Circuits, June 16--18th, 2005, Rhiga Royal Hotel Kyoto, Kyoto, Japan}
rawnote: Paper 2.4
author:
H.-J. Oh and S. M. Mueller and C. Jacobi and K. D. Tran and S. R. Cottier and B. W. Michael and H. Nishikawa and Y. Totsuka and T. Namatame and N. Yano and T. Machida and S. H. Dhong

title:
A Fully-Pipelined Single-Precision Floating Point Unit in the Synergistic Processor Element of a CELL Processor

abstract:
The floating point unit in the synergistic processor element of a CELL processor is a fully-pipelined 4-way SIMD unit designed to accelerate media and data streaming. It supports 32-bit single-precision floating point and 16-bit integer operands with two different latencies, optimizing the performance of critical single-precision multiply-add operations. It employs fine-grained clock gating for power saving. Architecture, logic, circuits and integration are co-designed to meet the performance, power, and area goals.

rawabstract:
The floating point unit in the synergistic processor element of a CELL processor is a fully-pipelined 4-way SIMD unit designed to accelerate media and data streaming. It supports 32-bit single-precision floating point and 16-bit integer operands with two different latencies, optimizing the performance of critical single-precision multiply-add operations. It employs fine-grained clock gating for power saving. Architecture, logic, circuits and integration are co-designed to meet the performance, power, and area goals.

rawauthor:
H.-J. Oh and S. M. Mueller and C. Jacobi and K. D. Tran and S. R. Cottier and B. W. Michael and H. Nishikawa and Y. Totsuka and T. Namatame and N. Yano and T. Machida and S. H. Dhong

rawtitle:
A Fully-Pipelined Single-Precision Floating Point Unit in the Synergistic Processor Element of a {CELL} Processor

entry:
@InProceedings{Oh:2005:FPS,
  author =       "H.-J. Oh and S. M. Mueller and C. Jacobi and K. D.
                 Tran and S. R. Cottier and B. W. Michael and H.
                 Nishikawa and Y. Totsuka and T. Namatame and N. Yano
                 and T. Machida and S. H. Dhong",
  booktitle =    "{2005 Symposium on VLSI Circuits, June 16--18th, 2005,
                 Rhiga Royal Hotel Kyoto, Kyoto, Japan}",
  title =        "A Fully-Pipelined Single-Precision Floating Point Unit
                 in the Synergistic Processor Element of a {CELL}
                 Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "??--??",
  year =         "2005",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jun 24 14:35:04 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Paper 2.4",
  URL =          "http://www.vlsisymposium.org/circuits/technical.html",
  abstract =     "The floating point unit in the synergistic processor
                 element of a CELL processor is a fully-pipelined 4-way
                 SIMD unit designed to accelerate media and data
                 streaming. It supports 32-bit single-precision floating
                 point and 16-bit integer operands with two different
                 latencies, optimizing the performance of critical
                 single-precision multiply-add operations. It employs
                 fine-grained clock gating for power saving.
                 Architecture, logic, circuits and integration are
                 co-designed to meet the performance, power, and area
                 goals.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Pareto:2005:GAL
author: Lena Pareto
title: Graphical arithmetic for learners with dyscalculia
crossref: ACM:2005:ASI
pages: 214--215
year: 2005
DOI: https://doi.org/10.1145/1090785.1090836
bibdate: Thu Aug 07 18:43:59 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 18:43:59 ???
keywords: decimal arithmetic
acknowledgement: ack-nhfb
rawauthor: Lena Pareto
rawtitle: Graphical arithmetic for learners with dyscalculia
abstract:
We propose a model for arithmetic, based on graphical representations, to complement the symbolic language of mathematics. The focus is conceptual understanding of arithmetic. We argue that the graphical model supports understanding concepts known to be difficult for learners with dyscalculia, such as number-sense and decimal system. The proposed graphical representation share properties of the decimal system, but is closer to the semantic representation of numbers vital to the number-sense. The model is evaluated with school-children, but needs to be further tested by learners with dyscalculia.

rawabstract:
We propose a model for arithmetic, based on graphical representations, to complement the symbolic language of mathematics. The focus is conceptual understanding of arithmetic. We argue that the graphical model supports understanding concepts known to be difficult for learners with dyscalculia, such as number-sense and decimal system. The proposed graphical representation share properties of the decimal system, but is closer to the semantic representation of numbers vital to the number-sense. The model is evaluated with school-children, but needs to be further tested by learners with dyscalculia.

entry:
@InProceedings{Pareto:2005:GAL,
  author =       "Lena Pareto",
  title =        "Graphical arithmetic for learners with dyscalculia",
  crossref =     "ACM:2005:ASI",
  pages =        "214--215",
  year =         "2005",
  DOI =          "https://doi.org/10.1145/1090785.1090836",
  bibdate =      "Thu Aug 07 18:43:59 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We propose a model for arithmetic, based on graphical
                 representations, to complement the symbolic language of
                 mathematics. The focus is conceptual understanding of
                 arithmetic. We argue that the graphical model supports
                 understanding concepts known to be difficult for
                 learners with dyscalculia, such as number-sense and
                 decimal system. The proposed graphical representation
                 share properties of the decimal system, but is closer
                 to the semantic representation of numbers vital to the
                 number-sense. The model is evaluated with
                 school-children, but needs to be further tested by
                 learners with dyscalculia.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Phatak:2005:FMR
author: Dhananjay Phatak and Tom Goff
title: Fast Modular Reduction for Large Wordlengths via One Linear and One Cyclic Convolution
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-156.pdf
acknowledgement: ack-nhfb
rawauthor: Dhananjay Phatak and Tom Goff
rawtitle: Fast Modular Reduction for Large Wordlengths via One Linear and One Cyclic Convolution
abstract:
Modular reduction is a fundamental operation in cryptographic systems. Most well known modular reduction methods including Barrett's and Montgomery's algorithms leverage some-pre computations to avoid divisions so that the main complexity of these methods lies in a sequence of two long multiplications. For large wordlengths a multiplication which is tantamount to a linear convolution is performed via the Fast Fourier Transform (FFT) or other transform-based techniques as in the Schonhage-Strassen multiplication algorithm.par We show a fundamental property (the separation principle): in a modular reduction based on long multiplications, the linear convolution required by one of the two long multiplications can be replaced by a cyclic convolution, and the halves can be separated using other information available due to the intrinsic redundancy of the operations. This reduces the number of operations by about 25%. We demonstrate that both Barrett's and Montgomery's methods can be sped up by using the aforementioned fundamental principle. It is shown that a direct application of this algorithm to modular exponentiation (either using Barrett's or Montgomery's methods) can be expected to yield about 17% speedup.

keywords:
ARITH-17; cryptography; cyclic convolution; elliptic-curve; fast modular reduction; FFT multiply; large wordlength; linear convolution; number theoretic transforms; principle of separation

rawabstract:
Modular reduction is a fundamental operation in cryptographic systems. Most well known modular reduction methods including Barrett's and Montgomery's algorithms leverage some-pre computations to avoid divisions so that the main complexity of these methods lies in a sequence of two long multiplications. For large wordlengths a multiplication which is tantamount to a linear convolution is performed via the Fast Fourier Transform (FFT) or other transform-based techniques as in the Schonhage-Strassen multiplication algorithm.\par We show a fundamental property (the separation principle): in a modular reduction based on long multiplications, the linear convolution required by one of the two long multiplications can be replaced by a cyclic convolution, and the halves can be separated using other information available due to the intrinsic redundancy of the operations. This reduces the number of operations by about 25\%. We demonstrate that both Barrett's and Montgomery's methods can be sped up by using the aforementioned fundamental principle. It is shown that a direct application of this algorithm to modular exponentiation (either using Barrett's or Montgomery's methods) can be expected to yield about 17\% speedup.

entry:
@InProceedings{Phatak:2005:FMR,
  author =       "Dhananjay Phatak and Tom Goff",
  title =        "Fast Modular Reduction for Large Wordlengths via One
                 Linear and One Cyclic Convolution",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-156.pdf",
  abstract =     "Modular reduction is a fundamental operation in
                 cryptographic systems. Most well known modular
                 reduction methods including Barrett's and Montgomery's
                 algorithms leverage some-pre computations to avoid
                 divisions so that the main complexity of these methods
                 lies in a sequence of two long multiplications. For
                 large wordlengths a multiplication which is tantamount
                 to a linear convolution is performed via the Fast
                 Fourier Transform (FFT) or other transform-based
                 techniques as in the Schonhage-Strassen multiplication
                 algorithm.\par

                 We show a fundamental property (the separation
                 principle): in a modular reduction based on long
                 multiplications, the linear convolution required by one
                 of the two long multiplications can be replaced by a
                 cyclic convolution, and the halves can be separated
                 using other information available due to the intrinsic
                 redundancy of the operations. This reduces the number
                 of operations by about 25\%. We demonstrate that both
                 Barrett's and Montgomery's methods can be sped up by
                 using the aforementioned fundamental principle. It is
                 shown that a direct application of this algorithm to
                 modular exponentiation (either using Barrett's or
                 Montgomery's methods) can be expected to yield about
                 17\% speedup.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; cryptography; cyclic convolution;
                 elliptic-curve; fast modular reduction; FFT multiply;
                 large wordlength; linear convolution; number theoretic
                 transforms; principle of separation",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Pineiro:2005:HSF
author: Jose-Alejandro Pineiro and Stuart F. Oberman and Jean-Michel Muller and Javier D. Bruguera
title: High-Speed Function Approximation Using a Minimax Quadratic Interpolator
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 304--318
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.52
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Jose-Alejandro Pi{\~n}eiro and Stuart F. Oberman and Jean-Michel Muller and Javier D. Bruguera
rawtitle: High-Speed Function Approximation Using a Minimax Quadratic Interpolator
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0304abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0304.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0304.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388195.pdf?isnumber=30205&prod=JNL&arnumber=1388195&arSt=+304&ared=+318&arAuthor=Pineiro%2C+J.-A.%3B+Oberman%2C+S.F.%3B+Muller%2C+J.-M.%3B+Bruguera%2C+J.D.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388195&count=13&index=6; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388195

abstract:
A table-based method for high-speed function approximation in single-precision floating-point format is presented in this paper. Our focus is the approximation of reciprocal, square root, square root reciprocal, exponentials, logarithms, trigonometric functions, powering (with a fixed exponent $p$) , or special functions. The algorithm presented here combines table look-up, an enhanced minimax quadratic approximation, and an efficient evaluation of the second-degree polynomial (using a specialized squaring unit, redundant arithmetic, and multioperand addition). The execution times and area costs of an architecture implementing our method are estimated, showing the achievement of the fast execution times of linear approximation methods and the reduced area requirements of other second-degree interpolation algorithms. Moreover, the use of an enhanced minimax approximation which, through an iterative process, takes into account the effect of rounding the polynomial coefficients to a finite size allows for a further reduction in the size of the look-up tables to be used, making our method very suitable for the implementation of an elementary function generator in state-of-the-art DSPs or graphics processing units (GPUs).

rawabstract:
A table-based method for high-speed function approximation in single-precision floating-point format is presented in this paper. Our focus is the approximation of reciprocal, square root, square root reciprocal, exponentials, logarithms, trigonometric functions, powering (with a fixed exponent $p$) , or special functions. The algorithm presented here combines table look-up, an enhanced minimax quadratic approximation, and an efficient evaluation of the second-degree polynomial (using a specialized squaring unit, redundant arithmetic, and multioperand addition). The execution times and area costs of an architecture implementing our method are estimated, showing the achievement of the fast execution times of linear approximation methods and the reduced area requirements of other second-degree interpolation algorithms. Moreover, the use of an enhanced minimax approximation which, through an iterative process, takes into account the effect of rounding the polynomial coefficients to a finite size allows for a further reduction in the size of the look-up tables to be used, making our method very suitable for the implementation of an elementary function generator in state-of-the-art DSPs or graphics processing units (GPUs).

entry:
@Article{Pineiro:2005:HSF,
  author =       "Jose-Alejandro Pi{\~n}eiro and Stuart F. Oberman and
                 Jean-Michel Muller and Javier D. Bruguera",
  title =        "High-Speed Function Approximation Using a Minimax
                 Quadratic Interpolator",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "304--318",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.52",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0304abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0304.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0304.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388195.pdf?isnumber=30205&prod=JNL&arnumber=1388195&arSt=+304&ared=+318&arAuthor=Pineiro%2C+J.-A.%3B+Oberman%2C+S.F.%3B+Muller%2C+J.-M.%3B+Bruguera%2C+J.D.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388195&count=13&index=6;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388195",
  abstract =     "A table-based method for high-speed function
                 approximation in single-precision floating-point format
                 is presented in this paper. Our focus is the
                 approximation of reciprocal, square root, square root
                 reciprocal, exponentials, logarithms, trigonometric
                 functions, powering (with a fixed exponent $p$) , or
                 special functions. The algorithm presented here
                 combines table look-up, an enhanced minimax quadratic
                 approximation, and an efficient evaluation of the
                 second-degree polynomial (using a specialized squaring
                 unit, redundant arithmetic, and multioperand addition).
                 The execution times and area costs of an architecture
                 implementing our method are estimated, showing the
                 achievement of the fast execution times of linear
                 approximation methods and the reduced area requirements
                 of other second-degree interpolation algorithms.
                 Moreover, the use of an enhanced minimax approximation
                 which, through an iterative process, takes into account
                 the effect of rounding the polynomial coefficients to a
                 finite size allows for a further reduction in the size
                 of the look-up tables to be used, making our method
                 very suitable for the implementation of an elementary
                 function generator in state-of-the-art DSPs or graphics
                 processing units (GPUs).",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: article
filename: fparith.bib
label: Revol:2005:TMF
author: N. Revol and K. Makino and M. Berz
title: Taylor models and floating-point arithmetic: proof that arithmetic operations are validated in COSY
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 135--154
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.008
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
MRclass: 65G20
MRnumber: MR2137738 (2006a:65071)
bibdate: Thu Oct 17 10:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 10:09:18 ???
URL: http://bt.pa.msu.edu/pub/papers/TMJLAP03/TMJLAP03.pdf
fjournal: Journal of Logic and Algebraic Programming
remark: Special issue on Practical development of exact real number computation.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: N. Revol and K. Makino and M. Berz
abstract:
The goal of this paper is to prove that the implementation of Taylor models in COSY, based on floating-point arithmetic, computes results satisfying the ``containment property'', i.e., guaranteed results.par First, Taylor models are defined and their implementation in the COSY software by Makino and Berz is detailed. Afterwards IEEE-754 floating-point arithmetic is introduced. Then the core of this paper is given: the algorithms implemented in COSY for multiplying a Taylor model by a scalar, for adding or multiplying two Taylor models are given and are proven to return Taylor models satisfying the containment property.

keywords:
Containment property; COSY software; Floating-point operation; Rounding error; Taylor model; Validated result

rawabstract:
The goal of this paper is to prove that the implementation of Taylor models in COSY, based on floating-point arithmetic, computes results satisfying the ``containment property'', i.e., guaranteed results.\par First, Taylor models are defined and their implementation in the COSY software by Makino and Berz is detailed. Afterwards IEEE-754 floating-point arithmetic is introduced. Then the core of this paper is given: the algorithms implemented in COSY for multiplying a Taylor model by a scalar, for adding or multiplying two Taylor models are given and are proven to return Taylor models satisfying the containment property.

rawtitle:
{Taylor} models and floating-point arithmetic: proof that arithmetic operations are validated in {COSY}

entry:
@Article{Revol:2005:TMF,
  author =       "N. Revol and K. Makino and M. Berz",
  title =        "{Taylor} models and floating-point arithmetic: proof
                 that arithmetic operations are validated in {COSY}",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "135--154",
  month =        jul,
  year =         "2005",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.008",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  MRclass =      "65G20",
  MRnumber =     "MR2137738 (2006a:65071)",
  bibdate =      "Thu Oct 17 10:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://bt.pa.msu.edu/pub/papers/TMJLAP03/TMJLAP03.pdf",
  abstract =     "The goal of this paper is to prove that the
                 implementation of Taylor models in COSY, based on
                 floating-point arithmetic, computes results satisfying
                 the ``containment property'', i.e., guaranteed
                 results.\par

                 First, Taylor models are defined and their
                 implementation in the COSY software by Makino and Berz
                 is detailed. Afterwards IEEE-754 floating-point
                 arithmetic is introduced. Then the core of this paper
                 is given: the algorithms implemented in COSY for
                 multiplying a Taylor model by a scalar, for adding or
                 multiplying two Taylor models are given and are proven
                 to return Taylor models satisfying the containment
                 property.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  keywords =     "Containment property; COSY software; Floating-point
                 operation; Rounding error; Taylor model; Validated
                 result",
  remark =       "Special issue on Practical development of exact real
                 number computation.",
}


bibtype: article
filename: fparith.bib
label: Reyhani-Masoleh:2005:LCW
author: A. Reyhani-Masoleh and M. A. Hasan
title: Low complexity word-level sequential normal basis multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 2
pages: 98--110
month: feb
monthnumber: 2
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.29
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:15 MDT 2011
bibtimestamp: 2011.07.04 16:17:15 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1377149
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Reyhani-Masoleh and M. A. Hasan
rawtitle: Low complexity word-level sequential normal basis multipliers
entry:
@Article{Reyhani-Masoleh:2005:LCW,
  author =       "A. Reyhani-Masoleh and M. A. Hasan",
  title =        "Low complexity word-level sequential normal basis
                 multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "2",
  pages =        "98--110",
  month =        feb,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.29",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:15 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1377149",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Robison:2005:BUD
author: Arch Robison
title: $N$-Bit Unsigned Division Via $N$-Bit Multiply-Add
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-104.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Arch Robison
rawtitle: {$N$}-Bit Unsigned Division Via {$N$}-Bit Multiply-Add
abstract:
Integer division on modern processors is expensive compared to multiplication. Previous algorithms for performing unsigned division by an invariant divisor, via reciprocal approximation, suffer in the worst case from a common requirement for $ n + 1 $ bit multiplication, which typically must be synthesized from $n$-bit multiplication and extra arithmetic operations. This paper presents, and proves, a hybrid of previous algorithms that replaces $ n + 1 $ bit multiplication with a single fused multiply-add operation on $n$-bit operands, thus reducing any $n$-bit unsigned division to the upper $n$ bits of a multiply-add, followed by a single right shift. An additional benefit is that the prerequisite calculations are simple and fast. On the Itanium 2 processor, the technique is advantageous for as few as two quotients that share a common run-time divisor.

rawabstract:
Integer division on modern processors is expensive compared to multiplication. Previous algorithms for performing unsigned division by an invariant divisor, via reciprocal approximation, suffer in the worst case from a common requirement for $ n + 1 $ bit multiplication, which typically must be synthesized from $n$-bit multiplication and extra arithmetic operations. This paper presents, and proves, a hybrid of previous algorithms that replaces $ n + 1 $ bit multiplication with a single fused multiply-add operation on $n$-bit operands, thus reducing any $n$-bit unsigned division to the upper $n$ bits of a multiply-add, followed by a single right shift. An additional benefit is that the prerequisite calculations are simple and fast. On the Itanium 2 processor, the technique is advantageous for as few as two quotients that share a common run-time divisor.

entry:
@InProceedings{Robison:2005:BUD,
  author =       "Arch Robison",
  title =        "{$N$}-Bit Unsigned Division Via {$N$}-Bit
                 Multiply-Add",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-104.pdf",
  abstract =     "Integer division on modern processors is expensive
                 compared to multiplication. Previous algorithms for
                 performing unsigned division by an invariant divisor,
                 via reciprocal approximation, suffer in the worst case
                 from a common requirement for $ n + 1 $ bit
                 multiplication, which typically must be synthesized
                 from $n$-bit multiplication and extra arithmetic
                 operations. This paper presents, and proves, a hybrid
                 of previous algorithms that replaces $ n + 1 $ bit
                 multiplication with a single fused multiply-add
                 operation on $n$-bit operands, thus reducing any
                 $n$-bit unsigned division to the upper $n$ bits of a
                 multiply-add, followed by a single right shift. An
                 additional benefit is that the prerequisite
                 calculations are simple and fast. On the Itanium 2
                 processor, the technique is advantageous for as few as
                 two quotients that share a common run-time divisor.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "9",
}


bibtype: techreport
filename: fparith.bib
label: Rump:2005:AFP
author: Siegfried M. Rump and Takeshi Ogita and Shin'ichi Oishi
title: Accurate Floating-Point Summation
type: Technical Report
number: 05.12
institution: Faculty for Information- and Communication Sciences, Hamburg University of Technology
address: Hamburg, Germany
pages: ??--??
day: 13
month: nov
monthnumber: 11
year: 2005
bibdate: Wed Jan 04 12:31:28 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.01.04 12:31:28 ???
URL: http://www.ti3.tu-harburg.de/paper/rump/Ru05d.pdf
keywords: accurate floating-point summation; distillation
acknowledgement: ack-nhfb
rawauthor: Siegfried M. Rump and Takeshi Ogita and Shin'ichi Oishi
rawtitle: Accurate Floating-Point Summation
entry:
@TechReport{Rump:2005:AFP,
  author =       "Siegfried M. Rump and Takeshi Ogita and Shin'ichi
                 Oishi",
  title =        "Accurate Floating-Point Summation",
  type =         "Technical Report",
  number =       "05.12",
  institution =  "Faculty for Information- and Communication Sciences,
                 Hamburg University of Technology",
  address =      "Hamburg, Germany",
  day =          "13",
  month =        nov,
  year =         "2005",
  bibdate =      "Wed Jan 04 12:31:28 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ti3.tu-harburg.de/paper/rump/Ru05d.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; distillation",
}


bibtype: article
filename: fparith.bib
label: Savas:2005:CFA
author: E. Savas
title: A carry-free architecture for Montgomery inversion
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 12
pages: 1508--1519
month: dec
monthnumber: 12
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.188
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:19 MDT 2011
bibtimestamp: 2011.07.04 16:17:19 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1524933
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: E. Savas
rawtitle: A carry-free architecture for {Montgomery} inversion
entry:
@Article{Savas:2005:CFA,
  author =       "E. Savas",
  title =        "A carry-free architecture for {Montgomery} inversion",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "12",
  pages =        "1508--1519",
  month =        dec,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.188",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:19 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1524933",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: Sax:2005:FPN
author: Jeffrey Sax
title: Floating Point in .NET part 1: Concepts and Formats
pages: 1508--1519
day: 18
month: apr
monthnumber: 4
year: 2005
bibdate: Wed Mar 15 06:07:27 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.15 06:07:27 ???
remark: Introductory tutorial on floating-point formats. Cannot find parts 2 and 3.
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: Jeffrey Sax
rawtitle: Floating Point in {.NET} part 1: {Concepts} and Formats
URL:
http://www.codeproject.com/dotnet/ExtremeFloatingPoint1.asp; http://www.codeproject.com/dotnet/ExtremeFloatingPoint1/ExtremeFloatingPoint1.zip

entry:
@Misc{Sax:2005:FPN,
  author =       "Jeffrey Sax",
  title =        "Floating Point in {.NET} part 1: {Concepts} and
                 Formats",
  howpublished = "World-Wide Web document",
  day =          "18",
  month =        apr,
  year =         "2005",
  bibdate =      "Wed Mar 15 06:07:27 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.codeproject.com/dotnet/ExtremeFloatingPoint1.asp;
                 http://www.codeproject.com/dotnet/ExtremeFloatingPoint1/ExtremeFloatingPoint1.zip",
  acknowledgement = ack-nhfb,
  remark =       "Introductory tutorial on floating-point formats.
                 Cannot find parts 2 and 3.",
}


bibtype: article
filename: fparith.bib
label: Schulte:2005:GEI
author: Michael J. Schulte and Jean-Claude Bajard
title: Guest Editors' Introduction: Special Issue on Computer Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 241--242
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.50
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Apr 27 18:04:38 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:04:38 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Michael J. Schulte and Jean-Claude Bajard
rawtitle: {Guest Editors}' Introduction: Special Issue on Computer Arithmetic
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0241.pdf; http://csdl.computer.org/dl/trans/tc/2005/03/t0241.htm

remark:
From the article: ``This special issue presents recent high-quality research in computer arithmetic. The 12 papers included in this special issue were selected from 36 papers submitted in response to an open call for papers. This call for papers followed the 16th IEEE International Symposium on Computer Arithmetic, which took place in Santiago de Compostella in June 2003. Each paper received at least three reviews and the top papers were selected for inclusion in this special issue. Six papers are expanded versions of the papers presented at the 16th IEEE Symposium on Computer Arithmetic, three are expanded versions of papers presented at other conferences, and three are original contributions.''

entry:
@Article{Schulte:2005:GEI,
  author =       "Michael J. Schulte and Jean-Claude Bajard",
  title =        "{Guest Editors}' Introduction: Special Issue on
                 Computer Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "241--242",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.50",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Apr 27 18:04:38 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0241.pdf;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0241.htm",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "From the article: ``This special issue presents recent
                 high-quality research in computer arithmetic. The 12
                 papers included in this special issue were selected
                 from 36 papers submitted in response to an open call
                 for papers. This call for papers followed the 16th IEEE
                 International Symposium on Computer Arithmetic, which
                 took place in Santiago de Compostella in June 2003.
                 Each paper received at least three reviews and the top
                 papers were selected for inclusion in this special
                 issue. Six papers are expanded versions of the papers
                 presented at the 16th IEEE Symposium on Computer
                 Arithmetic, three are expanded versions of papers
                 presented at other conferences, and three are original
                 contributions.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:2005:PED
author: M. J. Schulte and N. Lindberg and A. Laxminarain
title: Performance Evaluation of Decimal Floating-Point Arithmetic
publisher: pub-IBM
address: pub-IBM:adr
pages: ??--??
year: 2005
bibdate: Sun Mar 04 10:14:56 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 10:14:56 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and N. Lindberg and A. Laxminarain
rawtitle: Performance Evaluation of Decimal Floating-Point Arithmetic
booktitle:
Proceedings of the 6th IBM Austin Center for Advanced Studies Conference, Austin, TX, February, 2005

URL:
http://domino.watson.ibm.com/acas/w3www_acas.nsf/images/conf05/%24FILE/schulte.pdf; http://mesa.ece.wisc.edu/publications/cp_2005-14.pdf

abstract:
The prominence of decimal data in commercial and financial applications has led researchers to pursue efficient techniques for performing decimal floating-point arithmetic. While several software implementations of decimal floating-point arithmetic have been implemented, there is a growing need to provide hardware support for decimal floating-point arithmetic to keep up with the processing demands of emerging commercial and financial applications. This paper evaluates and compares the performance of decimal floating-point arithmetic operations when implemented on superscalar processors using either software libraries or specialized hardware designs. Our comparisons show that hardware implementations of decimal floating-point arithmetic operations are one to two orders of magnitude faster than software implementations.

rawabstract:
The prominence of decimal data in commercial and financial applications has led researchers to pursue efficient techniques for performing decimal floating-point arithmetic. While several software implementations of decimal floating-point arithmetic have been implemented, there is a growing need to provide hardware support for decimal floating-point arithmetic to keep up with the processing demands of emerging commercial and financial applications. This paper evaluates and compares the performance of decimal floating-point arithmetic operations when implemented on superscalar processors using either software libraries or specialized hardware designs. Our comparisons show that hardware implementations of decimal floating-point arithmetic operations are one to two orders of magnitude faster than software implementations.

rawbooktitle:
Proceedings of the 6th {IBM} Austin Center for Advanced Studies Conference, Austin, {TX}, February, 2005

entry:
@InProceedings{Schulte:2005:PED,
  author =       "M. J. Schulte and N. Lindberg and A. Laxminarain",
  booktitle =    "Proceedings of the 6th {IBM} Austin Center for
                 Advanced Studies Conference, Austin, {TX}, February,
                 2005",
  title =        "Performance Evaluation of Decimal Floating-Point
                 Arithmetic",
  publisher =    pub-IBM,
  address =      pub-IBM:adr,
  pages =        "??--??",
  year =         "2005",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Sun Mar 04 10:14:56 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://domino.watson.ibm.com/acas/w3www_acas.nsf/images/conf05/%24FILE/schulte.pdf;
                 http://mesa.ece.wisc.edu/publications/cp_2005-14.pdf",
  abstract =     "The prominence of decimal data in commercial and
                 financial applications has led researchers to pursue
                 efficient techniques for performing decimal
                 floating-point arithmetic. While several software
                 implementations of decimal floating-point arithmetic
                 have been implemented, there is a growing need to
                 provide hardware support for decimal floating-point
                 arithmetic to keep up with the processing demands of
                 emerging commercial and financial applications. This
                 paper evaluates and compares the performance of decimal
                 floating-point arithmetic operations when implemented
                 on superscalar processors using either software
                 libraries or specialized hardware designs. Our
                 comparisons show that hardware implementations of
                 decimal floating-point arithmetic operations are one to
                 two orders of magnitude faster than software
                 implementations.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Seidel:2005:HRI
author: Peter-Michael Seidel
title: High-Radix Implementation of IEEE Floating-Point Addition
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-192.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Peter-Michael Seidel
rawtitle: High-Radix Implementation of {IEEE} Floating-Point Addition
abstract:
We are proposing a micro-architecture for high-performance IEEE floating-point addition that is based on a (non-redundant) high-radix representation of the floating-point operands. The main improvement of the proposed IEEE FP addition implementation is achieved by avoiding the computation of full alignment and normalization shifts which impose major delays in conventional implementations of IEEE FP addition. This reduction is achieved at the cost of wider operand interfaces and an increased complexity for IEEE compliant rounding. We present a detailed discussion of an IEEE FP adder implementation using the proposed high-radix format and explain the specific benefits and challenges of the design.

rawabstract:
We are proposing a micro-architecture for high-performance IEEE floating-point addition that is based on a (non-redundant) high-radix representation of the floating-point operands. The main improvement of the proposed IEEE FP addition implementation is achieved by avoiding the computation of full alignment and normalization shifts which impose major delays in conventional implementations of IEEE FP addition. This reduction is achieved at the cost of wider operand interfaces and an increased complexity for IEEE compliant rounding. We present a detailed discussion of an IEEE FP adder implementation using the proposed high-radix format and explain the specific benefits and challenges of the design.

entry:
@InProceedings{Seidel:2005:HRI,
  author =       "Peter-Michael Seidel",
  title =        "High-Radix Implementation of {IEEE} Floating-Point
                 Addition",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-192.pdf",
  abstract =     "We are proposing a micro-architecture for
                 high-performance IEEE floating-point addition that is
                 based on a (non-redundant) high-radix representation of
                 the floating-point operands. The main improvement of
                 the proposed IEEE FP addition implementation is
                 achieved by avoiding the computation of full alignment
                 and normalization shifts which impose major delays in
                 conventional implementations of IEEE FP addition. This
                 reduction is achieved at the cost of wider operand
                 interfaces and an increased complexity for IEEE
                 compliant rounding. We present a detailed discussion of
                 an IEEE FP adder implementation using the proposed
                 high-radix format and explain the specific benefits and
                 challenges of the design.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Seidel:2005:SRR
author: P.-M. Seidel and L. D. McFearin and D. W. Matula
title: Secondary radix recodings for higher radix multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 2
pages: 111--123
month: feb
monthnumber: 2
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.32
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:15 MDT 2011
bibtimestamp: 2011.07.04 16:17:15 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1377150
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P.-M. Seidel and L. D. McFearin and D. W. Matula
rawtitle: Secondary radix recodings for higher radix multipliers
entry:
@Article{Seidel:2005:SRR,
  author =       "P.-M. Seidel and L. D. McFearin and D. W. Matula",
  title =        "Secondary radix recodings for higher radix
                 multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "2",
  pages =        "111--123",
  month =        feb,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.32",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:15 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1377150",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Serebrenik:2005:TFP
author: Alexander Serebrenik and Danny De Schreye
title: Termination of Floating-Point Computations
journal: j-J-AUTOM-REASON
volume: 34
number: 2
pages: 141--177
month: dec
monthnumber: 12
year: 2005
CODEN: JAREEW
DOI: https://doi.org/10.1007/s10817-005-6546-z
ISSN: 0168-7433 (print), 1573-0670 (electronic) OR 01687433 (print), 15730670 (electronic)
ISSNL: 0168-7433 OR 01687433
MRclass: 68N17 (65G99 68Q60)
MRnumber: MR2213571 (2007d:68022)
MRreviewer: Andrzej Kozlowski
bibdate: Sat Apr 2 10:50:29 MDT 2016
bibtimestamp: 2016.04.02 10:50:29 MDT
URL: http://link.springer.com/article/10.1007/s10817-005-6546-z
fjournal: Journal of Automated Reasoning
acknowledgement: ack-nhfb
ajournal: J. Autom. Reason.
journalURL: http://link.springer.com/journal/10817
rawauthor: Alexander Serebrenik and Danny {De Schreye}
rawtitle: Termination of Floating-Point Computations
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jautomreason.bib

entry:
@Article{Serebrenik:2005:TFP,
  author =       "Alexander Serebrenik and Danny {De Schreye}",
  title =        "Termination of Floating-Point Computations",
  journal =      j-J-AUTOM-REASON,
  volume =       "34",
  number =       "2",
  pages =        "141--177",
  month =        dec,
  year =         "2005",
  CODEN =        "JAREEW",
  DOI =          "https://doi.org/10.1007/s10817-005-6546-z",
  ISSN =         "0168-7433 (print), 1573-0670 (electronic)",
  ISSN-L =       "0168-7433",
  MRclass =      "68N17 (65G99 68Q60)",
  MRnumber =     "MR2213571 (2007d:68022)",
  MRreviewer =   "Andrzej Kozlowski",
  bibdate =      "Sat Apr 2 10:50:29 MDT 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jautomreason.bib",
  URL =          "http://link.springer.com/article/10.1007/s10817-005-6546-z",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Autom. Reason.",
  fjournal =     "Journal of Automated Reasoning",
  journal-URL =  "http://link.springer.com/journal/10817",
}


bibtype: inproceedings
filename: fparith.bib
label: Setiaarif:2005:NMS
author: E. Setiaarif and P. Siy
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 766--768
year: 2005
DOI: https://doi.org/10.1109/NAFIPS.2005.1548635
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: E. Setiaarif and P. Siy
booktitle:
NAFIPS 2005, Annual Meeting of the North American Fuzzy Information Processing Society, 26--28 June 2005

title:
A new moduli set selection technique to improve sign detection and number comparison in residue number system (RNS)

rawbooktitle:
{NAFIPS 2005}, Annual Meeting of the North American Fuzzy Information Processing Society, 26--28 June 2005

rawtitle:
A new moduli set selection technique to improve sign detection and number comparison in residue number system ({RNS})

entry:
@InProceedings{Setiaarif:2005:NMS,
  author =       "E. Setiaarif and P. Siy",
  booktitle =    "{NAFIPS 2005}, Annual Meeting of the North American
                 Fuzzy Information Processing Society, 26--28 June
                 2005",
  title =        "A new moduli set selection technique to improve sign
                 detection and number comparison in residue number
                 system ({RNS})",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "766--768",
  year =         "2005",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/NAFIPS.2005.1548635",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Residue number system (RNS) offers a promising future
                 because its carry-free operations in addition,
                 subtraction and multiplication. This inherent property
                 of RNS can be used to reduce the complexity of
                 calculation in many applications, such as \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Soderstrand:2005:RNS
author: M. A. Soderstrand and G. Y. Cho and L. G. Johnson
booktitle: ISCAS 2005, IEEE International Symposium on Circuits and Systems, 23--26 May 2005
title: Residue number system implementations of complex heterodyne tunable filters
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 548--551
year: 2005
DOI: https://doi.org/10.1109/ISCAS.2005.1464646
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. A. Soderstrand and G. Y. Cho and L. G. Johnson
rawbooktitle: {ISCAS 2005}, {IEEE} International Symposium on Circuits and Systems, 23--26 May 2005
rawtitle: Residue number system implementations of complex heterodyne tunable filters
entry:
@InProceedings{Soderstrand:2005:RNS,
  author =       "M. A. Soderstrand and G. Y. Cho and L. G. Johnson",
  booktitle =    "{ISCAS 2005}, {IEEE} International Symposium on
                 Circuits and Systems, 23--26 May 2005",
  title =        "Residue number system implementations of complex
                 heterodyne tunable filters",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "548--551",
  year =         "2005",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.2005.1464646",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The heterodyne signals for a complex heterodyne filter
                 based upon M/2 equally-spaced heterodyne frequencies
                 between DC and the Nyquist frequency can be generated
                 from taking integer powers of the M/sup th/ root of
                 one. In residue number systems (RNS) \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Sofroniou:2005:PNC
author: Mark Sofroniou and Giulia Spaletta
title: Precise numerical computation
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 113--134
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.007
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Thu Oct 17 10:09:18 2019
bibtimestamp: 2019.10.17 10:09:18 ???
URL: http://www.sciencedirect.com/science/article/pii/S1567832604000785
fjournal: Journal of Logic and Algebraic Programming
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: Mark Sofroniou and Giulia Spaletta
rawtitle: Precise numerical computation
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/m/metropolis-nicholas.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathematica.bib

keywords:
accuracy and precision; computer algebra systems; computer aspects of numerical algorithms; condition number; error analysis; floating-point arithmetic; interval arithmetic; Mathematica; significance arithmetic; symbolic algebra

remark:
Special issue on Practical development of exact real number computation. Paper dedicated to Jerry B. Keiper (1953--1995) and Nicholas C. Metropolis (1915--1999). It is primarily about describing Mathematica's significance arithmetic.

entry:
@Article{Sofroniou:2005:PNC,
  author =       "Mark Sofroniou and Giulia Spaletta",
  title =        "Precise numerical computation",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "113--134",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.007",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Thu Oct 17 10:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/m/metropolis-nicholas.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathematica.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S1567832604000785",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  keywords =     "accuracy and precision; computer algebra systems;
                 computer aspects of numerical algorithms; condition
                 number; error analysis; floating-point arithmetic;
                 interval arithmetic; Mathematica; significance
                 arithmetic; symbolic algebra",
  remark =       "Special issue on Practical development of exact real
                 number computation. Paper dedicated to Jerry B. Keiper
                 (1953--1995) and Nicholas C. Metropolis (1915--1999).
                 It is primarily about describing Mathematica's
                 significance arithmetic.",
}


bibtype: article
filename: fparith.bib
label: Sofronioua:2005:PNC
author: Mark Sofronioua and Giulia Spalettab
title: Precise numerical computation
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 113--134
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.007
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Fri Apr 04 08:12:14 2014
bibtimestamp: 2014.04.04 08:12:14 ???
URL: http://www.sciencedirect.com/science/article/pii/S1567832604000785
fjournal: Journal of Logic and Algebraic Programming
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: Mark Sofronioua and Giulia Spalettab
rawtitle: Precise numerical computation
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathematica.bib

keywords:
accuracy and precision; computer algebra systems; computer aspects of numerical algorithms; condition number; error analysis; floating-point arithmetic; interval arithmetic; Mathematica; significance arithmetic; symbolic algebra

entry:
@Article{Sofronioua:2005:PNC,
  author =       "Mark Sofronioua and Giulia Spalettab",
  title =        "Precise numerical computation",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "113--134",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.007",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Fri Apr 04 08:12:14 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathematica.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S1567832604000785",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  keywords =     "accuracy and precision; computer algebra systems;
                 computer aspects of numerical algorithms; condition
                 number; error analysis; floating-point arithmetic;
                 interval arithmetic; Mathematica; significance
                 arithmetic; symbolic algebra",
}


bibtype: misc
filename: fparith.bib
label: Steele:2005:SME
author: Guy L. Steele Jr.
title: System and method for extracting the high part of a floating point operand
pages: 113--134
day: 13
month: dec
monthnumber: 12
year: 2005
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/6976050/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 6976050
rawauthor: Guy L. {Steele Jr.}
rawtitle: System and method for extracting the high part of a floating point operand
abstract:
A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an overflow format. The exponent field bits and the fraction field bits of the result are set to corresponding exponent field bits and corresponding fraction field bits of the floating point operand if the determined format is a not-a-number (NaN) format. At least one of the fraction field bits of the result is adaptively cleared if the determined format is a denormalized format or a delimited format.

rawabstract:
A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an overflow format. The exponent field bits and the fraction field bits of the result are set to corresponding exponent field bits and corresponding fraction field bits of the floating point operand if the determined format is a not-a-number (NaN) format. At least one of the fraction field bits of the result is adaptively cleared if the determined format is a denormalized format or a delimited format.

entry:
@Misc{Steele:2005:SME,
  author =       "Guy L. {Steele Jr.}",
  title =        "System and method for extracting the high part of a
                 floating point operand",
  howpublished = "US Patent 6976050",
  day =          "13",
  month =        dec,
  year =         "2005",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/6976050/fulltext.html",
  abstract =     "A method and system determine a high part of a
                 floating point operand. Exponent field bits and
                 fraction field bits of a result are set to a zero if
                 the determined format is an infinity format or an
                 overflow format. The exponent field bits and the
                 fraction field bits of the result are set to
                 corresponding exponent field bits and corresponding
                 fraction field bits of the floating point operand if
                 the determined format is a not-a-number (NaN) format.
                 At least one of the fraction field bits of the result
                 is adaptively cleared if the determined format is a
                 denormalized format or a delimited format.",
  acknowledgement = ack-nhfb,
  patentdate =   "12/13/2005",
}


bibtype: misc
filename: fparith.bib
label: Steele:2005:SMF
author: Guy L. Steele Jr.
title: System and method for forcing floating point status information to selected values
pages: 113--134
day: 29
month: nov
monthnumber: 11
year: 2005
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/6970898/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 6970898
rawauthor: Guy L. {Steele Jr.}
rawtitle: System and method for forcing floating point status information to selected values
abstract:
A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.

rawabstract:
A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.

entry:
@Misc{Steele:2005:SMF,
  author =       "Guy L. {Steele Jr.}",
  title =        "System and method for forcing floating point status
                 information to selected values",
  howpublished = "US Patent 6970898",
  day =          "29",
  month =        nov,
  year =         "2005",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/6970898/fulltext.html",
  abstract =     "A floating point flag forcing circuit comprising an
                 circuit and a result assembler. The circuit receives a
                 plurality of floating point operands, analyzes the
                 floating point operand, receives one or more control
                 input signals, determines one or more predetermined
                 formats in which the plurality of operands are
                 represented, and generates one or more control signals.
                 The result assembler receives the control signals from
                 the circuit, along with one or more inputs, and
                 assembles a result.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2005:SMG
author: Guy L. Steele Jr.
title: System and method for generating an integer part of a logarithm of a floating point operand
pages: 113--134
day: 01
month: nov
monthnumber: 11
year: 2005
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/6961744/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 6961744
rawauthor: Guy L. {Steele Jr.}
rawtitle: System and method for generating an integer part of a logarithm of a floating point operand
abstract:
A logarithm unit computes an integer part of a logarithm of a floating point operand according to an embodiment of the present invention. The logarithm unit analyzes a format of the floating point operand and generates at least one signal representative of the format. The logarithm unit determines a magnitude of an unbiased exponent of the floating point operand as an intermediate result based on the at least one signal, wherein the unbiased exponent is represented by unbiased exponent bits. Still further, the logarithm unit determines an exponent field and a fraction field high part of the intermediate result. A result is assembled equaling the integer part of the logarithm of the floating point operand based on the at least one signal wherein, if the floating point operand is in at least one of a denormalized format, a normalized non-zero format, and a delimited format, an exponent field of the result equals the exponent field of the intermediate result and a fraction field high part of the result equals the fraction field high part of the intermediate result.

rawabstract:
A logarithm unit computes an integer part of a logarithm of a floating point operand according to an embodiment of the present invention. The logarithm unit analyzes a format of the floating point operand and generates at least one signal representative of the format. The logarithm unit determines a magnitude of an unbiased exponent of the floating point operand as an intermediate result based on the at least one signal, wherein the unbiased exponent is represented by unbiased exponent bits. Still further, the logarithm unit determines an exponent field and a fraction field high part of the intermediate result. A result is assembled equaling the integer part of the logarithm of the floating point operand based on the at least one signal wherein, if the floating point operand is in at least one of a denormalized format, a normalized non-zero format, and a delimited format, an exponent field of the result equals the exponent field of the intermediate result and a fraction field high part of the result equals the fraction field high part of the intermediate result.

entry:
@Misc{Steele:2005:SMG,
  author =       "Guy L. {Steele Jr.}",
  title =        "System and method for generating an integer part of a
                 logarithm of a floating point operand",
  howpublished = "US Patent 6961744",
  day =          "01",
  month =        nov,
  year =         "2005",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/6961744/fulltext.html",
  abstract =     "A logarithm unit computes an integer part of a
                 logarithm of a floating point operand according to an
                 embodiment of the present invention. The logarithm unit
                 analyzes a format of the floating point operand and
                 generates at least one signal representative of the
                 format. The logarithm unit determines a magnitude of an
                 unbiased exponent of the floating point operand as an
                 intermediate result based on the at least one signal,
                 wherein the unbiased exponent is represented by
                 unbiased exponent bits. Still further, the logarithm
                 unit determines an exponent field and a fraction field
                 high part of the intermediate result. A result is
                 assembled equaling the integer part of the logarithm of
                 the floating point operand based on the at least one
                 signal wherein, if the floating point operand is in at
                 least one of a denormalized format, a normalized
                 non-zero format, and a delimited format, an exponent
                 field of the result equals the exponent field of the
                 intermediate result and a fraction field high part of
                 the result equals the fraction field high part of the
                 intermediate result.",
  acknowledgement = ack-nhfb,
}


bibtype: phdthesis
filename: fparith.bib
label: Stehle:2004:ARR
author: Damien Stehle
type: Doctorat de l'Universite Henri Poincare --- Nancy 1 (specialite informatique)
school: Universite Henri Poincare --- Nancy
address: Nancy, France
pages: xvi + 252
year: 2004
bibdate: Fri Dec 08 09:38:41 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 09:38:41 ???
URL: https://theses.hal.science/tel-01748080/
acknowledgement: ack-nhfb
rawauthor: Damien Stehl{\'e}
title:
Algorithmique de la reduction de reseaux et application a la recherche de pires cas pour l'arrondi de fonctions mathematiques. (French) [Algorithmics of network reduction and application to the search for worst cases for rounding of mathematical functions]

abstract:
Euclidean lattices are a powerful tool for several algorithmic topics, among which are cryptography and algorithmic number theory. The contributions of this thesis are twofold: we improve lattice basis reduction algorithms, and we introduce a new application of lattice reduction, in computer arithmetic. Concerning lattices, we consider both small dimensions and arbitrary dimensions, for which we improve the classical LLL algorithm. Concerning the application, we make use of Coppersmith's method for computing the small roots of multivariate modular polynomials, in order to find the worst cases for the rounding of mathematical functions, when the function, the rounding mode and the precision are fixed. We also generalise our technique to find input numbers that are simultaneously bad for two functions. These two methods are expensive pre-computations, but once performed, they help speeding up the implementations of elementary mathematical functions in fixed precision.

rawabstract:
Euclidean lattices are a powerful tool for several algorithmic topics, among which are cryptography and algorithmic number theory. The contributions of this thesis are twofold: we improve lattice basis reduction algorithms, and we introduce a new application of lattice reduction, in computer arithmetic. Concerning lattices, we consider both small dimensions and arbitrary dimensions, for which we improve the classical LLL algorithm. Concerning the application, we make use of Coppersmith's method for computing the small roots of multivariate modular polynomials, in order to find the worst cases for the rounding of mathematical functions, when the function, the rounding mode and the precision are fixed. We also generalise our technique to find input numbers that are simultaneously bad for two functions. These two methods are expensive pre-computations, but once performed, they help speeding up the implementations of elementary mathematical functions in fixed precision.

rawtitle:
Algorithmique de la r{\'e}duction de r{\'e}seaux et application {\`a} la recherche de pires cas pour l'arrondi de fonctions math{\'e}matiques. ({French}) [{Algorithmics} of network reduction and application to the search for worst cases for rounding of mathematical functions]

entry:
@PhdThesis{Stehle:2004:ARR,
  author =       "Damien Stehl{\'e}",
  title =        "Algorithmique de la r{\'e}duction de r{\'e}seaux et
                 application {\`a} la recherche de pires cas pour
                 l'arrondi de fonctions math{\'e}matiques. ({French})
                 [{Algorithmics} of network reduction and application to
                 the search for worst cases for rounding of mathematical
                 functions]",
  type =         "Doctorat de {l'Universit{\'e} Henri Poincar{\'e} ---
                 Nancy 1 (sp{\'e}cialit{\'e} informatique)}",
  school =       "Universit{\'e} Henri Poincar{\'e} --- Nancy",
  address =      "Nancy, France",
  pages =        "xvi + 252",
  year =         "2004",
  bibdate =      "Fri Dec 08 09:38:41 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://theses.hal.science/tel-01748080/",
  abstract =     "Euclidean lattices are a powerful tool for several
                 algorithmic topics, among which are cryptography and
                 algorithmic number theory. The contributions of this
                 thesis are twofold: we improve lattice basis reduction
                 algorithms, and we introduce a new application of
                 lattice reduction, in computer arithmetic. Concerning
                 lattices, we consider both small dimensions and
                 arbitrary dimensions, for which we improve the
                 classical LLL algorithm. Concerning the application, we
                 make use of Coppersmith's method for computing the
                 small roots of multivariate modular polynomials, in
                 order to find the worst cases for the rounding of
                 mathematical functions, when the function, the rounding
                 mode and the precision are fixed. We also generalise
                 our technique to find input numbers that are
                 simultaneously bad for two functions. These two methods
                 are expensive pre-computations, but once performed,
                 they help speeding up the implementations of elementary
                 mathematical functions in fixed precision.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Stehle:2005:GAT
author: Damien Stehle and Paul Zimmermann
title: Gal's Accurate Tables Method Revisited
crossref: Montuschi:2005:PIS
pages: 275--264
year: 2005
DOI: https://doi.org/10.1109/ARITH.2005.24
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-152.pdf
keywords: ARITH-17; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Damien Stehl{\'e} and Paul Zimmermann
rawtitle: {Gal}'s Accurate Tables Method Revisited
abstract:
Gal's accurate tables algorithm aims at providing an efficient implementation of mathematical functions with correct rounding as often as possible. This method requires an expensive pre-computation of the values taken by the function or by several related functions at some distinguished points. Our improvements of Gal's method are two-fold: on the one hand we describe what is the arguably best set of distinguished values and how it improves the efficiency and accuracy of the function implementation, and on the other hand we give an algorithm which drastically decreases the cost of the pre-computation. These improvements are related to the worst cases for the correct rounding of mathematical functions and to the algorithms for finding them. We demonstrate how the whole method can be turned into practice for $ 2^x $ and $ sin x $ for $ x in [1 / 2, 1) $, in double precision.

rawabstract:
Gal's accurate tables algorithm aims at providing an efficient implementation of mathematical functions with correct rounding as often as possible. This method requires an expensive pre-computation of the values taken by the function or by several related functions at some distinguished points. Our improvements of Gal's method are two-fold: on the one hand we describe what is the arguably best set of distinguished values and how it improves the efficiency and accuracy of the function implementation, and on the other hand we give an algorithm which drastically decreases the cost of the pre-computation. These improvements are related to the worst cases for the correct rounding of mathematical functions and to the algorithms for finding them. We demonstrate how the whole method can be turned into practice for $ 2^x $ and $ \sin x $ for $ x \in [1 / 2, 1) $, in double precision.

entry:
@InProceedings{Stehle:2005:GAT,
  author =       "Damien Stehl{\'e} and Paul Zimmermann",
  title =        "{Gal}'s Accurate Tables Method Revisited",
  crossref =     "Montuschi:2005:PIS",
  pages =        "275--264",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ARITH.2005.24",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-152.pdf",
  abstract =     "Gal's accurate tables algorithm aims at providing an
                 efficient implementation of mathematical functions with
                 correct rounding as often as possible. This method
                 requires an expensive pre-computation of the values
                 taken by the function or by several related functions
                 at some distinguished points. Our improvements of Gal's
                 method are two-fold: on the one hand we describe what
                 is the arguably best set of distinguished values and
                 how it improves the efficiency and accuracy of the
                 function implementation, and on the other hand we give
                 an algorithm which drastically decreases the cost of
                 the pre-computation. These improvements are related to
                 the worst cases for the correct rounding of
                 mathematical functions and to the algorithms for
                 finding them. We demonstrate how the whole method can
                 be turned into practice for $ 2^x $ and $ \sin x $ for
                 $ x \in [1 / 2, 1) $, in double precision.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; correct rounding; floating-point
                 arithmetic",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Stehle:2005:SWC
author: Damien Stehle and Vincent Lefevre and Paul Zimmermann
title: Searching Worst Cases of a One-Variable Function Using Lattice Reduction
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 340--346
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.55
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Damien Stehl{\'e} and Vincent Lef{\`e}vre and Paul Zimmermann
rawtitle: Searching Worst Cases of a One-Variable Function Using Lattice Reduction
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0340abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0340.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0340.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388198.pdf?isnumber=30205&prod=JNL&arnumber=1388198&arSt=+340&ared=+346&arAuthor=Stehle%2C+D.%3B+Lefevre%2C+V.%3B+Zimmermann%2C+P.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388198&count=13&index=9; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388198

abstract:
We propose a new algorithm to find worst cases for the correct rounding of a mathematical function of one variable. We first reduce this problem to the real small value problem---i.e., for polynomials with real coefficients. Then, we show that this second problem can be solved efficiently by extending Coppersmith's work on the integer small value problem---for polynomials with integer coefficients---using lattice reduction. For floating-point numbers with a mantissa less than $N$ and a polynomial approximation of degree $d$, our algorithm finds all worst cases at distance less than $ N^frac -d^22d + 1 $ from a machine number in time $ O(N^frac d + 12d + 1 + varepsilon ) $. For $ d = 2 $, a detailed study improves on the $ O(N^2 / 3 + varepsilon ) $ complexity from Lefevre's algorithm to $ O(N^4 / 7 + varepsilon ) $. For larger $d$, our algorithm can be used to check that there exist no worst cases at distance less than $ N^-k $ in time $ O(N^1 / 2 + varepsilon ) $.

keywords:
ARITH-16; Computer arithmetic; correct rounding; multiple precision arithmetic; special function approximations

rawabstract:
We propose a new algorithm to find worst cases for the correct rounding of a mathematical function of one variable. We first reduce this problem to the real small value problem---i.e., for polynomials with real coefficients. Then, we show that this second problem can be solved efficiently by extending Coppersmith's work on the integer small value problem---for polynomials with integer coefficients---using lattice reduction. For floating-point numbers with a mantissa less than $N$ and a polynomial approximation of degree $d$, our algorithm finds all worst cases at distance less than $ N^{\frac {-d^2}{2d + 1}} $ from a machine number in time $ O(N^{{\frac {d + 12d + 1}} + \varepsilon }) $. For $ d = 2 $, a detailed study improves on the $ O(N^{2 / 3 + \varepsilon }) $ complexity from Lef{\`e}vre's algorithm to $ O(N^{4 / 7 + \varepsilon }) $. For larger $d$, our algorithm can be used to check that there exist no worst cases at distance less than $ N^{-k} $ in time $ O(N^{1 / 2 + \varepsilon }) $.

entry:
@Article{Stehle:2005:SWC,
  author =       "Damien Stehl{\'e} and Vincent Lef{\`e}vre and Paul
                 Zimmermann",
  title =        "Searching Worst Cases of a One-Variable Function Using
                 Lattice Reduction",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "340--346",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.55",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0340abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0340.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0340.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388198.pdf?isnumber=30205&prod=JNL&arnumber=1388198&arSt=+340&ared=+346&arAuthor=Stehle%2C+D.%3B+Lefevre%2C+V.%3B+Zimmermann%2C+P.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388198&count=13&index=9;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388198",
  abstract =     "We propose a new algorithm to find worst cases for the
                 correct rounding of a mathematical function of one
                 variable. We first reduce this problem to the real
                 small value problem---i.e., for polynomials with real
                 coefficients. Then, we show that this second problem
                 can be solved efficiently by extending Coppersmith's
                 work on the integer small value problem---for
                 polynomials with integer coefficients---using lattice
                 reduction. For floating-point numbers with a mantissa
                 less than $N$ and a polynomial approximation of degree
                 $d$, our algorithm finds all worst cases at distance
                 less than $ N^{\frac {-d^2}{2d + 1}} $ from a machine
                 number in time $ O(N^{{\frac {d + 12d + 1}} +
                 \varepsilon }) $. For $ d = 2 $, a detailed study
                 improves on the $ O(N^{2 / 3 + \varepsilon }) $
                 complexity from Lef{\`e}vre's algorithm to $ O(N^{4 / 7
                 + \varepsilon }) $. For larger $d$, our algorithm can
                 be used to check that there exist no worst cases at
                 distance less than $ N^{-k} $ in time $ O(N^{1 / 2 +
                 \varepsilon }) $.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16; Computer arithmetic; correct rounding;
                 multiple precision arithmetic; special function
                 approximations",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: inproceedings
filename: fparith.bib
label: Stine:2005:CTC
author: J. E. Stine and M. J. Schulte
title: A Combined Two's Complement and Floating-Point Comparator
crossref: IEEE:2005:IIS
pages: 89--92
year: 2005
bibdate: Sun Mar 04 21:02:35 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 21:02:35 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2005-09.pdf
acknowledgement: ack-nhfb
rawauthor: J. E. Stine and M. J. Schulte
rawtitle: A Combined Two's Complement and Floating-Point Comparator
entry:
@InProceedings{Stine:2005:CTC,
  author =       "J. E. Stine and M. J. Schulte",
  title =        "A Combined Two's Complement and Floating-Point
                 Comparator",
  crossref =     "IEEE:2005:IIS",
  pages =        "89--92",
  year =         "2005",
  bibdate =      "Sun Mar 04 21:02:35 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2005-09.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2005:HAI
author: Naofumi Takagi and Shunsuke Kadowaki and Kazuyoshi Takagi
title: A Hardware Algorithm for Integer Division
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-113.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Naofumi Takagi and Shunsuke Kadowaki and Kazuyoshi Takagi
rawtitle: A Hardware Algorithm for Integer Division
abstract:
A hardware algorithm for integer division is proposed. It is based on the digit-recurrence, non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit representation. The algorithm does not require normalization of the divisor, and hence, does not require area-consuming leading one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, where pipelining is possible for increasing the throughput. Sequential implementation yields a compact divider.

rawabstract:
A hardware algorithm for integer division is proposed. It is based on the digit-recurrence, non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit representation. The algorithm does not require normalization of the divisor, and hence, does not require area-consuming leading one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, where pipelining is possible for increasing the throughput. Sequential implementation yields a compact divider.

entry:
@InProceedings{Takagi:2005:HAI,
  author =       "Naofumi Takagi and Shunsuke Kadowaki and Kazuyoshi
                 Takagi",
  title =        "A Hardware Algorithm for Integer Division",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-113.pdf",
  abstract =     "A hardware algorithm for integer division is proposed.
                 It is based on the digit-recurrence, non-restoring
                 division algorithm. Fast computation is achieved by the
                 use of the radix-2 signed-digit representation. The
                 algorithm does not require normalization of the
                 divisor, and hence, does not require area-consuming
                 leading one (or zero) detection nor shifts of
                 variable-amount. Combinational (unfolded)
                 implementation of the algorithm yields a regularly
                 structured array divider, where pipelining is possible
                 for increasing the throughput. Sequential
                 implementation yields a compact divider.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "7",
}


bibtype: article
filename: fparith.bib
label: Takahashi:2005:AMP
author: Daisuke Takahashi
title: An algorithm for multiple-precision floating-point multiplication
journal: j-APPL-MATH-COMP
volume: 166
number: 2
pages: 291--298
day: 15
month: jul
monthnumber: 7
year: 2005
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
MRclass: 65G99
MRnumber: MR2143788 (2006a:65075)
bibdate: Mon Jul 4 09:15:46 MDT 2005
bibtimestamp: 2005.07.04 09:15:46 MDT
fjournal: Applied Mathematics and Computation
keywords: Fast Fourier transform; Multiple-precision arithmetic; Multiplication; Program derivation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Daisuke Takahashi
rawtitle: An algorithm for multiple-precision floating-point multiplication
bibsource:
http://www.sciencedirect.com/science/journal/00963003; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We present an algorithm for multiple-precision floating-point multiplication. The conventional algorithms based on the fast Fourier transform (FFT) multiply two $n$-bit numbers to obtain a $ 2 n $-bit result. In multiple-precision floating-point multiplication, we need only the returned result whose precision is equal to the multiple-precision floating-point number. We show that the overall arithmetic operations for FFT-based multiple-precision floating-point multiplication are reduced by decomposition of the full-length multiplication into shorter-length multiplication.

rawabstract:
We present an algorithm for multiple-precision floating-point multiplication. The conventional algorithms based on the fast Fourier transform (FFT) multiply two $n$-bit numbers to obtain a $ 2 n $-bit result. In multiple-precision floating-point multiplication, we need only the returned result whose precision is equal to the multiple-precision floating-point number. We show that the overall arithmetic operations for FFT-based multiple-precision floating-point multiplication are reduced by decomposition of the full-length multiplication into shorter-length multiplication.

entry:
@Article{Takahashi:2005:AMP,
  author =       "Daisuke Takahashi",
  title =        "An algorithm for multiple-precision floating-point
                 multiplication",
  journal =      j-APPL-MATH-COMP,
  volume =       "166",
  number =       "2",
  pages =        "291--298",
  day =          "15",
  month =        jul,
  year =         "2005",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  MRclass =      "65G99",
  MRnumber =     "MR2143788 (2006a:65075)",
  bibdate =      "Mon Jul 4 09:15:46 MDT 2005",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present an algorithm for multiple-precision
                 floating-point multiplication. The conventional
                 algorithms based on the fast Fourier transform (FFT)
                 multiply two $n$-bit numbers to obtain a $ 2 n $-bit
                 result. In multiple-precision floating-point
                 multiplication, we need only the returned result whose
                 precision is equal to the multiple-precision
                 floating-point number. We show that the overall
                 arithmetic operations for FFT-based multiple-precision
                 floating-point multiplication are reduced by
                 decomposition of the full-length multiplication into
                 shorter-length multiplication.",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
  keywords =     "Fast Fourier transform; Multiple-precision arithmetic;
                 Multiplication; Program derivation",
}


bibtype: techreport
filename: fparith.bib
label: Tang:2005:BBI
author: Ping Tak Peter Tang
type: Technical report
institution: Intel Corporation
address: San Jose, CA, USA
pages: 291--298
day: 17
month: jun
monthnumber: 6
year: 2005
bibdate: Thu Oct 14 14:50:39 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.14 14:50:39 ???
keywords: BID (Binary-Integer Decimal) Encoding; decimal floating point arithmetic
remark: Last Updated: July 12, 2005. Minor Modifications: January 3, 2006
acknowledgement: ack-nhfb
rawauthor: Ping Tak Peter Tang
title:
BID --- Binary-Integer Decimal Encoding for Decimal Floating Point: a Format Friendly to Software Emulation and Compiler Native Support

rawtitle:
{BID} --- Binary-Integer Decimal Encoding for Decimal Floating Point: a Format Friendly to Software Emulation and Compiler Native Support

entry:
@TechReport{Tang:2005:BBI,
  author =       "Ping Tak Peter Tang",
  title =        "{BID} --- Binary-Integer Decimal Encoding for Decimal
                 Floating Point: a Format Friendly to Software Emulation
                 and Compiler Native Support",
  type =         "Technical report",
  institution =  "Intel Corporation",
  address =      "San Jose, CA, USA",
  day =          "17",
  month =        jun,
  year =         "2005",
  bibdate =      "Thu Oct 14 14:50:39 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "BID (Binary-Integer Decimal) Encoding; decimal
                 floating point arithmetic",
  remark =       "Last Updated: July 12, 2005. Minor Modifications:
                 January 3, 2006",
}


bibtype: techreport
filename: fparith.bib
label: Tang:2005:GBE
author: Ping Tak Peter Tang
title: On Generalized BCD Encodings for Decimal Floating Point
type: Technical comment
institution: Software and Solutions Group, Intel Corporation
address: San Jose, CA, USA
pages: 291--298
day: 7
month: mar
monthnumber: 3
year: 2005
bibdate: Sat Nov 05 21:19:43 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.05 21:19:43 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Ping Tak Peter Tang
rawtitle: On Generalized {BCD} Encodings for Decimal Floating Point
entry:
@TechReport{Tang:2005:GBE,
  author =       "Ping Tak Peter Tang",
  title =        "On Generalized {BCD} Encodings for Decimal Floating
                 Point",
  type =         "Technical comment",
  institution =  "Software and Solutions Group, Intel Corporation",
  address =      "San Jose, CA, USA",
  day =          "7",
  month =        mar,
  year =         "2005",
  bibdate =      "Sat Nov 05 21:19:43 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Tsuiki:2005:RNC
author: Hideki Tsuiki
title: Real number computation with committed choice logic programming languages
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 61--84
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.005
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Thu Oct 17 10:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 10:09:18 ???
fjournal: Journal of Logic and Algebraic Programming
remark: Special issue on Practical development of exact real number computation.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: Hideki Tsuiki
rawtitle: Real number computation with committed choice logic programming languages
entry:
@Article{Tsuiki:2005:RNC,
  author =       "Hideki Tsuiki",
  title =        "Real number computation with committed choice logic
                 programming languages",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "61--84",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.005",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Thu Oct 17 10:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  remark =       "Special issue on Practical development of exact real
                 number computation.",
}


bibtype: incollection
filename: fparith.bib
label: Turing:2005:PEC
author: Alan M. Turing
title: Proposed Electronic Calculator (1945)
crossref: Copeland:2005:ATA
pages: ??--??
year: 2005
DOI: https://doi.org/10.1093/acprof:oso/9780198565932.003.0021
bibdate: Mon Nov 01 18:47:26 2010
bibtimestamp: 2010.11.01 18:47:26 ???
acknowledgement: ack-nhfb
authordates: Alan Mathison Turing (23 June 1912--7 June 1954)
rawauthor: Alan M. Turing
rawtitle: Proposed Electronic Calculator (1945)
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/t/turing-alan-mathison.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
This chapter presents Alan M. Turing's report, `Proposed Electronic Calculator'. The report was submitted to the Executive Committee of the National Physical Laboratory in February 1946, under the description `Report by Dr. A. M. Turing on Proposals for the Development of an Automatic Computing Engine (ACE)'. The design set out in `Proposed Electronic Calculator' was the basis for all the ACE computers.

rawabstract:
This chapter presents Alan M. Turing's report, `Proposed Electronic Calculator'. The report was submitted to the Executive Committee of the National Physical Laboratory in February 1946, under the description `Report by Dr. A. M. Turing on Proposals for the Development of an Automatic Computing Engine (ACE)'. The design set out in `Proposed Electronic Calculator' was the basis for all the ACE computers.

entry:
@InCollection{Turing:2005:PEC,
  author =       "Alan M. Turing",
  title =        "Proposed Electronic Calculator (1945)",
  crossref =     "Copeland:2005:ATA",
  pages =        "??--??",
  year =         "2005",
  DOI =          "https://doi.org/10.1093/acprof:oso/9780198565932.003.0021",
  bibdate =      "Mon Nov 01 18:47:26 2010",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/t/turing-alan-mathison.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This chapter presents Alan M. Turing's report,
                 `Proposed Electronic Calculator'. The report was
                 submitted to the Executive Committee of the National
                 Physical Laboratory in February 1946, under the
                 description `Report by Dr. A. M. Turing on Proposals
                 for the Development of an Automatic Computing Engine
                 (ACE)'. The design set out in `Proposed Electronic
                 Calculator' was the basis for all the ACE computers.",
  acknowledgement = ack-nhfb,
  author-dates = "Alan Mathison Turing (23 June 1912--7 June 1954)",
}


bibtype: inproceedings
filename: fparith.bib
label: Usevitch:2005:JCL
author: B. Usevitch
booktitle: Proceedings. DCC 2005 Data Compression Conference, 29--31 March 2005
title: JPEG2000 Compliant Lossless Coding of Floating Point Data
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 484--484
year: 2005
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: B. Usevitch
rawbooktitle: Proceedings. {DCC 2005} Data Compression Conference, 29--31 March 2005
rawtitle: {JPEG2000} Compliant Lossless Coding of Floating Point Data
entry:
@InProceedings{Usevitch:2005:JCL,
  author =       "B. Usevitch",
  booktitle =    "Proceedings. {DCC 2005} Data Compression Conference,
                 29--31 March 2005",
  title =        "{JPEG2000} Compliant Lossless Coding of Floating Point
                 Data",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "484--484",
  year =         "2005",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Verdonk:2005:BSI
author: B. Verdonk and J. Vervloet and A. Cuyt
title: Blending Set and Interval Arithmetic for Maximal Reliability
journal: j-COMPUTING
volume: 74
number: 1
pages: 41--65
month: feb
monthnumber: 2
year: 2005
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-004-0090-2
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Tue Jul 5 09:25:15 MDT 2005
bibtimestamp: 2005.07.05 09:25:15 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=74&issue=1&spage=41
fjournal: Computing: Archiv fur informatik und numerik
keywords: inclusion property; Interval arithmetic
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: B. Verdonk and J. Vervloet and A. Cuyt
rawtitle: Blending Set and Interval Arithmetic for Maximal Reliability
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=74&issue=1; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
In both [3] and [8], the authors review the implementation of the basic operations in interval arithmetic, and in particular discuss the different approaches given in the literature for interval division when the divisor interval contains zero. In these papers, and in the references therein, the basic operations are defined for real or extended real interval operands.par Division by an interval containing zero is a special case of an interval function for which the input arguments contain points outside the domain of the underlying point function. A number of approaches exist in the literature, [7], [12], to remove restrictions on the domain of interval functions and hence obtain a closed, exception-free interval system.par In this paper, we present an alternative approach to remove restrictions on the domain of interval functions and to guarantee the inclusion property in all situations, even when some input intervals contain points that lie outside the domain of the underlying point function. To achieve this, we allow for the (efficient) set-based representation of non-real results. The computed intervals are sharp, yet contain more information and the resulting interval system is closed and exception-free. We also show how the presented ideas can be implemented in an interval arithmetic library. The performance overhead is negligible compared to the fact that the implementation using the new approach offers 100% reliability in return.par The structure of the paper is as follows. We set off with a motivating example in Sect. 1. In Sect. 2, we review various approaches to interval division and then introduce vset-division of real intervals, based on the newly introduced concept of value set or vset. In Sect. 3, we give a formal definition of real vset-intervals and arithmetic on these intervals. We prove a number of essential properties and point out the likenesses and differences with other approaches. Finally, in Sect. 4, we discuss the implementation of vset-interval arithmetic in a floating-point context.

rawabstract:
In both [3] and [8], the authors review the implementation of the basic operations in interval arithmetic, and in particular discuss the different approaches given in the literature for interval division when the divisor interval contains zero. In these papers, and in the references therein, the basic operations are defined for real or extended real interval operands.\par Division by an interval containing zero is a special case of an interval function for which the input arguments contain points outside the domain of the underlying point function. A number of approaches exist in the literature, [7], [12], to remove restrictions on the domain of interval functions and hence obtain a closed, exception-free interval system.\par In this paper, we present an alternative approach to remove restrictions on the domain of interval functions and to guarantee the inclusion property in all situations, even when some input intervals contain points that lie outside the domain of the underlying point function. To achieve this, we allow for the (efficient) set-based representation of non-real results. The computed intervals are sharp, yet contain more information and the resulting interval system is closed and exception-free. We also show how the presented ideas can be implemented in an interval arithmetic library. The performance overhead is negligible compared to the fact that the implementation using the new approach offers 100\% reliability in return.\par The structure of the paper is as follows. We set off with a motivating example in Sect. 1. In Sect. 2, we review various approaches to interval division and then introduce vset-division of real intervals, based on the newly introduced concept of value set or vset. In Sect. 3, we give a formal definition of real vset-intervals and arithmetic on these intervals. We prove a number of essential properties and point out the likenesses and differences with other approaches. Finally, in Sect. 4, we discuss the implementation of vset-interval arithmetic in a floating-point context.

entry:
@Article{Verdonk:2005:BSI,
  author =       "B. Verdonk and J. Vervloet and A. Cuyt",
  title =        "Blending Set and Interval Arithmetic for Maximal
                 Reliability",
  journal =      j-COMPUTING,
  volume =       "74",
  number =       "1",
  pages =        "41--65",
  month =        feb,
  year =         "2005",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-004-0090-2",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Tue Jul 5 09:25:15 MDT 2005",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=74&issue=1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=74&issue=1&spage=41",
  abstract =     "In both [3] and [8], the authors review the
                 implementation of the basic operations in interval
                 arithmetic, and in particular discuss the different
                 approaches given in the literature for interval
                 division when the divisor interval contains zero. In
                 these papers, and in the references therein, the basic
                 operations are defined for real or extended real
                 interval operands.\par

                 Division by an interval containing zero is a special
                 case of an interval function for which the input
                 arguments contain points outside the domain of the
                 underlying point function. A number of approaches exist
                 in the literature, [7], [12], to remove restrictions on
                 the domain of interval functions and hence obtain a
                 closed, exception-free interval system.\par

                 In this paper, we present an alternative approach to
                 remove restrictions on the domain of interval functions
                 and to guarantee the inclusion property in all
                 situations, even when some input intervals contain
                 points that lie outside the domain of the underlying
                 point function. To achieve this, we allow for the
                 (efficient) set-based representation of non-real
                 results. The computed intervals are sharp, yet contain
                 more information and the resulting interval system is
                 closed and exception-free. We also show how the
                 presented ideas can be implemented in an interval
                 arithmetic library. The performance overhead is
                 negligible compared to the fact that the implementation
                 using the new approach offers 100\% reliability in
                 return.\par

                 The structure of the paper is as follows. We set off
                 with a motivating example in Sect. 1. In Sect. 2, we
                 review various approaches to interval division and then
                 introduce vset-division of real intervals, based on the
                 newly introduced concept of value set or vset. In Sect.
                 3, we give a formal definition of real vset-intervals
                 and arithmetic on these intervals. We prove a number of
                 essential properties and point out the likenesses and
                 differences with other approaches. Finally, in Sect. 4,
                 we discuss the implementation of vset-interval
                 arithmetic in a floating-point context.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
  keywords =     "inclusion property; Interval arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Wahid:2005:EFC
author: Khan Wahid and Vassil Dimitrov and Graham Jullien
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-138.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Khan Wahid and Vassil Dimitrov and Graham Jullien
title:
Error-Free Computation of $ 8 times 8 $ $2$-D DCT and IDCT using Two-Dimensional Algebraic Integer Quantization

abstract:
This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both $ 8 times 8 $ $2$-D Discrete Cosine Transform and Inverse DCT. The architecture uses a new algebraic integer quantization of a $1$-D radix-8 DCT that allows the separable computation of a $2$-D $ 8 times 8 $ DCT without any intermediate number representation conversions. This is a considerable improvement on previously introduced algebraic integer encoding techniques to compute both DCT and IDCT which eliminates the requirements to approximate the transformation matrix elements by obtaining their exact representations and hence mapping the transcendental functions without any errors. Using this encoding scheme, an entire $ 8 times 8 $ $1$-D DCT-SQ (scalar quantization) algorithm can be implemented with only 24 adders. Apart from the multiplication-free nature, this new mapping scheme fits to this algorithm, eliminating any computational or quantization errors and resulting short-word-length and high-speed-design.

rawabstract:
This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both $ 8 \times 8 $ $2$-D Discrete Cosine Transform and Inverse DCT. The architecture uses a new algebraic integer quantization of a $1$-D radix-8 DCT that allows the separable computation of a $2$-D $ 8 \times 8 $ DCT without any intermediate number representation conversions. This is a considerable improvement on previously introduced algebraic integer encoding techniques to compute both DCT and IDCT which eliminates the requirements to approximate the transformation matrix elements by obtaining their exact representations and hence mapping the transcendental functions without any errors. Using this encoding scheme, an entire $ 8 \times 8 $ $1$-D DCT-SQ (scalar quantization) algorithm can be implemented with only 24 adders. Apart from the multiplication-free nature, this new mapping scheme fits to this algorithm, eliminating any computational or quantization errors and resulting short-word-length and high-speed-design.

rawtitle:
Error-Free Computation of $ 8 \times 8 $ {$2$-D} {DCT} and {IDCT} using Two-Dimensional Algebraic Integer Quantization

entry:
@InProceedings{Wahid:2005:EFC,
  author =       "Khan Wahid and Vassil Dimitrov and Graham Jullien",
  title =        "Error-Free Computation of $ 8 \times 8 $ {$2$-D} {DCT}
                 and {IDCT} using Two-Dimensional Algebraic Integer
                 Quantization",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-138.pdf",
  abstract =     "This paper presents a novel error-free
                 (infinite-precision) architecture for the fast
                 implementation of both $ 8 \times 8 $ $2$-D Discrete
                 Cosine Transform and Inverse DCT. The architecture uses
                 a new algebraic integer quantization of a $1$-D radix-8
                 DCT that allows the separable computation of a $2$-D $
                 8 \times 8 $ DCT without any intermediate number
                 representation conversions. This is a considerable
                 improvement on previously introduced algebraic integer
                 encoding techniques to compute both DCT and IDCT which
                 eliminates the requirements to approximate the
                 transformation matrix elements by obtaining their exact
                 representations and hence mapping the transcendental
                 functions without any errors. Using this encoding
                 scheme, an entire $ 8 \times 8 $ $1$-D DCT-SQ (scalar
                 quantization) algorithm can be implemented with only 24
                 adders. Apart from the multiplication-free nature, this
                 new mapping scheme fits to this algorithm, eliminating
                 any computational or quantization errors and resulting
                 short-word-length and high-speed-design.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


