# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Lue:1999:ADE
author: Jeng-Jong J. Lue and Dhananjay S. Phatak
crossref: Koren:1999:ISC
pages: 216--224
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Jeng-Jong J. Lue and Dhananjay S. Phatak
title:
Area $ times $ Delay ($ A cdot T $) Efficient Multipliers Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation

URL:
http://euler.ecs.umass.edu/paper/final/paper-159.pdf; http://euler.ecs.umass.edu/paper/final/paper-159.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Lue.pdf

abstract:
Intermediate Signed Digit (SD) representation can facilitate fast and compact VLSI implementations of partial product accumulation trees. It achieves a reduction ratio of 2:1 at every level and also leads to more regular layouts. Its disadvantage is that the number of bit lines that need to routed can be high. This can lead to a significant area overhead especially at smaller feature sizes where the wire/interconnect area and delay can be dominant.par A Hybrid Signed Digit (HSD) representation lets some of the digits be unsigned bits, thereby reducing the number of bit lines. By arbitrarily varying the positions of and distances between consecutive signed digits, this representation can trade off latency for area and offers a continuum of choices between the two's complement representation on the one hand and fully Signed Digit (FSD or simply SD) representation on the other.par In this paper, we illustrate an $ A cdot T $ (area $ times $ delay) efficient multiplier based on the HSD?1 representation which is one of the many possible HSD formats, wherein every alternate digit is signed and the rest are unsigned (ordinary) bits. It is seen that multipliers based on HSD?1 format require more transistors than those based on FSD format. However, they require fewer bit lines to be routed, which substantially reduces the interconnect area; thereby leading to a reduction in the total VLSI area and a lower $ A cdot T $ product. The design reaffirms that the interconnect area can be significant especially at small feature sizes.

rawabstract:
Intermediate Signed Digit (SD) representation can facilitate fast and compact VLSI implementations of partial product accumulation trees. It achieves a reduction ratio of 2:1 at every level and also leads to more regular layouts. Its disadvantage is that the number of bit lines that need to routed can be high. This can lead to a significant area overhead especially at smaller feature sizes where the wire/interconnect area and delay can be dominant.\par A Hybrid Signed Digit (HSD) representation lets some of the digits be unsigned bits, thereby reducing the number of bit lines. By arbitrarily varying the positions of and distances between consecutive signed digits, this representation can trade off latency for area and offers a continuum of choices between the two's complement representation on the one hand and fully Signed Digit (FSD or simply SD) representation on the other.\par In this paper, we illustrate an $ A \cdot T $ (area $ \times $ delay) efficient multiplier based on the HSD?1 representation which is one of the many possible HSD formats, wherein every alternate digit is signed and the rest are unsigned (ordinary) bits. It is seen that multipliers based on HSD?1 format require more transistors than those based on FSD format. However, they require fewer bit lines to be routed, which substantially reduces the interconnect area; thereby leading to a reduction in the total VLSI area and a lower $ A \cdot T $ product. The design reaffirms that the interconnect area can be significant especially at small feature sizes.

rawtitle:
Area $ \times $ Delay ({$ A \cdot T $}) Efficient Multipliers Based on an Intermediate Hybrid Signed-Digit ({HSD-1}) Representation

entry:
@InProceedings{Lue:1999:ADE,
  author =       "Jeng-Jong J. Lue and Dhananjay S. Phatak",
  title =        "Area $ \times $ Delay ({$ A \cdot T $}) Efficient
                 Multipliers Based on an Intermediate Hybrid
                 Signed-Digit ({HSD-1}) Representation",
  crossref =     "Koren:1999:ISC",
  pages =        "216--224",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-159.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-159.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Lue.pdf",
  abstract =     "Intermediate Signed Digit (SD) representation can
                 facilitate fast and compact VLSI implementations of
                 partial product accumulation trees. It achieves a
                 reduction ratio of 2:1 at every level and also leads to
                 more regular layouts. Its disadvantage is that the
                 number of bit lines that need to routed can be high.
                 This can lead to a significant area overhead especially
                 at smaller feature sizes where the wire/interconnect
                 area and delay can be dominant.\par

                 A Hybrid Signed Digit (HSD) representation lets some of
                 the digits be unsigned bits, thereby reducing the
                 number of bit lines. By arbitrarily varying the
                 positions of and distances between consecutive signed
                 digits, this representation can trade off latency for
                 area and offers a continuum of choices between the
                 two's complement representation on the one hand and
                 fully Signed Digit (FSD or simply SD) representation on
                 the other.\par

                 In this paper, we illustrate an $ A \cdot T $ (area $
                 \times $ delay) efficient multiplier based on the HSD?1
                 representation which is one of the many possible HSD
                 formats, wherein every alternate digit is signed and
                 the rest are unsigned (ordinary) bits. It is seen that
                 multipliers based on HSD?1 format require more
                 transistors than those based on FSD format. However,
                 they require fewer bit lines to be routed, which
                 substantially reduces the interconnect area; thereby
                 leading to a reduction in the total VLSI area and a
                 lower $ A \cdot T $ product. The design reaffirms that
                 the interconnect area can be significant especially at
                 small feature sizes.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Mahesh:1999:IAE
author: M. N. Mahesh and S. Gupta and M. Mehendale
booktitle: Twelfth International Conference on VLSI Design, 1999. Proceedings
title: Improving area efficiency of residue number system based implementation of DSP algorithms
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 340--345
year: 1999
DOI: https://doi.org/10.1109/ICVD.1999.745179
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. N. Mahesh and S. Gupta and M. Mehendale
rawbooktitle: Twelfth International Conference on {VLSI} Design, 1999. Proceedings
rawtitle: Improving area efficiency of residue number system based implementation of {DSP} algorithms
entry:
@InProceedings{Mahesh:1999:IAE,
  author =       "M. N. Mahesh and S. Gupta and M. Mehendale",
  booktitle =    "Twelfth International Conference on {VLSI} Design,
                 1999. Proceedings",
  title =        "Improving area efficiency of residue number system
                 based implementation of {DSP} algorithms",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "340--345",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICVD.1999.745179",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Residue Number System based applications involve
                 modulo-arithmetic which is typically implemented using
                 look-up-tables (LUTs) for a small value of modulus. In
                 this paper we present a data coding technique to
                 minimize the area of these LUTs when \ldots{}",
}


bibtype: article
filename: fparith.bib
label: McCullough:1999:ARS
author: B. D. McCullough
title: Assessing the Reliability of Statistical Software: Part II
journal: j-AMER-STAT
volume: 53
number: 2
pages: 149--159
month: may
monthnumber: 5
year: 1999
CODEN: ASTAAJ
ISSN: 0003-1305 (print), 1537-2731 (electronic) OR 00031305 (print), 15372731 (electronic)
ISSNL: 0003-1305 OR 00031305
bibdate: Fri Jan 27 14:51:25 MST 2012
bibtimestamp: 2012.01.27 14:51:25 MST
URL: http://www.amstat.org/publications/tas/mccull.pdf; http://www.jstor.org/stable/2685736
fjournal: The American Statistician
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/utas20
rawauthor: B. D. McCullough
rawtitle: Assessing the Reliability of Statistical Software: {Part II}
bibsource:
http://www.amstat.org/publications/tas/toc_99.html; http://www.jstor.org/journals/00031305.html; http://www.jstor.org/stable/i326504; https://www.math.utah.edu/pub/tex/bib/amstat1990.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{McCullough:1999:ARS,
  author =       "B. D. McCullough",
  title =        "Assessing the Reliability of Statistical Software:
                 {Part II}",
  journal =      j-AMER-STAT,
  volume =       "53",
  number =       "2",
  pages =        "149--159",
  month =        may,
  year =         "1999",
  CODEN =        "ASTAAJ",
  ISSN =         "0003-1305 (print), 1537-2731 (electronic)",
  ISSN-L =       "0003-1305",
  bibdate =      "Fri Jan 27 14:51:25 MST 2012",
  bibsource =    "http://www.amstat.org/publications/tas/toc_99.html;
                 http://www.jstor.org/journals/00031305.html;
                 http://www.jstor.org/stable/i326504;
                 https://www.math.utah.edu/pub/tex/bib/amstat1990.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.amstat.org/publications/tas/mccull.pdf;
                 http://www.jstor.org/stable/2685736",
  acknowledgement = ack-nhfb,
  fjournal =     "The American Statistician",
  journal-URL =  "http://www.tandfonline.com/loi/utas20",
}


bibtype: article
filename: fparith.bib
label: McCullough:1999:NRE
author: B. D. McCullough and H. D. Vinod
title: The Numerical Reliability of Econometric Software
journal: j-J-ECON-LIT
volume: 37
number: 2
pages: 633--665
month: jun
monthnumber: 6
year: 1999
CODEN: JECLB3
DOI: https://doi.org/10.1257/jel.37.2.633
ISSN: 0022-0515 (print), 1547-1101 (electronic) OR 00220515 (print), 15471101 (electronic)
ISSNL: 0022-0515 OR 00220515
bibdate: Thu Oct 17 05:56:48 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib
bibtimestamp: 2019.10.17 05:56:48 ???
URL: http://www.jstor.org/stable/2565215; https://www.aeaweb.org/articles?id=10.1257/jel.37.2.633
fjournal: Journal of Economic Literature
acknowledgement: ack-nhfb
journalURL: https://www.aeaweb.org/journals/jel/issues
rawauthor: B. D. McCullough and H. D. Vinod
rawtitle: The Numerical Reliability of Econometric Software
abstract:
Numerous examples show that some econometric software packages contain serious flaws, and that users cannot safely assume that their software is accurate. A brief survey of the fundamentals of computer arithmetic discusses the sources of numerical error and emphasizes that computer arithmetic is not at all like pencil-and-paper arithmetic. Both users and developers of econometrics software should first pay attention to accuracy, and only later consider user-friendliness. Details are provided for assessing the accuracy of basic estimation routines, statistical distributions, and random number generators. More accuracy benchmarks are needed, especially for specialized econometric procedures.

remark:
This paper discusses the effect of both floating-point arithmetic and random-number generators on econometric computations.

rawabstract:
Numerous examples show that some econometric software packages contain serious flaws, and that users cannot safely assume that their software is accurate. A brief survey of the fundamentals of computer arithmetic discusses the sources of numerical error and emphasizes that computer arithmetic is not at all like pencil-and-paper arithmetic. Both users and developers of econometrics software should first pay attention to accuracy, and only later consider user-friendliness. Details are provided for assessing the accuracy of basic estimation routines, statistical distributions, and random number generators. More accuracy benchmarks are needed, especially for specialized econometric procedures.

entry:
@Article{McCullough:1999:NRE,
  author =       "B. D. McCullough and H. D. Vinod",
  title =        "The Numerical Reliability of Econometric Software",
  journal =      j-J-ECON-LIT,
  volume =       "37",
  number =       "2",
  pages =        "633--665",
  month =        jun,
  year =         "1999",
  CODEN =        "JECLB3",
  DOI =          "https://doi.org/10.1257/jel.37.2.633",
  ISSN =         "0022-0515 (print), 1547-1101 (electronic)",
  ISSN-L =       "0022-0515",
  bibdate =      "Thu Oct 17 05:56:48 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  URL =          "http://www.jstor.org/stable/2565215;
                 https://www.aeaweb.org/articles?id=10.1257/jel.37.2.633",
  abstract =     "Numerous examples show that some econometric software
                 packages contain serious flaws, and that users cannot
                 safely assume that their software is accurate. A brief
                 survey of the fundamentals of computer arithmetic
                 discusses the sources of numerical error and emphasizes
                 that computer arithmetic is not at all like
                 pencil-and-paper arithmetic. Both users and developers
                 of econometrics software should first pay attention to
                 accuracy, and only later consider user-friendliness.
                 Details are provided for assessing the accuracy of
                 basic estimation routines, statistical distributions,
                 and random number generators. More accuracy benchmarks
                 are needed, especially for specialized econometric
                 procedures.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Economic Literature",
  journal-URL =  "https://www.aeaweb.org/journals/jel/issues",
  remark =       "This paper discusses the effect of both floating-point
                 arithmetic and random-number generators on econometric
                 computations.",
}


bibtype: inproceedings
filename: fparith.bib
label: Montuschi:1999:BVH
author: Paolo Montuschi and Tomas Lang
title: Boosting Very High Radix Division with Prescaling and Selection by Rounding
crossref: Koren:1999:ISC
pages: 52--59
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Paolo Montuschi and Tom{\'a}s Lang
rawtitle: Boosting Very High Radix Division with Prescaling and Selection by Rounding
URL:
http://euler.ecs.umass.edu/paper/final/paper-150.pdf; http://euler.ecs.umass.edu/paper/final/paper-150.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Montuschi.pdf

abstract:
An extension of the very-high radix division with prescaling and selection by rounding is presented. This extension consists in increasing the effective radix of the implementation by obtaining a few additional bits of the quotient per iteration, without increasing the complexity of the unit to obtain the prescaling factor nor the delay of an iteration. As a consequence, for some values of the effective radix, it permits an implementation with a smaller area and the same execution time than the original scheme. Estimations are given for 54-bit and 114-bit quotients.

rawabstract:
An extension of the very-high radix division with prescaling and selection by rounding is presented. This extension consists in increasing the effective radix of the implementation by obtaining a few additional bits of the quotient per iteration, without increasing the complexity of the unit to obtain the prescaling factor nor the delay of an iteration. As a consequence, for some values of the effective radix, it permits an implementation with a smaller area and the same execution time than the original scheme. Estimations are given for 54-bit and 114-bit quotients.

entry:
@InProceedings{Montuschi:1999:BVH,
  author =       "Paolo Montuschi and Tom{\'a}s Lang",
  title =        "Boosting Very High Radix Division with Prescaling and
                 Selection by Rounding",
  crossref =     "Koren:1999:ISC",
  pages =        "52--59",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-150.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-150.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Montuschi.pdf",
  abstract =     "An extension of the very-high radix division with
                 prescaling and selection by rounding is presented. This
                 extension consists in increasing the effective radix of
                 the implementation by obtaining a few additional bits
                 of the quotient per iteration, without increasing the
                 complexity of the unit to obtain the prescaling factor
                 nor the delay of an iteration. As a consequence, for
                 some values of the effective radix, it permits an
                 implementation with a smaller area and the same
                 execution time than the original scheme. Estimations
                 are given for 54-bit and 114-bit quotients.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Muller:1999:FRT
author: Jean-Michel Muller
title: A Few Results on Table-Based Methods
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 279--288
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: Jean-Michel Muller
rawtitle: A Few Results on Table-Based Methods
entry:
@Article{Muller:1999:FRT,
  author =       "Jean-Michel Muller",
  title =        "A Few Results on Table-Based Methods",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "279--288",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: article
filename: fparith.bib
label: Muroi:1999:ESR
author: Kazuo Muroi
title: Extraction of square roots in Babylonian mathematics
journal: j-HIST-SCI-2
volume: 9
number: 2
pages: 127--133
month: nov
monthnumber: 11
year: 1999
CODEN: HISCDU
ISSN: 0285-4821 OR 02854821
ISSNL: 0285-4821 OR 02854821
MRclass: 01A17
MRnumber: 1762167
MRreviewer: Bruno Poizat
bibdate: Sat Oct 6 17:22:25 2018
bibtimestamp: 2018.10.06 17:22:25 ???
acknowledgement: ack-nhfb
journalURL: http://hssj.info/
rawauthor: Kazuo Muroi
rawtitle: Extraction of square roots in {Babylonian} mathematics
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/histscijpn.bib

fjournal:
Historia Scientiarum. Second Series. International Journal of the History of Science Society of Japan

entry:
@Article{Muroi:1999:ESR,
  author =       "Kazuo Muroi",
  title =        "Extraction of square roots in {Babylonian}
                 mathematics",
  journal =      j-HIST-SCI-2,
  volume =       "9",
  number =       "2",
  pages =        "127--133",
  month =        nov,
  year =         "1999",
  CODEN =        "HISCDU",
  ISSN =         "0285-4821",
  ISSN-L =       "0285-4821",
  MRclass =      "01A17",
  MRnumber =     "1762167",
  MRreviewer =   "Bruno Poizat",
  bibdate =      "Sat Oct 6 17:22:25 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/histscijpn.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Historia Scientiarum. Second Series. International
                 Journal of the History of Science Society of Japan",
  journal-URL =  "http://hssj.info/",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:1999:LPDa
author: Alberto Nannarelli and Tomas Lang
title: Low-Power Division: Comparison among Implementations of Radix $4$, $8$ and $ 16 $
crossref: Koren:1999:ISC
pages: 60--69
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli and Tomas Lang
rawtitle: Low-Power Division: Comparison among Implementations of Radix $4$, $8$ and $ 16 $
URL:
http://euler.ecs.umass.edu/paper/final/paper-158.pdf; http://euler.ecs.umass.edu/paper/final/paper-158.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Nannarelli.pdf

abstract:
Although division is less frequent than addition and multiplication, because of its longer latency it dissipates a substantial part of the energy in floating-point units. In this paper we explore the relation between the radix and the energy dissipated. Previous work has been done on radix-4 and radix-8 division. Here we extend this study to a radix-16 scheme with two overlapped radix-4 stages and compare the latency, area, and energy of the three implementations.par Results show that by applying the low-power techniques the energy dissipation is reduced from 30% to 40%, with respect to the standard implementation. An additional 20% reduction can be obtained using a dual voltage. Moreover, the energy dissipated to complete the division is roughly the same for the three radices. However, the power dissipation, proportional to the average current, increases with the radix. If reducing the energy is the priority, for the same latency radix-16 with dual voltage produces the smallest energy dissipation.

rawabstract:
Although division is less frequent than addition and multiplication, because of its longer latency it dissipates a substantial part of the energy in floating-point units. In this paper we explore the relation between the radix and the energy dissipated. Previous work has been done on radix-4 and radix-8 division. Here we extend this study to a radix-16 scheme with two overlapped radix-4 stages and compare the latency, area, and energy of the three implementations.\par Results show that by applying the low-power techniques the energy dissipation is reduced from 30\% to 40\%, with respect to the standard implementation. An additional 20\% reduction can be obtained using a dual voltage. Moreover, the energy dissipated to complete the division is roughly the same for the three radices. However, the power dissipation, proportional to the average current, increases with the radix. If reducing the energy is the priority, for the same latency radix-16 with dual voltage produces the smallest energy dissipation.

entry:
@InProceedings{Nannarelli:1999:LPDa,
  author =       "Alberto Nannarelli and Tomas Lang",
  title =        "Low-Power Division: Comparison among Implementations
                 of Radix $4$, $8$ and $ 16 $",
  crossref =     "Koren:1999:ISC",
  pages =        "60--69",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-158.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-158.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Nannarelli.pdf",
  abstract =     "Although division is less frequent than addition and
                 multiplication, because of its longer latency it
                 dissipates a substantial part of the energy in
                 floating-point units. In this paper we explore the
                 relation between the radix and the energy dissipated.
                 Previous work has been done on radix-4 and radix-8
                 division. Here we extend this study to a radix-16
                 scheme with two overlapped radix-4 stages and compare
                 the latency, area, and energy of the three
                 implementations.\par

                 Results show that by applying the low-power techniques
                 the energy dissipation is reduced from 30\% to 40\%,
                 with respect to the standard implementation. An
                 additional 20\% reduction can be obtained using a dual
                 voltage. Moreover, the energy dissipated to complete
                 the division is roughly the same for the three radices.
                 However, the power dissipation, proportional to the
                 average current, increases with the radix. If reducing
                 the energy is the priority, for the same latency
                 radix-16 with dual voltage produces the smallest energy
                 dissipation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Nannarelli:1999:LPDb
author: A. Nannarelli and T. Lang
title: Low-Power Divider
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 1
pages: 2--14
month: jan
monthnumber: 1
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.743407
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:56 MDT 2011
bibtimestamp: 2011.07.06 08:46:56 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=743407
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Nannarelli and T. Lang
rawtitle: Low-Power Divider
entry:
@Article{Nannarelli:1999:LPDb,
  author =       "A. Nannarelli and T. Lang",
  title =        "Low-Power Divider",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "1",
  pages =        "2--14",
  month =        jan,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.743407",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=743407",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:1999:LPR
author: Alberto Nannarelli and Tomas Lang
booktitle: (ICCD '99) International Conference on Computer Design
title: Low-power radix-$4$ combined division and square root
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 236--242
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli and Tomas Lang
rawbooktitle: {(ICCD '99)} International Conference on Computer Design
rawtitle: Low-power radix-$4$ combined division and square root
entry:
@InProceedings{Nannarelli:1999:LPR,
  author =       "Alberto Nannarelli and Tomas Lang",
  booktitle =    "{(ICCD '99)} International Conference on Computer
                 Design",
  title =        "Low-power radix-$4$ combined division and square
                 root",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "236--242",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Because of the similarities in the algorithm it is
                 quite common to implement division and square root in
                 the same unit. The purpose of this work is to implement
                 a low-power combined radix-$4$ division and square root
                 floating-point double precision \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Nedialkov:1999:IHO
author: N. S. Nedialkov and K. R. Jackson
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 289--310
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: N. S. Nedialkov and K. R. Jackson
title:
An Interval Hermite-Obreschkoff Method for Computing Rigorous Bounds on the Solution of an Initial Value Problem for an Ordinary Differential Equation

rawtitle:
An Interval Hermite-Obreschkoff Method for Computing Rigorous Bounds on the Solution of an Initial Value Problem for an Ordinary Differential Equation

entry:
@Article{Nedialkov:1999:IHO,
  author =       "N. S. Nedialkov and K. R. Jackson",
  title =        "An Interval Hermite-Obreschkoff Method for Computing
                 Rigorous Bounds on the Solution of an Initial Value
                 Problem for an Ordinary Differential Equation",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "289--310",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: inproceedings
filename: fparith.bib
label: Northrop:1999:GM
title: 600MHz G5 S/390 Microprocessor
crossref: Wuorinen:1999:IIS
pages: ??--??
year: 1999
bibdate: Mon Jan 08 08:40:27 2001
bibsource: http://www.sscs.org/digests/1999/DATA/05_2.pdf; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.01.08 08:40:27 ???
acknowledgement: ack-nhfb
rawtitle: {600MHz G5 S/390} Microprocessor
author:
G. Northrop and R. Averill and K. Barkley and S. Carey and Y. Chan and Y. H. Chan and M. Check and D. Hoffman and W. Huott and B. Krumm and C. Krygowski and J. Liptay and M. Mayo and T. McNamara and T. McPherson and E. Schwarz and L. Sigal and T. Slegel and C. Webb and D. Webber and P. Williams

rawauthor:
G. Northrop and R. Averill and K. Barkley and S. Carey and Y. Chan and Y. H. Chan and M. Check and D. Hoffman and W. Huott and B. Krumm and C. Krygowski and J. Liptay and M. Mayo and T. McNamara and T. McPherson and E. Schwarz and L. Sigal and T. Slegel and C. Webb and D. Webber and P. Williams

entry:
@InProceedings{Northrop:1999:GM,
  author =       "G. Northrop and R. Averill and K. Barkley and S. Carey
                 and Y. Chan and Y. H. Chan and M. Check and D. Hoffman
                 and W. Huott and B. Krumm and C. Krygowski and J.
                 Liptay and M. Mayo and T. McNamara and T. McPherson and
                 E. Schwarz and L. Sigal and T. Slegel and C. Webb and
                 D. Webber and P. Williams",
  title =        "{600MHz G5 S/390} Microprocessor",
  crossref =     "Wuorinen:1999:IIS",
  pages =        "??--??",
  year =         "1999",
  bibdate =      "Mon Jan 08 08:40:27 2001",
  bibsource =    "http://www.sscs.org/digests/1999/DATA/05_2.pdf;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  pagecount =    "9",
}


bibtype: inproceedings
filename: fparith.bib
label: Oberman:1999:FPD
author: Stuart F. Oberman
crossref: Koren:1999:ISC
pages: 106--115
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Stuart F. Oberman
title:
Floating point division and square root algorithms and implementation in the AMD-K7TM microprocessor

URL:
http://euler.ecs.umass.edu/paper/final/paper-139.pdf; http://euler.ecs.umass.edu/paper/final/paper-139.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Oberman.pdf

abstract:
This paper presents the AMD-K7 IEEE 754 and x87 compliant floating point division and square root algorithms and implementation. The AMD-K7 processor employs an iterative implementation of a series expansion to converge quadratically to the quotient and square root. Highly accurate initial approximations and a high performance shared floating point multiplier assist in achieving low division and square root latencies at high operating frequencies. A novel time-sharing technique allows independent floating point multiplication operations to proceed while division or square root computation is in progress. Exact IEEE 754 rounding for all rounding modes and target precisions has been verified by conventional directed and random testing procedures, along with the formulation of a mechanically-checked formal proof using the ACL2 theorem prover.

rawabstract:
This paper presents the AMD-K7 IEEE 754 and x87 compliant floating point division and square root algorithms and implementation. The AMD-K7 processor employs an iterative implementation of a series expansion to converge quadratically to the quotient and square root. Highly accurate initial approximations and a high performance shared floating point multiplier assist in achieving low division and square root latencies at high operating frequencies. A novel time-sharing technique allows independent floating point multiplication operations to proceed while division or square root computation is in progress. Exact IEEE 754 rounding for all rounding modes and target precisions has been verified by conventional directed and random testing procedures, along with the formulation of a mechanically-checked formal proof using the ACL2 theorem prover.

rawtitle:
Floating point division and square root algorithms and implementation in the {AMD-K7{\TM}} microprocessor

entry:
@InProceedings{Oberman:1999:FPD,
  author =       "Stuart F. Oberman",
  title =        "Floating point division and square root algorithms and
                 implementation in the {AMD-K7{\TM}} microprocessor",
  crossref =     "Koren:1999:ISC",
  pages =        "106--115",
  year =         "1999",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-139.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-139.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Oberman.pdf",
  abstract =     "This paper presents the AMD-K7 IEEE 754 and x87
                 compliant floating point division and square root
                 algorithms and implementation. The AMD-K7 processor
                 employs an iterative implementation of a series
                 expansion to converge quadratically to the quotient and
                 square root. Highly accurate initial approximations and
                 a high performance shared floating point multiplier
                 assist in achieving low division and square root
                 latencies at high operating frequencies. A novel
                 time-sharing technique allows independent floating
                 point multiplication operations to proceed while
                 division or square root computation is in progress.
                 Exact IEEE 754 rounding for all rounding modes and
                 target precisions has been verified by conventional
                 directed and random testing procedures, along with the
                 formulation of a mechanically-checked formal proof
                 using the ACL2 theorem prover.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
  summary =      "This paper presents the AMD-K7 IEEE 754 and $\times$87
                 compliant floating point division and square root
                 algorithms and implementation. The AMD-K7 processor
                 employs an iterative implementation of a series
                 expansion to converge quadratically to the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: OLeary:1999:FVI
author: John O'Leary and Xudong Zhao and Rob Gerth and Carl-Johan H. Seger
title: Formally Verifying IEEE Compliance of Floating-Point Hardware
journal: j-INTEL-TECH-J
volume: Q1
pages: 10
day: 17
month: feb
monthnumber: 2
year: 1999
bibdate: Fri Jun 01 06:02:08 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.01 06:02:08 ???
acknowledgement: ack-nhfb
rawauthor: John O'Leary and Xudong Zhao and Rob Gerth and Carl-Johan H. Seger
rawtitle: Formally Verifying {IEEE} Compliance of Floating-Point Hardware
URL:
http://developer.intel.com/technology/itj/q11999/articles/art_5.htm; http://developer.intel.com/technology/itj/q11999/pdf/floating_point.pdf

entry:
@Article{OLeary:1999:FVI,
  author =       "John O'Leary and Xudong Zhao and Rob Gerth and
                 Carl-Johan H. Seger",
  title =        "Formally Verifying {IEEE} Compliance of Floating-Point
                 Hardware",
  journal =      j-INTEL-TECH-J,
  volume =       "Q1",
  pages =        "10",
  day =          "17",
  month =        feb,
  year =         "1999",
  bibdate =      "Fri Jun 01 06:02:08 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://developer.intel.com/technology/itj/q11999/articles/art_5.htm;
                 http://developer.intel.com/technology/itj/q11999/pdf/floating_point.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Paar:1999:FAP
author: C. Paar and P. Fleischmann and P. Soria-Rodriguez
title: Fast arithmetic for public-key algorithms in Galois fields with composite exponents
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 10
pages: 1025--1034
month: oct
monthnumber: 10
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.805153
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:59 MDT 2011
bibtimestamp: 2011.07.06 08:46:59 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=805153
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: C. Paar and P. Fleischmann and P. Soria-Rodriguez
rawtitle: Fast arithmetic for public-key algorithms in {Galois} fields with composite exponents
entry:
@Article{Paar:1999:FAP,
  author =       "C. Paar and P. Fleischmann and P. Soria-Rodriguez",
  title =        "Fast arithmetic for public-key algorithms in {Galois}
                 fields with composite exponents",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "10",
  pages =        "1025--1034",
  month =        oct,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.805153",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:59 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=805153",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Paliouras:1999:MAR
author: V. Paliouras and T. Stouraitis
title: Multifunction Architectures for RNS Processors
journal: j-IEEE-TRANS-CIRCUITS-SYST
volume: 46
number: 8
pages: 1041--1054
month: aug
monthnumber: 8
year: 1999
CODEN: ICSYBT
ISSN: 0098-4094 (print), 1558-1276 (electronic) OR 00984094 (print), 15581276 (electronic)
ISSNL: 0098-4094 OR 00984094
bibdate: Fri Jun 24 18:26:56 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 18:26:56 ???
fjournal: IEEE Transactions on Circuits and Systems
keywords: Residue Number System (RNS)
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and T. Stouraitis
rawtitle: Multifunction Architectures for {RNS} Processors
entry:
@Article{Paliouras:1999:MAR,
  author =       "V. Paliouras and T. Stouraitis",
  title =        "Multifunction Architectures for {RNS} Processors",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST,
  volume =       "46",
  number =       "8",
  pages =        "1041--1054",
  month =        aug,
  year =         "1999",
  CODEN =        "ICSYBT",
  ISSN =         "0098-4094 (print), 1558-1276 (electronic)",
  ISSN-L =       "0098-4094",
  bibdate =      "Fri Jun 24 18:26:56 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems",
  keywords =     "Residue Number System (RNS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Paliouras:1999:NHR
author: V. Paliouras and T. Stouraitis
title: Novel high-radix residue number system multipliers and adders
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 451--454
year: 1999
DOI: https://doi.org/10.1109/ISCAS.1999.777911
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and T. Stouraitis
rawtitle: Novel high-radix residue number system multipliers and adders
booktitle:
ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 2 June 1999

rawbooktitle:
{ISCAS '99}. Proceedings of the 1999 {IEEE} International Symposium on Circuits and Systems, 2 June 1999

entry:
@InProceedings{Paliouras:1999:NHR,
  author =       "V. Paliouras and T. Stouraitis",
  booktitle =    "{ISCAS '99}. Proceedings of the 1999 {IEEE}
                 International Symposium on Circuits and Systems, 2 June
                 1999",
  title =        "Novel high-radix residue number system multipliers and
                 adders",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "451--454",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1999.777911",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Radix-r modulo r n multipliers and adders are
                 introduced in this paper. The proposed architectures
                 are shown to require several times less area than
                 previously reported architectures, for particular
                 moduli of operation. The proposed \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parhami:1999:ALT
author: B. Parhami
booktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
title: Analysis of the lookup table size for square-rooting
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1327--1330
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: B. Parhami
rawbooktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
rawtitle: Analysis of the lookup table size for square-rooting
entry:
@InProceedings{Parhami:1999:ALT,
  author =       "B. Parhami",
  booktitle =    "Conference Record of the Thirty-Third Asilomar
                 Conference on Signals, Systems, and Computers, 1999",
  title =        "Analysis of the lookup table size for square-rooting",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1327--1330",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Convergence methods are widely used for division,
                 reciprocation, and square-rooting. With such methods,
                 it is common to use an initial table lookup step for
                 obtaining an approximate result that leads to faster
                 convergence. In the case of division \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Park:1999:FPM
author: W.-C. Park and T.-D. Han and S.-D. Kim and S.-B. Yang
title: A floating point multiplier performing IEEE rounding and addition in parallel
journal: j-J-SYST-ARCH
volume: 45
number: 14
pages: 1195--1207
month: jul
monthnumber: 7
year: 1999
CODEN: JSARFB
ISSN: 1383-7621 (print), 1873-6165 (electronic) OR 13837621 (print), 18736165 (electronic)
ISSNL: 1383-7621 OR 13837621
bibdate: Fri Nov 8 05:39:32 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.11.08 05:39:32 MST
fjournal: Journal of Systems Architecture
acknowledgement: ack-nhfb
rawauthor: W.-C. Park and T.-D. Han and S.-D. Kim and S.-B. Yang
rawtitle: A floating point multiplier performing {IEEE} rounding and addition in parallel
entry:
@Article{Park:1999:FPM,
  author =       "W.-C. Park and T.-D. Han and S.-D. Kim and S.-B.
                 Yang",
  title =        "A floating point multiplier performing {IEEE} rounding
                 and addition in parallel",
  journal =      j-J-SYST-ARCH,
  volume =       "45",
  number =       "14",
  pages =        "1195--1207",
  month =        jul,
  year =         "1999",
  CODEN =        "JSARFB",
  ISSN =         "1383-7621 (print), 1873-6165 (electronic)",
  ISSN-L =       "1383-7621",
  bibdate =      "Fri Nov 8 05:39:32 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Systems Architecture",
  pagecount =    "13",
}


bibtype: misc
filename: fparith.bib
label: Parker:1999:SPA
author: D. Stott Parker
title: A semi-portable ANSI C implementation of Monte Carlo floating-point arithmetic
pages: 1195--1207
year: 1999
bibdate: Mon Aug 25 15:08:02 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.08.25 15:08:02 ???
URL: http://www.cs.ucla.edu/~stott/mca/MCAdemo.c
acknowledgement: ack-nhfb
howpublished: World-Wide Web document.
rawauthor: D. Stott Parker
rawtitle: A semi-portable {ANSI} {C} implementation of {Monte Carlo} floating-point arithmetic
entry:
@Misc{Parker:1999:SPA,
  author =       "D. Stott Parker",
  title =        "A semi-portable {ANSI} {C} implementation of {Monte
                 Carlo} floating-point arithmetic",
  howpublished = "World-Wide Web document.",
  year =         "1999",
  bibdate =      "Mon Aug 25 15:08:02 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.ucla.edu/~stott/mca/MCAdemo.c",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Parks:1999:NTT
author: Michael Parks
title: Number-Theoretic Test Generation for Directed Rounding
crossref: Koren:1999:ISC
pages: 241--249
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic; correct rounding; floating-point arithmetic; floating-point testing
acknowledgement: ack-nhfb
rawauthor: Michael Parks
rawtitle: Number-Theoretic Test Generation for Directed Rounding
URL:
http://euler.ecs.umass.edu/paper/final/paper-131.pdf; http://euler.ecs.umass.edu/paper/final/paper-131.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Parks.pdf

abstract:
We present methods to generate systematically the hardest test cases for multiplication, division, and square root subject to directed rounding, essentially extending previous work on number-theoretic floating-point testing to rounding modes other than to-nearest. The algorithms focus upon the rounding boundaries of the modes truncate, to-minus-infinity, and to-infinity, and programs based on them require little beyond exact arithmetic in the working precision to create billions of edge cases. We will show that the amount of work required to calculate trial multiplicands pays off in the form of free extra tests due to an interconnection among the operations considered herein. Although these tests do not replace proofs of correctness, they can be used to gain a high degree of confidence that the accuracy requirements as mandated by IEEE Standard 754 have been satisfied.

rawabstract:
We present methods to generate systematically the hardest test cases for multiplication, division, and square root subject to directed rounding, essentially extending previous work on number-theoretic floating-point testing to rounding modes other than to-nearest. The algorithms focus upon the rounding boundaries of the modes truncate, to-minus-infinity, and to-infinity, and programs based on them require little beyond exact arithmetic in the working precision to create billions of edge cases. We will show that the amount of work required to calculate trial multiplicands pays off in the form of free extra tests due to an interconnection among the operations considered herein. Although these tests do not replace proofs of correctness, they can be used to gain a high degree of confidence that the accuracy requirements as mandated by IEEE Standard 754 have been satisfied.

entry:
@InProceedings{Parks:1999:NTT,
  author =       "Michael Parks",
  title =        "Number-Theoretic Test Generation for Directed
                 Rounding",
  crossref =     "Koren:1999:ISC",
  pages =        "241--249",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-131.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-131.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Parks.pdf",
  abstract =     "We present methods to generate systematically the
                 hardest test cases for multiplication, division, and
                 square root subject to directed rounding, essentially
                 extending previous work on number-theoretic
                 floating-point testing to rounding modes other than
                 to-nearest. The algorithms focus upon the rounding
                 boundaries of the modes truncate, to-minus-infinity,
                 and to-infinity, and programs based on them require
                 little beyond exact arithmetic in the working precision
                 to create billions of edge cases. We will show that the
                 amount of work required to calculate trial
                 multiplicands pays off in the form of free extra tests
                 due to an interconnection among the operations
                 considered herein. Although these tests do not replace
                 proofs of correctness, they can be used to gain a high
                 degree of confidence that the accuracy requirements as
                 mandated by IEEE Standard 754 have been satisfied.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic; correct rounding;
                 floating-point arithmetic; floating-point testing",
  summary =      "We present methods to generate systematically the
                 hardest test cases for multiplication, division, and
                 square root subject to directed rounding, essentially
                 extending previous work on number-theoretic floating
                 point testing to rounding modes other \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Phatak:1999:IVE
author: Dhananjay S. Phatak and I. Koren
crossref: Koren:1999:ISC
pages: 22--29
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Dhananjay S. Phatak and I. Koren
title:
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition

URL:
http://euler.ecs.umass.edu/paper/final/paper-149.pdf; http://euler.ecs.umass.edu/paper/final/paper-149.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Phatak.pdf

abstract:
In two operand addition, bit-wise intermediate variables such as the ``propagate'' and ``generate'' terms are defined / evaluated first. Basic carry propagation recursion is then expressed in terms of these variables and is ``unrolled'' to obtain a tree structure for fast execution. In CMOS VLSI technology, multiplexors are fast and efficient to implement. Hence, we investigate in this paper all possible two-bit encodings for the intermediate variables and identify the ones that enable multiplexor-based implementations. Some of these encodings enable further simplification of the multiplexor-based realizations. Our analysis also shows that adopting an intermediate signed-digit representation simply amounts to selecting one of the possible encodings. Thus, there is no inherent advantage to the use of intermediate signed-digit representations in a two operand addition. Finally, we extend our analysis to the generalized look-ahead-recursions proposed by Doran.

rawabstract:
In two operand addition, bit-wise intermediate variables such as the ``propagate'' and ``generate'' terms are defined \slash evaluated first. Basic carry propagation recursion is then expressed in terms of these variables and is ``unrolled'' to obtain a tree structure for fast execution. In CMOS VLSI technology, multiplexors are fast and efficient to implement. Hence, we investigate in this paper all possible two-bit encodings for the intermediate variables and identify the ones that enable multiplexor-based implementations. Some of these encodings enable further simplification of the multiplexor-based realizations. Our analysis also shows that adopting an intermediate signed-digit representation simply amounts to selecting one of the possible encodings. Thus, there is no inherent advantage to the use of intermediate signed-digit representations in a two operand addition. Finally, we extend our analysis to the generalized look-ahead-recursions proposed by Doran.

rawtitle:
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition

entry:
@InProceedings{Phatak:1999:IVE,
  author =       "Dhananjay S. Phatak and I. Koren",
  title =        "Intermediate Variable Encodings that Enable
                 Multiplexor-Based Implementations of Two Operand
                 Addition",
  crossref =     "Koren:1999:ISC",
  pages =        "22--29",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-149.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-149.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Phatak.pdf",
  abstract =     "In two operand addition, bit-wise intermediate
                 variables such as the ``propagate'' and ``generate''
                 terms are defined \slash evaluated first. Basic carry
                 propagation recursion is then expressed in terms of
                 these variables and is ``unrolled'' to obtain a tree
                 structure for fast execution. In CMOS VLSI technology,
                 multiplexors are fast and efficient to implement.
                 Hence, we investigate in this paper all possible
                 two-bit encodings for the intermediate variables and
                 identify the ones that enable multiplexor-based
                 implementations. Some of these encodings enable further
                 simplification of the multiplexor-based realizations.
                 Our analysis also shows that adopting an intermediate
                 signed-digit representation simply amounts to selecting
                 one of the possible encodings. Thus, there is no
                 inherent advantage to the use of intermediate
                 signed-digit representations in a two operand addition.
                 Finally, we extend our analysis to the generalized
                 look-ahead-recursions proposed by Doran.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Ralev:1999:RBF
author: K. R. Ralev and P. H. Bauer
title: Realization of block floating-point digital filters and application to block implementations
journal: j-IEEE-TRANS-SIG-PROC
volume: 47
number: 4
pages: 1076--1086
month: apr
monthnumber: 4
year: 1999
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: K. R. Ralev and P. H. Bauer
rawtitle: Realization of block floating-point digital filters and application to block implementations
entry:
@Article{Ralev:1999:RBF,
  author =       "K. R. Ralev and P. H. Bauer",
  title =        "Realization of block floating-point digital filters
                 and application to block implementations",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "47",
  number =       "4",
  pages =        "1076--1086",
  month =        apr,
  year =         "1999",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "Realization issues of block floating-point (BFP)
                 filters such as complexity, roundoff noise, and absence
                 of limit cycles are analyzed. Several new results are
                 established. Under certain conditions, BFP filters
                 perform better than fixed-point filters \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ruess:1999:MVS
author: Harald Ruess and Natarajan Shankar and Mandayam K. Srivas
title: Modular Verification of SRT Division
journal: j-FORM-METHODS-SYST-DES
volume: 14
number: 1
pages: 45--73
month: jan
monthnumber: 1
year: 1999
CODEN: FMSDE6
ISSN: 0925-9856 (print), 1572-8102 (electronic) OR 09259856 (print), 15728102 (electronic)
ISSNL: 0925-9856 OR 09259856
bibdate: Sat Jun 02 09:22:39 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 09:22:39 ???
note: Special issue on arithmetic circuits.
URL: http://www.wkap.nl/jrnltoc.htm/0925-9856; http://www.wkap.nl/oasis.htm/194807
fjournal: Formal Methods in System Design
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/fmsd
rawauthor: Harald Ruess and Natarajan Shankar and Mandayam K. Srivas
rawnote: Special issue on arithmetic circuits.
rawtitle: Modular Verification of {SRT} Division
entry:
@Article{Ruess:1999:MVS,
  author =       "Harald Ruess and Natarajan Shankar and Mandayam K.
                 Srivas",
  title =        "Modular Verification of {SRT} Division",
  journal =      j-FORM-METHODS-SYST-DES,
  volume =       "14",
  number =       "1",
  pages =        "45--73",
  month =        jan,
  year =         "1999",
  CODEN =        "FMSDE6",
  ISSN =         "0925-9856 (print), 1572-8102 (electronic)",
  ISSN-L =       "0925-9856",
  bibdate =      "Sat Jun 02 09:22:39 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Special issue on arithmetic circuits.",
  URL =          "http://www.wkap.nl/jrnltoc.htm/0925-9856;
                 http://www.wkap.nl/oasis.htm/194807",
  acknowledgement = ack-nhfb,
  fjournal =     "Formal Methods in System Design",
  journal-URL =  "https://dl.acm.org/loi/fmsd",
}


bibtype: article
filename: fparith.bib
label: Rugina:1999:APD
author: Radu Rugina and Martin Rinard
title: Automatic parallelization of divide and conquer algorithms
journal: j-SIGPLAN
volume: 34
number: 8
pages: 72--83
month: aug
monthnumber: 8
year: 1999
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:18:06 MST 2003
bibtimestamp: 2003.12.14 09:18:06 MST
URL: http://www.acm.org/pubs/citations/proceedings/ppopp/301104/p72-rugina/
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Radu Rugina and Martin Rinard
rawtitle: Automatic parallelization of divide and conquer algorithms
bibsource:
http://portal.acm.org/; http://www.acm.org/pubs/contents/proceedings/ppopp/301104/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Rugina:1999:APD,
  author =       "Radu Rugina and Martin Rinard",
  title =        "Automatic parallelization of divide and conquer
                 algorithms",
  journal =      j-SIGPLAN,
  volume =       "34",
  number =       "8",
  pages =        "72--83",
  month =        aug,
  year =         "1999",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:18:06 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 http://www.acm.org/pubs/contents/proceedings/ppopp/301104/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/citations/proceedings/ppopp/301104/p72-rugina/",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


bibtype: inproceedings
filename: fparith.bib
label: Rump:1999:IIL
author: Siegfried M. Rump
title: INTLAB--INTerval LABoratory
crossref: Csendes:1999:DRC
pages: 77--104
year: 1999
bibdate: Tue Nov 22 06:39:33 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.22 06:39:33 ???
keywords: accurate floating-point summation; interval arithmetic
acknowledgement: ack-nhfb
rawauthor: Siegfried M. Rump
rawtitle: {INTLAB--INTerval LABoratory}
entry:
@InProceedings{Rump:1999:IIL,
  author =       "Siegfried M. Rump",
  title =        "{INTLAB--INTerval LABoratory}",
  crossref =     "Csendes:1999:DRC",
  pages =        "77--104",
  year =         "1999",
  bibdate =      "Tue Nov 22 06:39:33 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; interval
                 arithmetic",
}


bibtype: article
filename: fparith.bib
label: Russinoff:1999:MCP
author: David M. Russinoff
title: A mechanically checked proof of correctness of the AMD K5 floating point square root microcode
journal: j-FORM-METHODS-SYST-DES
volume: 14
number: 1
pages: 75--125
month: jan
monthnumber: 1
year: 1999
CODEN: FMSDE6
DOI: https://doi.org/10.1023/A:1008669628911
ISSN: 0925-9856 (print), 1572-8102 (electronic) OR 09259856 (print), 15728102 (electronic)
ISSNL: 0925-9856 OR 09259856
bibdate: Sat Jun 02 07:51:51 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 07:51:51 ???
note: Special issue on arithmetic circuits.
fjournal: Formal Methods in System Design
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/fmsd
rawauthor: David M. Russinoff
rawnote: Special issue on arithmetic circuits.
rawtitle: A mechanically checked proof of correctness of the {AMD K5} floating point square root microcode
URL:
http://www.wkap.nl/jrnltoc.htm/0925-9856; http://www.wkap.nl/oasis.htm/194808; https://dl.acm.org/doi/abs/10.1023/A:1008669628911

abstract:
We present a rigorous mathematical proof of the correctness of the floating point square root instruction of the AMD K5 microprocessor. The instruction is represented as a program in a formal language that was designed for this purpose, based on the K5 microcode and the architecture of its FPU. We prove a statement of its correctness that corresponds directly with the IEEE Standard. We also derive an equivalent formulation, expressed in terms of rational arithmetic, which has been encoded as a formula in the ACL2 logic and mechanically verified with the ACL2 prover. Finally, we describe a microcode modification that was implemented as a result of this analysis in order to ensure the correctness of the instruction.

rawabstract:
We present a rigorous mathematical proof of the correctness of the floating point square root instruction of the AMD K5 microprocessor. The instruction is represented as a program in a formal language that was designed for this purpose, based on the K5 microcode and the architecture of its FPU. We prove a statement of its correctness that corresponds directly with the IEEE Standard. We also derive an equivalent formulation, expressed in terms of rational arithmetic, which has been encoded as a formula in the ACL2 logic and mechanically verified with the ACL2 prover. Finally, we describe a microcode modification that was implemented as a result of this analysis in order to ensure the correctness of the instruction.

entry:
@Article{Russinoff:1999:MCP,
  author =       "David M. Russinoff",
  title =        "A mechanically checked proof of correctness of the
                 {AMD K5} floating point square root microcode",
  journal =      j-FORM-METHODS-SYST-DES,
  volume =       "14",
  number =       "1",
  pages =        "75--125",
  month =        jan,
  year =         "1999",
  CODEN =        "FMSDE6",
  DOI =          "https://doi.org/10.1023/A:1008669628911",
  ISSN =         "0925-9856 (print), 1572-8102 (electronic)",
  ISSN-L =       "0925-9856",
  bibdate =      "Sat Jun 02 07:51:51 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Special issue on arithmetic circuits.",
  URL =          "http://www.wkap.nl/jrnltoc.htm/0925-9856;
                 http://www.wkap.nl/oasis.htm/194808;
                 https://dl.acm.org/doi/abs/10.1023/A:1008669628911",
  abstract =     "We present a rigorous mathematical proof of the
                 correctness of the floating point square root
                 instruction of the AMD K5 microprocessor. The
                 instruction is represented as a program in a formal
                 language that was designed for this purpose, based on
                 the K5 microcode and the architecture of its FPU. We
                 prove a statement of its correctness that corresponds
                 directly with the IEEE Standard. We also derive an
                 equivalent formulation, expressed in terms of rational
                 arithmetic, which has been encoded as a formula in the
                 ACL2 logic and mechanically verified with the ACL2
                 prover. Finally, we describe a microcode modification
                 that was implemented as a result of this analysis in
                 order to ensure the correctness of the instruction.",
  acknowledgement = ack-nhfb,
  fjournal =     "Formal Methods in System Design",
  journal-URL =  "https://dl.acm.org/loi/fmsd",
}


bibtype: inproceedings
filename: fparith.bib
label: Saed:1999:ASA
author: Aryan Saed and Majid Ahmadi and Graham A. Jullien
title: Arithmetic with Signed Analog Digits
crossref: Koren:1999:ISC
pages: 134--141
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Aryan Saed and Majid Ahmadi and Graham A. Jullien
rawtitle: Arithmetic with Signed Analog Digits
URL:
http://euler.ecs.umass.edu/paper/final/paper-140.pdf; http://euler.ecs.umass.edu/paper/final/paper-140.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Saed.pdf

abstract:
This paper presents mathematical foundations of the Overlap Resolution Number System (ORNS) which is based on signed Continuous Valued Digits (CVD's). ORNS is a redundant Number System employing residue arithmetic. In contrast to the implementation of arithmetic by binary or multiple-valued logic circuits, arithmetic operations in this novel number system are performed by analog digit manipulation circuitry. The redundancy in an ensemble of Continuous Valued Digits that comprises a number provides tolerance to implementation imprecisions. Processing with these analog digits is performed by carry-free arithmetic structures with systematic circuit level redundancy.

rawabstract:
This paper presents mathematical foundations of the Overlap Resolution Number System (ORNS) which is based on signed Continuous Valued Digits (CVD's). ORNS is a redundant Number System employing residue arithmetic. In contrast to the implementation of arithmetic by binary or multiple-valued logic circuits, arithmetic operations in this novel number system are performed by analog digit manipulation circuitry. The redundancy in an ensemble of Continuous Valued Digits that comprises a number provides tolerance to implementation imprecisions. Processing with these analog digits is performed by carry-free arithmetic structures with systematic circuit level redundancy.

entry:
@InProceedings{Saed:1999:ASA,
  author =       "Aryan Saed and Majid Ahmadi and Graham A. Jullien",
  title =        "Arithmetic with Signed Analog Digits",
  crossref =     "Koren:1999:ISC",
  pages =        "134--141",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-140.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-140.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Saed.pdf",
  abstract =     "This paper presents mathematical foundations of the
                 Overlap Resolution Number System (ORNS) which is based
                 on signed Continuous Valued Digits (CVD's). ORNS is a
                 redundant Number System employing residue arithmetic.
                 In contrast to the implementation of arithmetic by
                 binary or multiple-valued logic circuits, arithmetic
                 operations in this novel number system are performed by
                 analog digit manipulation circuitry. The redundancy in
                 an ensemble of Continuous Valued Digits that comprises
                 a number provides tolerance to implementation
                 imprecisions. Processing with these analog digits is
                 performed by carry-free arithmetic structures with
                 systematic circuit level redundancy.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: SanGregory:1999:FLP
author: Samuel L. SanGregory and Charles Brothers and David Gallagher and Raymond Siferd
editor: IEEE
title: A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 388--391
year: 1999
DOI: https://doi.org/10.1109/MWSCAS.1999.867287
LCCN: TK3226 .M531 42nd 1999
bibdate: Wed Dec 20 07:16:14 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:16:14 ???
URL: https://digitalcommons.cedarville.edu/engineering_and_computer_science_presentations/13
acknowledgement: ack-nhfb
bookpages: xl + 1150 (two volumes)
rawauthor: Samuel L. SanGregory and Charles Brothers and David Gallagher and Raymond Siferd
raweditor: {IEEE}
rawtitle: A Fast, Low-Power Logarithm Approximation with {CMOS VLSI} Implementation
booktitle:
Proceedings of 1999 Midwest Symposium on Circuits and Systems: August 8--12, 1999, Corbett Center, New Mexico State University, Las Cruces, New Mexico

ISBN:
0-7803-5491-5 (softbound), 0-7803-5492-3 (casebound), 0-7803-5493-1 (microfiche) OR 0780354915 (softbound), 0780354923 (casebound), 0780354931 (microfiche)

ISBN13:
978-0-7803-5491-3 (softbound), 978-0-7803-5492-0 (casebound), 978-0-7803-5493-7 (microfiche) OR 9780780354913 (softbound), 9780780354920 (casebound), 9780780354937 (microfiche)

abstract:
A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2 and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented, a ROM of only $ N times log _2 (N) $ bits is used to convert $N$ bit integers. The maximum error of the approximation is 1.5% when the input value is 3, and decays exponentially to less than 0.5% for input values greater than 25.

rawabstract:
A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2 and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented, a ROM of only $ N \times \log_2 (N) $ bits is used to convert $N$ bit integers. The maximum error of the approximation is 1.5\% when the input value is 3, and decays exponentially to less than 0.5\% for input values greater than 25.

rawbooktitle:
{Proceedings of 1999 Midwest Symposium on Circuits and Systems: August 8--12, 1999, Corbett Center, New Mexico State University, Las Cruces, New Mexico}

entry:
@InProceedings{SanGregory:1999:FLP,
  author =       "Samuel L. SanGregory and Charles Brothers and David
                 Gallagher and Raymond Siferd",
  editor =       "{IEEE}",
  booktitle =    "{Proceedings of 1999 Midwest Symposium on Circuits and
                 Systems: August 8--12, 1999, Corbett Center, New Mexico
                 State University, Las Cruces, New Mexico}",
  title =        "A Fast, Low-Power Logarithm Approximation with {CMOS
                 VLSI} Implementation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "xl + 1150 (two volumes)",
  pages =        "388--391",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/MWSCAS.1999.867287",
  ISBN =         "0-7803-5491-5 (softbound), 0-7803-5492-3 (casebound),
                 0-7803-5493-1 (microfiche)",
  ISBN-13 =      "978-0-7803-5491-3 (softbound), 978-0-7803-5492-0
                 (casebound), 978-0-7803-5493-7 (microfiche)",
  LCCN =         "TK3226 .M531 42nd 1999",
  bibdate =      "Wed Dec 20 07:16:14 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://digitalcommons.cedarville.edu/engineering_and_computer_science_presentations/13",
  abstract =     "A new technique and CMOS VLSI implementation for
                 computing approximate logarithms (base 2 and 10) for
                 binary integers is presented. The approximation is
                 performed using only combinational logic and requires
                 no multiplications. Additionally, as implemented, a ROM
                 of only $ N \times \log_2 (N) $ bits is used to convert
                 $N$ bit integers. The maximum error of the
                 approximation is 1.5\% when the input value is 3, and
                 decays exponentially to less than 0.5\% for input
                 values greater than 25.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Scherer:1999:OTW
title: An Out-of-Order Three-Way Superscalar Multimedia Floating-Point Unit
crossref: Wuorinen:1999:IIS
pages: ??--??
year: 1999
bibdate: Mon Jan 08 08:35:15 2001
bibsource: http://www.sscs.org/digests/1999/DATA/05_5.pdf; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.01.08 08:35:15 ???
keywords: AMD-K7 floating-point unit
acknowledgement: ack-nhfb
rawtitle: An Out-of-Order Three-Way Superscalar Multimedia Floating-Point Unit
author:
Alisa Scherer and Michael Golden and Norbert Juffa and Stephan Meier and Stuart Oberman and Hamid Partovi and Fred Weber

remark:
The AMD-K7 floating-point unit is implemented as an out-of-order coprocessor responsible for executing all x86 FPU, MMX, and AMD 3DNow! instructions.

rawauthor:
Alisa Scherer and Michael Golden and Norbert Juffa and Stephan Meier and Stuart Oberman and Hamid Partovi and Fred Weber

entry:
@InProceedings{Scherer:1999:OTW,
  author =       "Alisa Scherer and Michael Golden and Norbert Juffa and
                 Stephan Meier and Stuart Oberman and Hamid Partovi and
                 Fred Weber",
  title =        "An Out-of-Order Three-Way Superscalar Multimedia
                 Floating-Point Unit",
  crossref =     "Wuorinen:1999:IIS",
  pages =        "??--??",
  year =         "1999",
  bibdate =      "Mon Jan 08 08:35:15 2001",
  bibsource =    "http://www.sscs.org/digests/1999/DATA/05_5.pdf;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "AMD-K7 floating-point unit",
  pagecount =    "10",
  remark =       "The AMD-K7 floating-point unit is implemented as an
                 out-of-order coprocessor responsible for executing all
                 x86 FPU, MMX, and AMD 3DNow! instructions.",
}


bibtype: inproceedings
filename: fparith.bib
label: Schmookler:1999:LPH
title: A Low-Power, High-Speed Implementation of a PowerPC[TM] Microprocessor Vector Extension
crossref: Koren:1999:ISC
pages: 12--21
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawtitle: A Low-Power, High-Speed Implementation of a {PowerPC[TM]} Microprocessor Vector Extension
author:
Martin S. Schmookler and Michael Putrino and Charles Roth and Mukesh Sharma and Anh Mather and Jon Tyler and Huy Van Nguyen and Mydung N. Pham and Jeff Lent

URL:
http://euler.ecs.umass.edu/paper/final/paper-145.pdf; http://euler.ecs.umass.edu/paper/final/paper-145.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schmookler.pdf

abstract:
The AltiVecTM technology is an extension to the PowerPC architectureTM which provides new computational and storage operations for handling vectors of various data lengths and data types. The first implementation using this technology is a low cost, low power processor based on the acclaimed PowerPC 750TM microprocessor. This paper describes the microarchitecture and design of the vector arithmetic unit of this implementation.

rawabstract:
The AltiVec{\TM} technology is an extension to the PowerPC architecture{\TM} which provides new computational and storage operations for handling vectors of various data lengths and data types. The first implementation using this technology is a low cost, low power processor based on the acclaimed PowerPC 750{\TM} microprocessor. This paper describes the microarchitecture and design of the vector arithmetic unit of this implementation.

rawauthor:
Martin S. Schmookler and Michael Putrino and Charles Roth and Mukesh Sharma and Anh Mather and Jon Tyler and Huy Van Nguyen and Mydung N. Pham and Jeff Lent

entry:
@InProceedings{Schmookler:1999:LPH,
  author =       "Martin S. Schmookler and Michael Putrino and Charles
                 Roth and Mukesh Sharma and Anh Mather and Jon Tyler and
                 Huy Van Nguyen and Mydung N. Pham and Jeff Lent",
  title =        "A Low-Power, High-Speed Implementation of a
                 {PowerPC[TM]} Microprocessor Vector Extension",
  crossref =     "Koren:1999:ISC",
  pages =        "12--21",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-145.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-145.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schmookler.pdf",
  abstract =     "The AltiVec{\TM} technology is an extension to the
                 PowerPC architecture{\TM} which provides new
                 computational and storage operations for handling
                 vectors of various data lengths and data types. The
                 first implementation using this technology is a low
                 cost, low power processor based on the acclaimed
                 PowerPC 750{\TM} microprocessor. This paper describes
                 the microarchitecture and design of the vector
                 arithmetic unit of this implementation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Schulte:1999:AEF
author: M. Schulte and J. Stine
title: Approximating Elementary Functions with Symmetric Bipartite Tables
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 8
pages: 842--847
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.795125
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 24 20:20:58 2005
bibtimestamp: 2005.06.24 20:20:58 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-10.pdf
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Schulte and J. Stine
rawtitle: Approximating Elementary Functions with Symmetric Bipartite Tables
entry:
@Article{Schulte:1999:AEF,
  author =       "M. Schulte and J. Stine",
  title =        "Approximating Elementary Functions with Symmetric
                 Bipartite Tables",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "8",
  pages =        "842--847",
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.795125",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 24 20:20:58 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-10.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:CSI
author: M. J. Schulte and A. Akkas and V. Zelov and J. C. Burley
title: Compiler Support for Interval Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1189--1193
year: 1999
bibdate: Fri Jun 11 05:44:37 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.06.11 05:44:37 ???
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and A. Akkas and V. Zelov and J. C. Burley
rawtitle: Compiler Support for Interval Arithmetic
booktitle:
Proceedings of 16th IEEE Instrumentation and Measurement Technology Conference, Venice, Italy, May, 1999

URL:
http://home.ku.edu.tr/~ahakkas/publications/comp-supp.pdf; http://mesa.ece.wisc.edu/publications/cp_1999-04.pdf

rawbooktitle:
Proceedings of {16th IEEE Instrumentation and Measurement Technology Conference, Venice, Italy, May, 1999}

entry:
@InProceedings{Schulte:1999:CSI,
  author =       "M. J. Schulte and A. Akkas and V. Zelov and J. C.
                 Burley",
  booktitle =    "Proceedings of {16th IEEE Instrumentation and
                 Measurement Technology Conference, Venice, Italy, May,
                 1999}",
  title =        "Compiler Support for Interval Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1189--1193",
  year =         "1999",
  bibdate =      "Fri Jun 11 05:44:37 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://home.ku.edu.tr/~ahakkas/publications/comp-supp.pdf;
                 http://mesa.ece.wisc.edu/publications/cp_1999-04.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:ESO
author: M. J. Schulte and K. E. Wires
title: Efficient Second Order Approximations for Reciprocals and Square Roots
crossref: Luk:1999:PSA
volume: 3807
pages: 10--18
year: 1999
bibdate: Sun Mar 04 11:10:48 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:10:48 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-05.pdf
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and K. E. Wires
rawtitle: Efficient Second Order Approximations for Reciprocals and Square Roots
entry:
@InProceedings{Schulte:1999:ESO,
  author =       "M. J. Schulte and K. E. Wires",
  title =        "Efficient Second Order Approximations for Reciprocals
                 and Square Roots",
  crossref =     "Luk:1999:PSA",
  volume =       "3807",
  pages =        "10--18",
  year =         "1999",
  bibdate =      "Sun Mar 04 11:10:48 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-05.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:HSI
author: Michael J. Schulte and Kent E. Wires
title: High-Speed Inverse Square Roots
crossref: Koren:1999:ISC
pages: 124--131
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Michael J. Schulte and Kent E. Wires
rawtitle: High-Speed Inverse Square Roots
URL:
http://euler.ecs.umass.edu/paper/final/paper-109.pdf; http://euler.ecs.umass.edu/paper/final/paper-109.ps; http://mesa.ece.wisc.edu/publications/cp_1999-03.pdf; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schulte.pdf

abstract:
Inverse square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents a high-speed method for computing inverse square roots. This method uses a table lookup, operand modification, and multiplication to obtain an initial approximation to the inverse square root. This is followed by a modified Newton--Raphson iteration, consisting of one square, one multiply-complement, and one multiply-add operation. The initial approximation and Newton--Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. Application of this method is illustrated through the design of an inverse square root unit for operands in the IEEE single precision format. An implementation of this unit with a 4-layer metal, 2.5 Volt, 0.25 micron CMOS standard cell library has a cycle time of 6.7 ns, an area of 0.41 mm$^2$, a latency of five cycles, and a throughput of one result per cycle.

rawabstract:
Inverse square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents a high-speed method for computing inverse square roots. This method uses a table lookup, operand modification, and multiplication to obtain an initial approximation to the inverse square root. This is followed by a modified Newton--Raphson iteration, consisting of one square, one multiply-complement, and one multiply-add operation. The initial approximation and Newton--Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. Application of this method is illustrated through the design of an inverse square root unit for operands in the IEEE single precision format. An implementation of this unit with a 4-layer metal, 2.5 Volt, 0.25 micron CMOS standard cell library has a cycle time of 6.7 ns, an area of 0.41 mm$^2$, a latency of five cycles, and a throughput of one result per cycle.

entry:
@InProceedings{Schulte:1999:HSI,
  author =       "Michael J. Schulte and Kent E. Wires",
  title =        "High-Speed Inverse Square Roots",
  crossref =     "Koren:1999:ISC",
  pages =        "124--131",
  year =         "1999",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-109.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-109.ps;
                 http://mesa.ece.wisc.edu/publications/cp_1999-03.pdf;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schulte.pdf",
  abstract =     "Inverse square roots are used in several digital
                 signal processing, multimedia, and scientific computing
                 applications. This paper presents a high-speed method
                 for computing inverse square roots. This method uses a
                 table lookup, operand modification, and multiplication
                 to obtain an initial approximation to the inverse
                 square root. This is followed by a modified
                 Newton--Raphson iteration, consisting of one square,
                 one multiply-complement, and one multiply-add
                 operation. The initial approximation and
                 Newton--Raphson iteration employ specialized hardware
                 to reduce the delay, area, and power dissipation.
                 Application of this method is illustrated through the
                 design of an inverse square root unit for operands in
                 the IEEE single precision format. An implementation of
                 this unit with a 4-layer metal, 2.5 Volt, 0.25 micron
                 CMOS standard cell library has a cycle time of 6.7 ns,
                 an area of 0.41 mm$^2$, a latency of five cycles, and a
                 throughput of one result per cycle.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
  summary =      "Inverse square roots are used in several digital
                 signal processing, multimedia, and scientific computing
                 applications. This paper presents a high-speed method
                 for computing inverse square roots. This method uses a
                 table lookup, operand modification, \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:IEG
author: M. J. Schulte and V. A. Zelov and A. Akkas and J. C. Burley
title: The interval-enhanced GNU Fortran compiler
crossref: Csendes:1999:DRC
pages: 311--322
year: 1999
bibdate: Wed Jan 29 16:56:25 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.01.29 16:56:25 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-12.pdf
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and V. A. Zelov and A. Akkas and J. C. Burley
rawtitle: The interval-enhanced {GNU Fortran} compiler
remark:
From cite Steele:2004:RHP: ``A recent extension of the GNU Fortran compiler makes use of accurate conversion techniques.''

entry:
@InProceedings{Schulte:1999:IEG,
  author =       "M. J. Schulte and V. A. Zelov and A. Akkas and J. C.
                 Burley",
  title =        "The interval-enhanced {GNU Fortran} compiler",
  crossref =     "Csendes:1999:DRC",
  pages =        "311--322",
  year =         "1999",
  bibdate =      "Wed Jan 29 16:56:25 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-12.pdf",
  acknowledgement = ack-nhfb,
  remark =       "From \cite{Steele:2004:RHP}: ``A recent extension of
                 the GNU Fortran compiler makes use of accurate
                 conversion techniques.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:RPD
author: M. J. Schulte and J. G. Jansen and J. E. Stine
title: Reduced Power Dissipation Through Truncated Multiplication
crossref: Piuri:1999:IAV
pages: 61--69
year: 1999
bibdate: Sun Mar 04 11:16:43 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:16:43 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-01.pdf
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and J. G. Jansen and J. E. Stine
rawtitle: Reduced Power Dissipation Through Truncated Multiplication
entry:
@InProceedings{Schulte:1999:RPD,
  author =       "M. J. Schulte and J. G. Jansen and J. E. Stine",
  title =        "Reduced Power Dissipation Through Truncated
                 Multiplication",
  crossref =     "Piuri:1999:IAV",
  pages =        "61--69",
  year =         "1999",
  bibdate =      "Sun Mar 04 11:16:43 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-01.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schwarz:1999:GFPa
author: Eric M. Schwarz and Ronald M. Smith and Christopher A. Krygowski
title: The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures
crossref: Koren:1999:ISC
pages: 258--265
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Eric M. Schwarz and Ronald M. Smith and Christopher A. Krygowski
rawtitle: The {S/390 G5} Floating Point Unit Supporting Hex and Binary Architectures
URL:
http://computer.org/proceedings/arith/0116/0116toc.htm; http://euler.ecs.umass.edu/paper/final/paper-112.pdf; http://euler.ecs.umass.edu/paper/final/paper-112.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schwarz.pdf

abstract:
The first high performance floating point unit to support both IBM 360 hexadecimal based floating point architecture and the IEEE 754 Standard binary floating point architecture is described. The S/390 G5 floating point unit supports the new S/390 architecture which includes hexadecimal based short, long, and extended precision formats and IEEE 754 standard single, double, and quad formats. This floating point unit is part of the microprocessor chip on the S/390 G5 mainframe computer introduced in 1998 and generally available at 500 MHz speeds. The S/390 G5 represents the current state of the art in CISC processor design. This paper describes the S/390 architecture enhancements, the internal format of the FPU, and the modifications to the FPU dataflow.

rawabstract:
The first high performance floating point unit to support both IBM 360 hexadecimal based floating point architecture and the IEEE 754 Standard binary floating point architecture is described. The S/390 G5 floating point unit supports the new S/390 architecture which includes hexadecimal based short, long, and extended precision formats and IEEE 754 standard single, double, and quad formats. This floating point unit is part of the microprocessor chip on the S/390 G5 mainframe computer introduced in 1998 and generally available at 500 MHz speeds. The S/390 G5 represents the current state of the art in CISC processor design. This paper describes the S/390 architecture enhancements, the internal format of the FPU, and the modifications to the FPU dataflow.

entry:
@InProceedings{Schwarz:1999:GFPa,
  author =       "Eric M. Schwarz and Ronald M. Smith and Christopher A.
                 Krygowski",
  title =        "The {S/390 G5} Floating Point Unit Supporting Hex and
                 Binary Architectures",
  crossref =     "Koren:1999:ISC",
  pages =        "258--265",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://computer.org/proceedings/arith/0116/0116toc.htm;
                 http://euler.ecs.umass.edu/paper/final/paper-112.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-112.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schwarz.pdf",
  abstract =     "The first high performance floating point unit to
                 support both IBM 360 hexadecimal based floating point
                 architecture and the IEEE 754 Standard binary floating
                 point architecture is described. The S/390 G5 floating
                 point unit supports the new S/390 architecture which
                 includes hexadecimal based short, long, and extended
                 precision formats and IEEE 754 standard single, double,
                 and quad formats. This floating point unit is part of
                 the microprocessor chip on the S/390 G5 mainframe
                 computer introduced in 1998 and generally available at
                 500 MHz speeds. The S/390 G5 represents the current
                 state of the art in CISC processor design. This paper
                 describes the S/390 architecture enhancements, the
                 internal format of the FPU, and the modifications to
                 the FPU dataflow.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Schwarz:1999:GFPb
author: E. M. Schwarz and C. A. Krygowski
title: The S/390 G5 floating-point unit
journal: j-IBM-JRD
volume: 43
number: 5/6
pages: 707--721
month: sep
monthnumber: 9
year: 1999
CODEN: IBMJAE
DOI: https://doi.org/10.1147/rd.435.0707
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Wed Apr 19 18:58:23 MDT 2000
bibtimestamp: 2000.04.19 18:58:23 MDT
URL: http://www.research.ibm.com/journal/rd/435/schwarz.html
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: E. M. Schwarz and C. A. Krygowski
rawtitle: The {S/390 G5} floating-point unit
entry:
@Article{Schwarz:1999:GFPb,
  author =       "E. M. Schwarz and C. A. Krygowski",
  title =        "The {S/390 G5} floating-point unit",
  journal =      j-IBM-JRD,
  volume =       "43",
  number =       "5/6",
  pages =        "707--721",
  month =        sep # "\slash " # nov,
  year =         "1999",
  CODEN =        "IBMJAE",
  DOI =          "https://doi.org/10.1147/rd.435.0707",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Apr 19 18:58:23 MDT 2000",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ibmjrd.bib",
  URL =          "http://www.research.ibm.com/journal/rd/435/schwarz.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
}


bibtype: misc
filename: fparith.bib
label: Schwarz:1999:MSE
author: E. M. Schwarz and B. Giamei and C. Krygowski and M. Check and J. Liptay
title: Method and system for executing denormalized numbers
pages: 707--721
day: 11
month: may
monthnumber: 5
year: 1999
bibdate: Fri Nov 28 15:29:52 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 15:29:52 ???
note: U.S. Patent No. 5,903,479.
acknowledgement: ack-nhfb
rawauthor: E. M. Schwarz and B. Giamei and C. Krygowski and M. Check and J. Liptay
rawnote: U.S. Patent No. 5,903,479.
rawtitle: Method and system for executing denormalized numbers
entry:
@Misc{Schwarz:1999:MSE,
  author =       "E. M. Schwarz and B. Giamei and C. Krygowski and M.
                 Check and J. Liptay",
  title =        "Method and system for executing denormalized numbers",
  day =          "11",
  month =        may,
  year =         "1999",
  bibdate =      "Fri Nov 28 15:29:52 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "U.S. Patent No. 5,903,479.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Seidel:1999:HSR
author: Peter-Michael Seidel
title: High-Speed Redundant Reciprocal Approximation
journal: j-INTEGRATION-VLSI-J
volume: 28
number: 1
pages: 1--12
month: sep
monthnumber: 9
year: 1999
CODEN: IVJODL
DOI: https://doi.org/10.1016/S0167-9260(99)00008-5
ISSN: 0167-9260 (print), 1872-7522 (electronic) OR 01679260 (print), 18727522 (electronic)
ISSNL: 0167-9260 OR 01679260
bibdate: Fri Jun 24 20:25:43 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 20:25:43 ???
fjournal: Integration, the VLSI journal
acknowledgement: ack-nhfb
rawauthor: Peter-Michael Seidel
rawtitle: High-Speed Redundant Reciprocal Approximation
abstract:
This paper presents a fast implementation for reciprocal approximation, that can compute a redundant reciprocal of a normalized number with a precision of $ 2^-28 $ in roughly 16--17 logic levels. Moreover, a less accurate, but much cheaper implementation is proposed. The redundant representation of the reciprocal can directly be fed into a common Booth multiplier. This allows to implement IEEE floating-point division with correct rounding in all rounding modes with a latency of 7 clock cycles in double precision and 4 clock cycles in single precision. We also consider fast redundant compressions from carry-save representations to redundant Booth-digit representations.

keywords:
Booth recoding; correct rounding; floating-point arithmetic; Multiplicative division; Reciprocal approximation; Redundant compression

rawabstract:
This paper presents a fast implementation for reciprocal approximation, that can compute a redundant reciprocal of a normalized number with a precision of $ 2^-28 $ in roughly 16--17 logic levels. Moreover, a less accurate, but much cheaper implementation is proposed. The redundant representation of the reciprocal can directly be fed into a common Booth multiplier. This allows to implement IEEE floating-point division with correct rounding in all rounding modes with a latency of 7 clock cycles in double precision and 4 clock cycles in single precision. We also consider fast redundant compressions from carry-save representations to redundant Booth-digit representations.

entry:
@Article{Seidel:1999:HSR,
  author =       "Peter-Michael Seidel",
  title =        "High-Speed Redundant Reciprocal Approximation",
  journal =      j-INTEGRATION-VLSI-J,
  volume =       "28",
  number =       "1",
  pages =        "1--12",
  month =        sep,
  year =         "1999",
  CODEN =        "IVJODL",
  DOI =          "https://doi.org/10.1016/S0167-9260(99)00008-5",
  ISSN =         "0167-9260 (print), 1872-7522 (electronic)",
  ISSN-L =       "0167-9260",
  bibdate =      "Fri Jun 24 20:25:43 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a fast implementation for
                 reciprocal approximation, that can compute a redundant
                 reciprocal of a normalized number with a precision of $
                 2^-28 $ in roughly 16--17 logic levels. Moreover, a
                 less accurate, but much cheaper implementation is
                 proposed. The redundant representation of the
                 reciprocal can directly be fed into a common Booth
                 multiplier. This allows to implement IEEE
                 floating-point division with correct rounding in all
                 rounding modes with a latency of 7 clock cycles in
                 double precision and 4 clock cycles in single
                 precision. We also consider fast redundant compressions
                 from carry-save representations to redundant
                 Booth-digit representations.",
  acknowledgement = ack-nhfb,
  fjournal =     "Integration, the VLSI journal",
  keywords =     "Booth recoding; correct rounding; floating-point
                 arithmetic; Multiplicative division; Reciprocal
                 approximation; Redundant compression",
}


bibtype: article
filename: fparith.bib
label: Shary:1999:OEG
author: S. P. Shary
title: Outer Estimation of Generalized Solution Sets to Interval Linear Systems
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 323--335
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: S. P. Shary
rawtitle: Outer Estimation of Generalized Solution Sets to Interval Linear Systems
entry:
@Article{Shary:1999:OEG,
  author =       "S. P. Shary",
  title =        "Outer Estimation of Generalized Solution Sets to
                 Interval Linear Systems",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "323--335",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: inproceedings
filename: fparith.bib
label: Skavantzos:1999:GMR
author: A. Skavantzos and T. Stouraitis
title: Grouped-moduli residue number systems for fast signal processing
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 478--483
year: 1999
DOI: https://doi.org/10.1109/ISCAS.1999.778887
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Skavantzos and T. Stouraitis
rawtitle: Grouped-moduli residue number systems for fast signal processing
booktitle:
ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 2 June 1999

rawbooktitle:
{ISCAS '99}. Proceedings of the 1999 {IEEE} International Symposium on Circuits and Systems, 2 June 1999

entry:
@InProceedings{Skavantzos:1999:GMR,
  author =       "A. Skavantzos and T. Stouraitis",
  booktitle =    "{ISCAS '99}. Proceedings of the 1999 {IEEE}
                 International Symposium on Circuits and Systems, 2 June
                 1999",
  title =        "Grouped-moduli residue number systems for fast signal
                 processing",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "478--483",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1999.778887",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "In this paper a new class of multi-moduli residue
                 number systems (RNS) and their efficient
                 RNS-to-weighted converters are presented. The new RNS
                 systems are based on sets consisting of two groups of
                 moduli with the moduli-product within one group
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Skavantzos:1999:IIT
author: A. Skavantzos and M. Abdallah
title: Implementation issues of the two-level residue number system with pairs of conjugate moduli
journal: j-IEEE-TRANS-SIG-PROC
volume: 47
number: 3
pages: 826--838
month: mar
monthnumber: 3
year: 1999
CODEN: ITPRED
DOI: https://doi.org/10.1109/78.747787
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=16138
fjournal: IEEE Transactions on Signal Processing
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: A. Skavantzos and M. Abdallah
rawtitle: Implementation issues of the two-level residue number system with pairs of conjugate moduli
entry:
@Article{Skavantzos:1999:IIT,
  author =       "A. Skavantzos and M. Abdallah",
  title =        "Implementation issues of the two-level residue number
                 system with pairs of conjugate moduli",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "47",
  number =       "3",
  pages =        "826--838",
  month =        mar,
  year =         "1999",
  CODEN =        "ITPRED",
  DOI =          "https://doi.org/10.1109/78.747787",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=16138",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  keywords =     "residue arithmetic; residue number system",
  summary =      "One of the most important considerations when
                 designing residue number systems (RNSs) is the choice
                 of the moduli set; this is due to the fact that the
                 dynamic range of the system, its speed, as well as its
                 hardware complexity, depend on both the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Skavantzos:1999:NER
author: A. Skavantzos and Y. Wang
booktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
title: New efficient RNS-to-weighted decoders for conjugate-pair-moduli residue number systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1345--1350
year: 1999
DOI: https://doi.org/10.1109/ACSSC.1999.831926
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Skavantzos and Y. Wang
rawbooktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
rawtitle: New efficient {RNS}-to-weighted decoders for conjugate-pair-moduli residue number systems
entry:
@InProceedings{Skavantzos:1999:NER,
  author =       "A. Skavantzos and Y. Wang",
  booktitle =    "Conference Record of the Thirty-Third Asilomar
                 Conference on Signals, Systems, and Computers, 1999",
  title =        "New efficient {RNS}-to-weighted decoders for
                 conjugate-pair-moduli residue number systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1345--1350",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ACSSC.1999.831926",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "New efficient residue-to-weighted converters for
                 multi-moduli residue number systems (RNS) based on sets
                 {2 n1 -1, 2 n1 +1, 2 n2 -1, 2 n2 +1, {\ldots}, 2 nL -1,
                 2 nL +1} are presented. The \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Skeel:1999:SIF
author: R. D. Skeel
title: Symplectic integration with floating-point arithmetic and other approximations
journal: j-APPL-NUM-MATH
volume: 29
number: 1
publisher: Elsevier Science
pages: 3--18
month: jan
monthnumber: 1
year: 1999
CODEN: ANMAEL
ISSN: 0168-9274 (print), 1873-5460 (electronic) OR 01689274 (print), 18735460 (electronic)
ISSNL: 0168-9274 OR 01689274
bibdate: Fri Nov 8 05:39:32 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.11.08 05:39:32 MST
fjournal: Applied Numerical Mathematics: Transactions of IMACS
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01689274
rawauthor: R. D. Skeel
rawtitle: Symplectic integration with floating-point arithmetic and other approximations
entry:
@Article{Skeel:1999:SIF,
  author =       "R. D. Skeel",
  title =        "Symplectic integration with floating-point arithmetic
                 and other approximations",
  journal =      j-APPL-NUM-MATH,
  volume =       "29",
  number =       "1",
  publisher =    "Elsevier Science",
  pages =        "3--18",
  month =        jan,
  year =         "1999",
  CODEN =        "ANMAEL",
  ISSN =         "0168-9274 (print), 1873-5460 (electronic)",
  ISSN-L =       "0168-9274",
  bibdate =      "Fri Nov 8 05:39:32 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Numerical Mathematics: Transactions of IMACS",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01689274",
  pagecount =    "16",
}


bibtype: article
filename: fparith.bib
label: Stine:1999:STA
author: J. E. Stine and M. J. Schulte
title: The Symmetric Table Addition Method for Accurate Function Approximation
journal: j-J-VLSI-SIGNAL-PROC
volume: 21
number: 2
pages: 167--177
month: jun
monthnumber: 6
year: 1999
CODEN: JVSPED
DOI: https://doi.org/10.1023/A:1008004523235
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Sun Mar 04 11:02:59 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:02:59 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-11.pdf
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: J. E. Stine and M. J. Schulte
rawtitle: The Symmetric Table Addition Method for Accurate Function Approximation
abstract:
This paper presents a high-speed method for computing elementary functions using parallel table lookups and multi-operand addition. Increasing the number of tables and inputs to the multi-operand adder significantly reduces the amount of memory required. Symmetry and leading zeros in the table coefficients are used to reduce the amount of memory even further. This method has a closed-form solution for the table entries and can be applied to any differentiable function. For 24-bit operands, it requires two to three orders of magn

rawabstract:
This paper presents a high-speed method for computing elementary functions using parallel table lookups and multi-operand addition. Increasing the number of tables and inputs to the multi-operand adder significantly reduces the amount of memory required. Symmetry and leading zeros in the table coefficients are used to reduce the amount of memory even further. This method has a closed-form solution for the table entries and can be applied to any differentiable function. For 24-bit operands, it requires two to three orders of magn

entry:
@Article{Stine:1999:STA,
  author =       "J. E. Stine and M. J. Schulte",
  title =        "The Symmetric Table Addition Method for Accurate
                 Function Approximation",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "21",
  number =       "2",
  pages =        "167--177",
  month =        jun,
  year =         "1999",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1023/A:1008004523235",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Sun Mar 04 11:02:59 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-11.pdf",
  abstract =     "This paper presents a high-speed method for computing
                 elementary functions using parallel table lookups and
                 multi-operand addition. Increasing the number of tables
                 and inputs to the multi-operand adder significantly
                 reduces the amount of memory required. Symmetry and
                 leading zeros in the table coefficients are used to
                 reduce the amount of memory even further. This method
                 has a closed-form solution for the table entries and
                 can be applied to any differentiable function. For
                 24-bit operands, it requires two to three orders of
                 magn",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Story:1999:NAI
author: Shane Story and Ping Tak Peter Tang
title: New Algorithms for Improved Transcendental Functions on IA-64
crossref: Koren:1999:ISC
pages: 4--11
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Shane Story and Ping Tak Peter Tang
rawtitle: New Algorithms for Improved Transcendental Functions on {IA-64}
URL:
http://euler.ecs.umass.edu/paper/final/paper-118.pdf; http://euler.ecs.umass.edu/paper/final/paper-118.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Story.pdf

abstract:
The IA-64 architecture provides new opportunities and challenges for implementing an improved set of transcendental functions. Using several novel polynomial-based table-driven techniques, we are able to provide new algorithms for the transcendental functions. Major improvements include an accuracy level of about 0.6 ulps (units in the last place) and forward trigonometric functions that have a period of $ 2 pi $. The accuracy enhancements are achieved at improved speed, yet without an increase in the table size. In this paper, we highlight the key IA-64 architectural features that influenced our designs and explain the main ideas used in our new algorithms.

rawabstract:
The IA-64 architecture provides new opportunities and challenges for implementing an improved set of transcendental functions. Using several novel polynomial-based table-driven techniques, we are able to provide new algorithms for the transcendental functions. Major improvements include an accuracy level of about 0.6 ulps (units in the last place) and forward trigonometric functions that have a period of $ 2 \pi $. The accuracy enhancements are achieved at improved speed, yet without an increase in the table size. In this paper, we highlight the key IA-64 architectural features that influenced our designs and explain the main ideas used in our new algorithms.

entry:
@InProceedings{Story:1999:NAI,
  author =       "Shane Story and Ping Tak Peter Tang",
  title =        "New Algorithms for Improved Transcendental Functions
                 on {IA-64}",
  crossref =     "Koren:1999:ISC",
  pages =        "4--11",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-118.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-118.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Story.pdf",
  abstract =     "The IA-64 architecture provides new opportunities and
                 challenges for implementing an improved set of
                 transcendental functions. Using several novel
                 polynomial-based table-driven techniques, we are able
                 to provide new algorithms for the transcendental
                 functions. Major improvements include an accuracy level
                 of about 0.6 ulps (units in the last place) and forward
                 trigonometric functions that have a period of $ 2 \pi
                 $. The accuracy enhancements are achieved at improved
                 speed, yet without an increase in the table size. In
                 this paper, we highlight the key IA-64 architectural
                 features that influenced our designs and explain the
                 main ideas used in our new algorithms.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Strzebonski:1999:RPD
author: A. Strzebonski
title: A Real Polynomial Decision Algorithm Using Arbitrary-Precision Floating Point Arithmetic
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 337--346
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: A. Strzebonski
rawtitle: A Real Polynomial Decision Algorithm Using Arbitrary-Precision Floating Point Arithmetic
entry:
@Article{Strzebonski:1999:RPD,
  author =       "A. Strzebonski",
  title =        "A Real Polynomial Decision Algorithm Using
                 Arbitrary-Precision Floating Point Arithmetic",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "337--346",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: article
filename: fparith.bib
label: Sunar:1999:MMA
author: B. Sunar and C. K. Koc
title: Mastrovito multiplier for all trinomials
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 5
pages: 522--527
month: may
monthnumber: 5
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.769434
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 24 21:18:53 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 21:18:53 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: B. Sunar and {\c{C}}. K. Ko{\c{c}}
rawtitle: {Mastrovito} multiplier for all trinomials
entry:
@Article{Sunar:1999:MMA,
  author =       "B. Sunar and {\c{C}}. K. Ko{\c{c}}",
  title =        "{Mastrovito} multiplier for all trinomials",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "5",
  pages =        "522--527",
  month =        may,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.769434",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 24 21:18:53 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: book
filename: fparith.bib
label: Sutherland:1999:LEDk
author: Ivan Sutherland and Bob Sproull and David Harris
title: Logical Effort: Designing Fast CMOS Circuits
publisher: pub-MORGAN-KAUFMANN
address: pub-MORGAN-KAUFMANN:adr
pages: xv + 239
year: 1999
ISBN: 1-55860-557-6 OR 1558605576
ISBN13: 978-1-55860-557-2 OR 9781558605572
LCCN: TK7871.99.M44 S88 1999
bibdate: Thu Sep 21 17:07:13 MDT 2023
bibsource: fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 17:07:13 MDT
acknowledgement: ack-nhfb
rawauthor: Ivan Sutherland and Bob Sproull and David Harris
rawtitle: Logical Effort: Designing Fast {CMOS} Circuits
subject:
circuiti elettronici CMOS; circuiti integrati CMOS; circuiti logici; CMOS (Circuit integre); CMOS-Schaltung; Complementary; Conception et construction; Delay faults (Semiconductors); Design and construction; Dispositifs logiques; Logic design; Logic devices; Logischer Entwurf; Metal oxide semiconductors, Complementary; Metal oxide semiconductors; MOS complementaires; Pannes temporelles (Semi-conducteurs); Progettazione Schaltungsentwurf; Semiconductores; Structure logique; Transistores MOS complementarios

TOC:
1. The Method of Logical Effort 2. Design Examples 3. Deriving the Method of Logical Effort 4. Calculating the Logical Effort of Gates 5. Calibrating the Model 6. Asymmetric Logic Gates 7. Unequal Rising and Falling Delays 8. Circuit Families 9. Forks of Amplifiers 10. Branches and Interconnect 11. Wide Structures 12. Conclusions App. A. Cast of Characters App. B. Reference Process Parameters App. C. Solutions to Selected Exercises

rawTOC:
1. The Method of Logical Effort \\ 2. Design Examples \\ 3. Deriving the Method of Logical Effort \\ 4. Calculating the Logical Effort of Gates \\ 5. Calibrating the Model \\ 6. Asymmetric Logic Gates \\ 7. Unequal Rising and Falling Delays \\ 8. Circuit Families \\ 9. Forks of Amplifiers \\ 10. Branches and Interconnect \\ 11. Wide Structures \\ 12. Conclusions \\ App. A. Cast of Characters \\ App. B. Reference Process Parameters \\ App. C. Solutions to Selected Exercises

entry:
@Book{Sutherland:1999:LEDk,
  author =       "Ivan Sutherland and Bob Sproull and David Harris",
  title =        "Logical Effort: Designing Fast {CMOS} Circuits",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xv + 239",
  year =         "1999",
  ISBN =         "1-55860-557-6",
  ISBN-13 =      "978-1-55860-557-2",
  LCCN =         "TK7871.99.M44 S88 1999",
  bibdate =      "Thu Sep 21 17:07:13 MDT 2023",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  subject =      "circuiti elettronici CMOS; circuiti integrati CMOS;
                 circuiti logici; CMOS (Circuit int{\'e}gr{\'e});
                 CMOS-Schaltung; Complementary; Conception et
                 construction; Delay faults (Semiconductors); Design and
                 construction; Dispositifs logiques; Logic design; Logic
                 devices; Logischer Entwurf; Metal oxide semiconductors,
                 Complementary; Metal oxide semiconductors; MOS
                 compl{\'e}mentaires; Pannes temporelles
                 (Semi-conducteurs); Progettazione Schaltungsentwurf;
                 Semiconductores; Structure logique; Transistores MOS
                 complementarios",
  tableofcontents = "1. The Method of Logical Effort \\
                 2. Design Examples \\
                 3. Deriving the Method of Logical Effort \\
                 4. Calculating the Logical Effort of Gates \\
                 5. Calibrating the Model \\
                 6. Asymmetric Logic Gates \\
                 7. Unequal Rising and Falling Delays \\
                 8. Circuit Families \\
                 9. Forks of Amplifiers \\
                 10. Branches and Interconnect \\
                 11. Wide Structures \\
                 12. Conclusions \\
                 App. A. Cast of Characters \\
                 App. B. Reference Process Parameters \\
                 App. C. Solutions to Selected Exercises",
}


bibtype: article
filename: fparith.bib
label: Suzuoki:1999:MBC
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 34
number: 11
pages: 1608--1618
month: nov
monthnumber: 11
year: 1999
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
author:
M. Suzuoki and K. Kutaragi and T. Hiroi and H. Magoshi and S. Okamoto and M. Oka and A. Ohba and Y. Yamamoto and M. Furuhashi and M. Tanaka and T. Yutaka and T. Okada and M. Nagamatsu and Y. Urakawa and M. Funyu and A. Kunimatsu and H. Goto and K. Hashimoto and N. Ide and H. Murakami and Y. Ohtaguro and A. Aono

title:
A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder

rawauthor:
M. Suzuoki and K. Kutaragi and T. Hiroi and H. Magoshi and S. Okamoto and M. Oka and A. Ohba and Y. Yamamoto and M. Furuhashi and M. Tanaka and T. Yutaka and T. Okada and M. Nagamatsu and Y. Urakawa and M. Funyu and A. Kunimatsu and H. Goto and K. Hashimoto and N. Ide and H. Murakami and Y. Ohtaguro and A. Aono

rawtitle:
A microprocessor with a 128-bit {CPU}, ten floating-point {MAC}'s, four floating-point dividers, and an {MPEG-2} decoder

entry:
@Article{Suzuoki:1999:MBC,
  author =       "M. Suzuoki and K. Kutaragi and T. Hiroi and H. Magoshi
                 and S. Okamoto and M. Oka and A. Ohba and Y. Yamamoto
                 and M. Furuhashi and M. Tanaka and T. Yutaka and T.
                 Okada and M. Nagamatsu and Y. Urakawa and M. Funyu and
                 A. Kunimatsu and H. Goto and K. Hashimoto and N. Ide
                 and H. Murakami and Y. Ohtaguro and A. Aono",
  title =        "A microprocessor with a 128-bit {CPU}, ten
                 floating-point {MAC}'s, four floating-point dividers,
                 and an {MPEG-2} decoder",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "34",
  number =       "11",
  pages =        "1608--1618",
  month =        nov,
  year =         "1999",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "A 250-MHz microprocessor intended for home computer
                 entertainment consists of a CPU core with 128-b
                 multimedia extensions, two single-instruction,
                 multiple-data (SIMD) very long instruction word (VLIW)
                 vector processors containing ten floating-point
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Swartzlander:1999:TMA
author: E. E. Swartzlander, Jr.
booktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
title: Truncated multiplication with approximate rounding
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1480--1483
year: 1999
bibdate: Sat Jul 16 11:25:05 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:05 MDT
acknowledgement: ack-nhfb
rawauthor: E. E. {Swartzlander, Jr.}
rawbooktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
rawtitle: Truncated multiplication with approximate rounding
entry:
@InProceedings{Swartzlander:1999:TMA,
  author =       "E. E. {Swartzlander, Jr.}",
  booktitle =    "Conference Record of the Thirty-Third Asilomar
                 Conference on Signals, Systems, and Computers, 1999",
  title =        "Truncated multiplication with approximate rounding",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1480--1483",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:05 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "In many signal processing applications it is desirable
                 to maintain constant word size through the basic
                 arithmetic operations of add, subtract, multiply and
                 divide. Of these operations, multiply is the biggest
                 concern as multiplying two n-bit data \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:1999:DRA
author: Naofumi Takagi and Seiji Kuwahara
title: Digit-Recurrence Algorithm for Computing Euclidean Norm of a $3$-D Vector
crossref: Koren:1999:ISC
pages: 86--95
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Naofumi Takagi and Seiji Kuwahara
rawtitle: Digit-Recurrence Algorithm for Computing {Euclidean} Norm of a {$3$-D} Vector
URL:
http://euler.ecs.umass.edu/paper/final/paper-142.pdf; http://euler.ecs.umass.edu/paper/final/paper-142.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Takagi.pdf

abstract:
A digit-recurrence algorithm for computing the Euclidean norm of a 3-dimensional vector is proposed. Starting from the vector component with the highest order of magnitude as the initial value of partial result, correcting-digits produced by the recurrence are added to it step by step. Partial products of the squares of the other two components are added to the residual, step by step. The addition / subtractions in the recurrence are performed without carry / borrow propagation by the use of a redundant representation of the residual. An extension of the on-the-fly conversion algorithm is used for updating the partial result. Different specific versions of the algorithm are possible, depending on the radix, the redundancy factor of the correcting-digit set, the type of representation of the residual, and the correcting-digit selection function.

rawabstract:
A digit-recurrence algorithm for computing the Euclidean norm of a 3-dimensional vector is proposed. Starting from the vector component with the highest order of magnitude as the initial value of partial result, correcting-digits produced by the recurrence are added to it step by step. Partial products of the squares of the other two components are added to the residual, step by step. The addition\slash subtractions in the recurrence are performed without carry\slash borrow propagation by the use of a redundant representation of the residual. An extension of the on-the-fly conversion algorithm is used for updating the partial result. Different specific versions of the algorithm are possible, depending on the radix, the redundancy factor of the correcting-digit set, the type of representation of the residual, and the correcting-digit selection function.

entry:
@InProceedings{Takagi:1999:DRA,
  author =       "Naofumi Takagi and Seiji Kuwahara",
  title =        "Digit-Recurrence Algorithm for Computing {Euclidean}
                 Norm of a {$3$-D} Vector",
  crossref =     "Koren:1999:ISC",
  pages =        "86--95",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-142.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-142.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Takagi.pdf",
  abstract =     "A digit-recurrence algorithm for computing the
                 Euclidean norm of a 3-dimensional vector is proposed.
                 Starting from the vector component with the highest
                 order of magnitude as the initial value of partial
                 result, correcting-digits produced by the recurrence
                 are added to it step by step. Partial products of the
                 squares of the other two components are added to the
                 residual, step by step. The addition\slash subtractions
                 in the recurrence are performed without carry\slash
                 borrow propagation by the use of a redundant
                 representation of the residual. An extension of the
                 on-the-fly conversion algorithm is used for updating
                 the partial result. Different specific versions of the
                 algorithm are possible, depending on the radix, the
                 redundancy factor of the correcting-digit set, the type
                 of representation of the residual, and the
                 correcting-digit selection function.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Tanskanen:1999:REF
author: J. M. A. Tanskanen and V. S. Dimitrov
booktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
title: Round-off error free fixed-point design of polynomial FIR predictors
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1317--1321
year: 1999
bibdate: Sat Jul 16 11:25:05 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:05 MDT
acknowledgement: ack-nhfb
rawauthor: J. M. A. Tanskanen and V. S. Dimitrov
rawbooktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
rawtitle: Round-off error free fixed-point design of polynomial {FIR} predictors
entry:
@InProceedings{Tanskanen:1999:REF,
  author =       "J. M. A. Tanskanen and V. S. Dimitrov",
  booktitle =    "Conference Record of the Thirty-Third Asilomar
                 Conference on Signals, Systems, and Computers, 1999",
  title =        "Round-off error free fixed-point design of polynomial
                 {FIR} predictors",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1317--1321",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:05 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "We present a novel method for designing polynomial FIR
                 predictors for fixed-point environments. Our method
                 yields filters that perform exact prediction of
                 polynomial signals even with short coefficient word
                 lengths. Under ordinary coefficient \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Tenca:1999:DHR
author: Alexandre F. Tenca and Milos D. Ercegovac
title: On the Design of High-Radix On-Line Division for Long Precision
crossref: Koren:1999:ISC
pages: 44--51
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Alexandre F. Tenca and Milo{\v{s}} D. Ercegovac
rawtitle: On the Design of High-Radix On-Line Division for Long Precision
URL:
http://euler.ecs.umass.edu/paper/final/paper-143.pdf; http://euler.ecs.umass.edu/paper/final/paper-143.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Tenca.pdf

abstract:
We present a design of a high-radix on-line division suitable for long precision computations. The proposed scheme uses a quotient-digit selection function based on the residual rounding and scaling of the operands. The bounds on the number of cycles and the cycle time for radix $ 2^k $ and $n$-bit precision are obtained in terms of full-adder delays. The speedup with respect to radix 2 is greater than 3.3 for $ k geq 6 $ and $ n geq 64 $. The cost increases as a function of the radix. For the case $ r = 64 $ and $ n = 64 $, the increase in area with respect to $ r = 2 $ is about 6.6 times plus a $ 512 times 10 $-bit table. The proposed scheme has been designed and verified using VHDL and a $ 1.2 mu $ m CMOS standard gate technology from MOSIS library.

rawabstract:
We present a design of a high-radix on-line division suitable for long precision computations. The proposed scheme uses a quotient-digit selection function based on the residual rounding and scaling of the operands. The bounds on the number of cycles and the cycle time for radix $ 2^k $ and $n$-bit precision are obtained in terms of full-adder delays. The speedup with respect to radix 2 is greater than 3.3 for $ k \geq 6 $ and $ n \geq 64 $. The cost increases as a function of the radix. For the case $ r = 64 $ and $ n = 64 $, the increase in area with respect to $ r = 2 $ is about 6.6 times plus a $ 512 \times 10 $-bit table. The proposed scheme has been designed and verified using VHDL and a $ 1.2 \mu $ m CMOS standard gate technology from MOSIS library.

entry:
@InProceedings{Tenca:1999:DHR,
  author =       "Alexandre F. Tenca and Milo{\v{s}} D. Ercegovac",
  title =        "On the Design of High-Radix On-Line Division for Long
                 Precision",
  crossref =     "Koren:1999:ISC",
  pages =        "44--51",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-143.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-143.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Tenca.pdf",
  abstract =     "We present a design of a high-radix on-line division
                 suitable for long precision computations. The proposed
                 scheme uses a quotient-digit selection function based
                 on the residual rounding and scaling of the operands.
                 The bounds on the number of cycles and the cycle time
                 for radix $ 2^k $ and $n$-bit precision are obtained in
                 terms of full-adder delays. The speedup with respect to
                 radix 2 is greater than 3.3 for $ k \geq 6 $ and $ n
                 \geq 64 $. The cost increases as a function of the
                 radix. For the case $ r = 64 $ and $ n = 64 $, the
                 increase in area with respect to $ r = 2 $ is about 6.6
                 times plus a $ 512 \times 10 $-bit table. The proposed
                 scheme has been designed and verified using VHDL and a
                 $ 1.2 \mu $ m CMOS standard gate technology from MOSIS
                 library.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Thompson:1999:BPF
author: D. U. Thompson and B. A. Wooley
title: A 15-bit Pipelined Floating-Point A/D Converter
crossref: Hosticka:1999:EPE
pages: 170--173
year: 1999
bibdate: Sat Jun 02 08:23:03 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 08:23:03 ???
acknowledgement: ack-nhfb
rawauthor: D. U. Thompson and B. A. Wooley
rawtitle: A 15-bit Pipelined Floating-Point {A/D} Converter
entry:
@InProceedings{Thompson:1999:BPF,
  author =       "D. U. Thompson and B. A. Wooley",
  title =        "A 15-bit Pipelined Floating-Point {A/D} Converter",
  crossref =     "Hosticka:1999:EPE",
  pages =        "170--173",
  year =         "1999",
  bibdate =      "Sat Jun 02 08:23:03 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Tisseur:1999:NMF
author: F. Tisseur
type: Numerical analysis report
number: 346-XY/N-1
institution: Manchester Centre for Computational Mathematics
address: Manchester, UK
pages: 170--173
month: aug
monthnumber: 8
year: 1999
bibdate: Thu May 09 08:58:00 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 08:58:00 ???
acknowledgement: ack-nhfb
rawauthor: F. Tisseur
title:
Newton's method in floating point arithmetic and iterative refinement of generalized eigenvalue problems

rawtitle:
{Newton}'s method in floating point arithmetic and iterative refinement of generalized eigenvalue problems

entry:
@TechReport{Tisseur:1999:NMF,
  author =       "F. Tisseur",
  title =        "{Newton}'s method in floating point arithmetic and
                 iterative refinement of generalized eigenvalue
                 problems",
  type =         "Numerical analysis report",
  number =       "346-XY/N-1",
  institution =  "Manchester Centre for Computational Mathematics",
  address =      "Manchester, UK",
  month =        aug,
  year =         "1999",
  bibdate =      "Thu May 09 08:58:00 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Tropp:1999:HAI
author: Henry S. Tropp
title: Howard Aiken interview: February 26--27, 1973
journal: Computer Oral History Collection, Smithsonian Institution Press
pages: 170--173
year: 1999
bibdate: Thu Aug 07 19:21:30 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 19:21:30 ???
note: Article No. 1.
acknowledgement: ack-nhfb
rawauthor: Henry S. Tropp
rawnote: Article No. 1.
rawtitle: {Howard Aiken} interview: {February 26--27, 1973}
abstract:
Howard Hathaway Aiken was born in 1900. He earned an undergraduate degree in electrical engineering from the University of Wisconsin in 1923, a Masters in Physics from Harvard in 1937, and his Ph.d in Physics from Harvard in 1939. He was the designer and developer of the first large-scale operating relay calculator in the United States. Aiken begins with a discussion of problems associated with mechanical computation while writing his thesis. He comments on Leslie John Comrie and his contributions to computational techniques and discusses his proposal for the MARK I and IBM's agreement and involvement in 1939, to build the machine. Aiken comments on his choice to design MARK I as an electronic device. He was motivated by money because digital counters made with vacuum tubes would have involved thousands of parts which would have been expensive. Aiken comments on early discussions with IBM about what kind of machine would eventually be built and their funding of the machine. He recalls learning that IBM could not divide and how he invented the technique of dividing by computing by reciprocals in response to this problem. Because of what Aiken introduced, the divider became a standard technique in IBM's technical machine design thereafter. The MARK I machine never did any computations for IBM, but rather split its computing time between a project for the Navy and for Harvard. Ultimately, Aiken's MARK machines were used by several other government agencies. He comments on his tenure on the National Academy of Sciences Commission and he discusses the other individuals on the committee---John von Neumann, George Stibitz, and John Curtiss---to name a few. Curtiss promoted the idea of starting an association for people interested in computing machines, which Aiken was opposed to. Curtiss ultimately founded the Association for Computing Machinery which Aiken never joined. The conferences Aiken held at Harvard University beginning in 1946 were solely his doing. He selected the participants and topics to be discussed. These conferences/lectures were, according to Aiken, essential to getting the field of computing ahead at that time. He comments at length on his work outside of the United States, specifically in Europe, and the individuals with whom he worked. Because of Aiken's work at Harvard with MARK, he had a steady stream of foreign researchers who came to work with his machine. He discusses at length the chronology of his four large scale calculators: MARK I, II, III and IV. MARK II was built for the Naval Proving Ground at Dahlgren and implemented in 1950. Aiken would then proceed to design MARK III almost at the same time, 1948 to 1950, and later MARK IV from 1950 to 1952. There was an overlap in the construction and conceptual periods for all the MARK machines. After all of Aiken's MARK machines were built, he felt his effort with computers was completed too and that competing with the industry would not be wise.par The second portion of this interview was conducted on February 27, 1973, and begins with a discussion of Aiken's method of division using the Newton-Raffson rule. Comments include subsequent machines, problems and users, historical digressions, elaboration on specific computing techniques, documentation regarding miscellaneous people and events, and some biographical background information. Those mentioned frequently include: Leon Chaffee, Leslie John Comrie, Donald Menzel, Ted Brown, Harlow Shapley, J.G. Phillips, E.B. Huntington, Ted Kimball, George Stibitz, Dick Bloch, Norbert Wiener, and Grace Murray Hopper.

rawabstract:
Howard Hathaway Aiken was born in 1900. He earned an undergraduate degree in electrical engineering from the University of Wisconsin in 1923, a Masters in Physics from Harvard in 1937, and his Ph.d in Physics from Harvard in 1939. He was the designer and developer of the first large-scale operating relay calculator in the United States. Aiken begins with a discussion of problems associated with mechanical computation while writing his thesis. He comments on Leslie John Comrie and his contributions to computational techniques and discusses his proposal for the MARK I and IBM's agreement and involvement in 1939, to build the machine. Aiken comments on his choice to design MARK I as an electronic device. He was motivated by money because digital counters made with vacuum tubes would have involved thousands of parts which would have been expensive. Aiken comments on early discussions with IBM about what kind of machine would eventually be built and their funding of the machine. He recalls learning that IBM could not divide and how he invented the technique of dividing by computing by reciprocals in response to this problem. Because of what Aiken introduced, the divider became a standard technique in IBM's technical machine design thereafter. The MARK I machine never did any computations for IBM, but rather split its computing time between a project for the Navy and for Harvard. Ultimately, Aiken's MARK machines were used by several other government agencies. He comments on his tenure on the National Academy of Sciences Commission and he discusses the other individuals on the committee---John von Neumann, George Stibitz, and John Curtiss---to name a few. Curtiss promoted the idea of starting an association for people interested in computing machines, which Aiken was opposed to. Curtiss ultimately founded the Association for Computing Machinery which Aiken never joined. The conferences Aiken held at Harvard University beginning in 1946 were solely his doing. He selected the participants and topics to be discussed. These conferences/lectures were, according to Aiken, essential to getting the field of computing ahead at that time. He comments at length on his work outside of the United States, specifically in Europe, and the individuals with whom he worked. Because of Aiken's work at Harvard with MARK, he had a steady stream of foreign researchers who came to work with his machine. He discusses at length the chronology of his four large scale calculators: MARK I, II, III and IV. MARK II was built for the Naval Proving Ground at Dahlgren and implemented in 1950. Aiken would then proceed to design MARK III almost at the same time, 1948 to 1950, and later MARK IV from 1950 to 1952. There was an overlap in the construction and conceptual periods for all the MARK machines. After all of Aiken's MARK machines were built, he felt his effort with computers was completed too and that competing with the industry would not be wise.\par The second portion of this interview was conducted on February 27, 1973, and begins with a discussion of Aiken's method of division using the Newton-Raffson rule. Comments include subsequent machines, problems and users, historical digressions, elaboration on specific computing techniques, documentation regarding miscellaneous people and events, and some biographical background information. Those mentioned frequently include: Leon Chaffee, Leslie John Comrie, Donald Menzel, Ted Brown, Harlow Shapley, J.G. Phillips, E.B. Huntington, Ted Kimball, George Stibitz, Dick Bloch, Norbert Wiener, and Grace Murray Hopper.

entry:
@Article{Tropp:1999:HAI,
  author =       "Henry S. Tropp",
  title =        "{Howard Aiken} interview: {February 26--27, 1973}",
  journal =      "Computer Oral History Collection, Smithsonian
                 Institution Press",
  year =         "1999",
  bibdate =      "Thu Aug 07 19:21:30 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Article No. 1.",
  abstract =     "Howard Hathaway Aiken was born in 1900. He earned an
                 undergraduate degree in electrical engineering from the
                 University of Wisconsin in 1923, a Masters in Physics
                 from Harvard in 1937, and his Ph.d in Physics from
                 Harvard in 1939. He was the designer and developer of
                 the first large-scale operating relay calculator in the
                 United States. Aiken begins with a discussion of
                 problems associated with mechanical computation while
                 writing his thesis. He comments on Leslie John Comrie
                 and his contributions to computational techniques and
                 discusses his proposal for the MARK I and IBM's
                 agreement and involvement in 1939, to build the
                 machine. Aiken comments on his choice to design MARK I
                 as an electronic device. He was motivated by money
                 because digital counters made with vacuum tubes would
                 have involved thousands of parts which would have been
                 expensive. Aiken comments on early discussions with IBM
                 about what kind of machine would eventually be built
                 and their funding of the machine. He recalls learning
                 that IBM could not divide and how he invented the
                 technique of dividing by computing by reciprocals in
                 response to this problem. Because of what Aiken
                 introduced, the divider became a standard technique in
                 IBM's technical machine design thereafter. The MARK I
                 machine never did any computations for IBM, but rather
                 split its computing time between a project for the Navy
                 and for Harvard. Ultimately, Aiken's MARK machines were
                 used by several other government agencies. He comments
                 on his tenure on the National Academy of Sciences
                 Commission and he discusses the other individuals on
                 the committee---John von Neumann, George Stibitz, and
                 John Curtiss---to name a few. Curtiss promoted the idea
                 of starting an association for people interested in
                 computing machines, which Aiken was opposed to. Curtiss
                 ultimately founded the Association for Computing
                 Machinery which Aiken never joined. The conferences
                 Aiken held at Harvard University beginning in 1946 were
                 solely his doing. He selected the participants and
                 topics to be discussed. These conferences/lectures
                 were, according to Aiken, essential to getting the
                 field of computing ahead at that time. He comments at
                 length on his work outside of the United States,
                 specifically in Europe, and the individuals with whom
                 he worked. Because of Aiken's work at Harvard with
                 MARK, he had a steady stream of foreign researchers who
                 came to work with his machine. He discusses at length
                 the chronology of his four large scale calculators:
                 MARK I, II, III and IV. MARK II was built for the Naval
                 Proving Ground at Dahlgren and implemented in 1950.
                 Aiken would then proceed to design MARK III almost at
                 the same time, 1948 to 1950, and later MARK IV from
                 1950 to 1952. There was an overlap in the construction
                 and conceptual periods for all the MARK machines. After
                 all of Aiken's MARK machines were built, he felt his
                 effort with computers was completed too and that
                 competing with the industry would not be wise.\par

                 The second portion of this interview was conducted on
                 February 27, 1973, and begins with a discussion of
                 Aiken's method of division using the Newton-Raffson
                 rule. Comments include subsequent machines, problems
                 and users, historical digressions, elaboration on
                 specific computing techniques, documentation regarding
                 miscellaneous people and events, and some biographical
                 background information. Those mentioned frequently
                 include: Leon Chaffee, Leslie John Comrie, Donald
                 Menzel, Ted Brown, Harlow Shapley, J.G. Phillips, E.B.
                 Huntington, Ted Kimball, George Stibitz, Dick Bloch,
                 Norbert Wiener, and Grace Murray Hopper.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Tropp:1999:NRI
author: Henry S. Tropp and Jean Sammett
title: Nat Rochester interview: July 24, 1973
journal: Computer Oral History Collection, Smithsonian Institution Press
pages: 170--173
year: 1999
bibdate: Thu Aug 07 18:47:37 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 18:47:37 ???
note: Article No. 75.
acknowledgement: ack-nhfb
rawauthor: Henry S. Tropp and Jean Sammett
rawnote: Article No. 75.
rawtitle: {Nat Rochester} interview: {July 24, 1973}
abstract:
Rochester studied electrical engineering at the Massachusetts Institute of Technology (MIT) and was working in acoustics at the outset of World War II. During the war, he worked on radar at the MIT Radiation Laboratory and at Sylvania, building equipment for the Radiation Laboratory. After the war, he worked on the arithmetic unit for Whirlwind and on cryptanalysis equipment for the national Security Agency (NSA). In 1948, feeling that computers would be a ``major thing,'' he went to IBM where he urged their development. His work on a study of the significance of magnetic tape lead to the IBM 700 series. He discusses assembly programming, the switches from card to tape and from decimal to binary systems, the seesawing of the relative reliability of software and hardware, and the advantages and disadvantages of system compatibility. Special mention is made of: the 1946 summer school program at the University of Pennsylvania; the 1947 Aberdeen meeting; and the meeting called by Tom Watson, Jr., at which the decision was made to go ahead with the 700 series, thus making a commitment to computers. Jean Sammett sat in on the interview. Among those often mentioned are John von Neumann, Ralph Palmer, Werner Buchholz, Cuthbert Hurd, and Steve Dunwell.

rawabstract:
Rochester studied electrical engineering at the Massachusetts Institute of Technology (MIT) and was working in acoustics at the outset of World War II. During the war, he worked on radar at the MIT Radiation Laboratory and at Sylvania, building equipment for the Radiation Laboratory. After the war, he worked on the arithmetic unit for Whirlwind and on cryptanalysis equipment for the national Security Agency (NSA). In 1948, feeling that computers would be a ``major thing,'' he went to IBM where he urged their development. His work on a study of the significance of magnetic tape lead to the IBM 700 series. He discusses assembly programming, the switches from card to tape and from decimal to binary systems, the seesawing of the relative reliability of software and hardware, and the advantages and disadvantages of system compatibility. Special mention is made of: the 1946 summer school program at the University of Pennsylvania; the 1947 Aberdeen meeting; and the meeting called by Tom Watson, Jr., at which the decision was made to go ahead with the 700 series, thus making a commitment to computers. Jean Sammett sat in on the interview. Among those often mentioned are John von Neumann, Ralph Palmer, Werner Buchholz, Cuthbert Hurd, and Steve Dunwell.

entry:
@Article{Tropp:1999:NRI,
  author =       "Henry S. Tropp and Jean Sammett",
  title =        "{Nat Rochester} interview: {July 24, 1973}",
  journal =      "Computer Oral History Collection, Smithsonian
                 Institution Press",
  year =         "1999",
  bibdate =      "Thu Aug 07 18:47:37 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Article No. 75.",
  abstract =     "Rochester studied electrical engineering at the
                 Massachusetts Institute of Technology (MIT) and was
                 working in acoustics at the outset of World War II.
                 During the war, he worked on radar at the MIT Radiation
                 Laboratory and at Sylvania, building equipment for the
                 Radiation Laboratory. After the war, he worked on the
                 arithmetic unit for Whirlwind and on cryptanalysis
                 equipment for the national Security Agency (NSA). In
                 1948, feeling that computers would be a ``major
                 thing,'' he went to IBM where he urged their
                 development. His work on a study of the significance of
                 magnetic tape lead to the IBM 700 series. He discusses
                 assembly programming, the switches from card to tape
                 and from decimal to binary systems, the seesawing of
                 the relative reliability of software and hardware, and
                 the advantages and disadvantages of system
                 compatibility. Special mention is made of: the 1946
                 summer school program at the University of
                 Pennsylvania; the 1947 Aberdeen meeting; and the
                 meeting called by Tom Watson, Jr., at which the
                 decision was made to go ahead with the 700 series, thus
                 making a commitment to computers. Jean Sammett sat in
                 on the interview. Among those often mentioned are John
                 von Neumann, Ralph Palmer, Werner Buchholz, Cuthbert
                 Hurd, and Steve Dunwell.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Tsuji:1999:REO
author: K. Tsuji
title: Round-off error of optimal control problems in floating-point number systems
crossref: Begehr:1999:PSI
pages: 929--944
year: 1999
bibdate: Sat Jun 02 08:12:11 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 08:12:11 ???
acknowledgement: ack-nhfb
rawauthor: K. Tsuji
rawtitle: Round-off error of optimal control problems in floating-point number systems
entry:
@InProceedings{Tsuji:1999:REO,
  author =       "K. Tsuji",
  title =        "Round-off error of optimal control problems in
                 floating-point number systems",
  crossref =     "Begehr:1999:PSI",
  pages =        "929--944",
  year =         "1999",
  bibdate =      "Sat Jun 02 08:12:11 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Walter:1999:MTI
author: Colin D. Walter
title: Moduli for Testing Implementations of the RSA Cryptosystem
crossref: Koren:1999:ISC
pages: 78--85
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
acknowledgement: ack-nhfb
rawauthor: Colin D. Walter
rawtitle: Moduli for Testing Implementations of the {RSA} Cryptosystem
URL:
http://euler.ecs.umass.edu/paper/final/paper-130.pdf; http://euler.ecs.umass.edu/paper/final/paper-130.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Walter.pdf

abstract:
Comprehensive testing of any implementation of the RSA cryptosystem requires the use of a number of moduli with specific properties. It is shown how to generate a sufficient variety of these to enable testing which will justify high confidence in the correctness of both the design and the operation of hardware implementations. The tests avoid the necessity of another implementation for comparison. Many of these moduli are also suitable for testing software implementations. Furthermore, the methods apply equally well to other similar modular arithmetic based cryptosystems which use exponentiation, such as Diffie-Helman key exchange.

keywords:
ARITH-14; computer arithmetic; correctness; cryptography; implementation validation benchmark.; RSA modulus; testing; verification

rawabstract:
Comprehensive testing of any implementation of the RSA cryptosystem requires the use of a number of moduli with specific properties. It is shown how to generate a sufficient variety of these to enable testing which will justify high confidence in the correctness of both the design and the operation of hardware implementations. The tests avoid the necessity of another implementation for comparison. Many of these moduli are also suitable for testing software implementations. Furthermore, the methods apply equally well to other similar modular arithmetic based cryptosystems which use exponentiation, such as Diffie-Helman key exchange.

entry:
@InProceedings{Walter:1999:MTI,
  author =       "Colin D. Walter",
  title =        "Moduli for Testing Implementations of the {RSA}
                 Cryptosystem",
  crossref =     "Koren:1999:ISC",
  pages =        "78--85",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-130.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-130.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Walter.pdf",
  abstract =     "Comprehensive testing of any implementation of the RSA
                 cryptosystem requires the use of a number of moduli
                 with specific properties. It is shown how to generate a
                 sufficient variety of these to enable testing which
                 will justify high confidence in the correctness of both
                 the design and the operation of hardware
                 implementations. The tests avoid the necessity of
                 another implementation for comparison. Many of these
                 moduli are also suitable for testing software
                 implementations. Furthermore, the methods apply equally
                 well to other similar modular arithmetic based
                 cryptosystems which use exponentiation, such as
                 Diffie-Helman key exchange.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic; correctness;
                 cryptography; implementation validation benchmark.; RSA
                 modulus; testing; verification",
}


bibtype: article
filename: fparith.bib
label: Watanabe:1999:NVM
author: Y. Watanabe and N. Yamamoto and M. T. Nakao
title: A Numerical Verification Method of Solutions for the Navier--Stokes Equations
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 347--357
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: Y. Watanabe and N. Yamamoto and M. T. Nakao
rawtitle: A Numerical Verification Method of Solutions for the {Navier--Stokes} Equations
entry:
@Article{Watanabe:1999:NVM,
  author =       "Y. Watanabe and N. Yamamoto and M. T. Nakao",
  title =        "A Numerical Verification Method of Solutions for the
                 {Navier--Stokes} Equations",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "347--357",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: inproceedings
filename: fparith.bib
label: Wires:1999:CUT
author: K. E. Wires and M. J. Schulte and L. P. Marquette and P. I. Balzola
title: Combined Unsigned and Two's Complement Squarers
crossref: Matthews:1999:CRT
pages: 1215--1219
year: 1999
bibdate: Sun Mar 04 11:08:58 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:08:58 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-06.pdf
acknowledgement: ack-nhfb
rawauthor: K. E. Wires and M. J. Schulte and L. P. Marquette and P. I. Balzola
rawtitle: Combined Unsigned and Two's Complement Squarers
entry:
@InProceedings{Wires:1999:CUT,
  author =       "K. E. Wires and M. J. Schulte and L. P. Marquette and
                 P. I. Balzola",
  title =        "Combined Unsigned and Two's Complement Squarers",
  crossref =     "Matthews:1999:CRT",
  pages =        "1215--1219",
  year =         "1999",
  bibdate =      "Sun Mar 04 11:08:58 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-06.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Wong:1999:OFP
author: W. F. Wong
title: Optimizing floating point operations in Scheme
journal: j-COMP-LANGS
volume: 25
number: 2
pages: 89--112
month: jul
monthnumber: 7
year: 1999
CODEN: COLADA
ISSN: 0096-0551 (print), 1873-6742 (electronic) OR 00960551 (print), 18736742 (electronic)
ISSNL: 0096-0551 OR 00960551
bibdate: Thu Oct 12 10:20:10 MDT 2000
bibtimestamp: 2000.10.12 10:20:10 MDT
fjournal: Computer Languages
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00960551
rawauthor: W. F. Wong
rawtitle: Optimizing floating point operations in {Scheme}
bibsource:
http://www.elsevier.com/locate/complang; https://www.math.utah.edu/pub/tex/bib/complngs.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www.elsevier.nl/gej-ng/10/15/18/28/27/26/abstract.html; http://www.elsevier.nl/gej-ng/10/15/18/28/27/26/article.pdf

entry:
@Article{Wong:1999:OFP,
  author =       "W. F. Wong",
  title =        "Optimizing floating point operations in {Scheme}",
  journal =      j-COMP-LANGS,
  volume =       "25",
  number =       "2",
  pages =        "89--112",
  month =        jul,
  year =         "1999",
  CODEN =        "COLADA",
  ISSN =         "0096-0551 (print), 1873-6742 (electronic)",
  ISSN-L =       "0096-0551",
  bibdate =      "Thu Oct 12 10:20:10 MDT 2000",
  bibsource =    "http://www.elsevier.com/locate/complang;
                 https://www.math.utah.edu/pub/tex/bib/complngs.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.elsevier.nl/gej-ng/10/15/18/28/27/26/abstract.html;
                 http://www.elsevier.nl/gej-ng/10/15/18/28/27/26/article.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Languages",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00960551",
}


bibtype: inproceedings
filename: fparith.bib
label: Yadav:1999:PSF
author: N. Yadav and M. J. Schulte and J. Glossner
title: Parallel Saturating Fractional Arithmetic Units
crossref: Mazumder:1999:NGL
pages: 214--217
year: 1999
bibdate: Sun Mar 04 11:15:11 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:15:11 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-02.pdf
acknowledgement: ack-nhfb
rawauthor: N. Yadav and M. J. Schulte and J. Glossner
rawtitle: Parallel Saturating Fractional Arithmetic Units
entry:
@InProceedings{Yadav:1999:PSF,
  author =       "N. Yadav and M. J. Schulte and J. Glossner",
  title =        "Parallel Saturating Fractional Arithmetic Units",
  crossref =     "Mazumder:1999:NGL",
  pages =        "214--217",
  year =         "1999",
  bibdate =      "Sun Mar 04 11:15:11 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-02.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Yang:1999:CIS
author: D. X. D. Yang and A. E. Gamal and B. Fowler and H. Tian
title: A 640$ times $512 CMOS image sensor with ultrawide dynamic range floating-point pixel-level ADC
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 34
number: 12
pages: 1821--1834
month: dec
monthnumber: 12
year: 1999
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawauthor: D. X. D. Yang and A. E. Gamal and B. Fowler and H. Tian
rawtitle:
A 640$ \times $512 {CMOS} image sensor with ultrawide dynamic range floating-point pixel-level {ADC}

entry:
@Article{Yang:1999:CIS,
  author =       "D. X. D. Yang and A. E. Gamal and B. Fowler and H.
                 Tian",
  title =        "A 640$ \times $512 {CMOS} image sensor with ultrawide
                 dynamic range floating-point pixel-level {ADC}",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "34",
  number =       "12",
  pages =        "1821--1834",
  month =        dec,
  year =         "1999",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "Analysis results demonstrate that multiple sampling
                 can achieve consistently higher signal-to-noise ratio
                 at equal or higher dynamic range than using other image
                 sensor dynamic range enhancement schemes such as well
                 capacity adjusting. Implementing \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Yang:1999:RNSa
author: Lie-Liang Yang and L. Hanzo
title: Residue number system arithmetic assisted $M$-ary modulation
journal: j-IEEE-COMMUN-LET
volume: 3
number: 2
pages: 28--30
month: feb
monthnumber: 2
year: 1999
CODEN: ICLEF6
DOI: https://doi.org/10.1109/4234.749352
ISSNL: 1089-7798 OR 10897798
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=16186
fjournal: IEEE Communications Letters
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4234
rawauthor: Lie-Liang Yang and L. Hanzo
rawtitle: Residue number system arithmetic assisted {$M$}-ary modulation
entry:
@Article{Yang:1999:RNSa,
  author =       "Lie-Liang Yang and L. Hanzo",
  title =        "Residue number system arithmetic assisted {$M$}-ary
                 modulation",
  journal =      j-IEEE-COMMUN-LET,
  volume =       "3",
  number =       "2",
  pages =        "28--30",
  month =        feb,
  year =         "1999",
  CODEN =        "ICLEF6",
  DOI =          "https://doi.org/10.1109/4234.749352",
  ISSN =         "????",
  ISSN-L =       "1089-7798",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=16186",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Communications Letters",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4234",
  keywords =     "residue arithmetic; residue number system",
  summary =      "A residue number system based M-ary modem is proposed
                 and its performance is evaluated over Gaussian
                 channels. When one or two redundant moduli are
                 employed, a signal-to-noise ratio gain of 1.2-2 dB was
                 achieved for a 16-ary, 32-ary and 37-ary modem,
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Yang:1999:RNSb
author: Lie-Liang Yang and L. Hanzo
booktitle: IEEE 49th Vehicular Technology Conference, 16--20 May 1999
title: Residue number system based multiple code DS-CDMA systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1450--1454
year: 1999
DOI: https://doi.org/10.1109/VETEC.1999.780587
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: Lie-Liang Yang and L. Hanzo
rawbooktitle: {IEEE 49th} Vehicular Technology Conference, 16--20 May 1999
rawtitle: Residue number system based multiple code {DS-CDMA} systems
entry:
@InProceedings{Yang:1999:RNSb,
  author =       "Lie-Liang Yang and L. Hanzo",
  booktitle =    "{IEEE 49th} Vehicular Technology Conference, 16--20
                 May 1999",
  title =        "Residue number system based multiple code {DS-CDMA}
                 systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1450--1454",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/VETEC.1999.780587",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A novel multi-code direct-sequence code division
                 multiple-access (DS-CDMA) system based on the so-called
                 residue number system (RNS) or the redundant residue
                 number system (RRNS) is proposed. Concatenated codes
                 employing RNS product codes (RNS-PC) \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Yang:1999:RST
author: Lie-Liang Yang and L. Hanzo
booktitle: IEEE 49th Vehicular Technology Conference. 16--20 May 1999
title: Ratio statistic test assisted residue number system based parallel communication schemes
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 894--898
year: 1999
DOI: https://doi.org/10.1109/VETEC.1999.780477
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: Lie-Liang Yang and L. Hanzo
rawbooktitle: {IEEE 49th} Vehicular Technology Conference. 16--20 May 1999
rawtitle: Ratio statistic test assisted residue number system based parallel communication schemes
entry:
@InProceedings{Yang:1999:RST,
  author =       "Lie-Liang Yang and L. Hanzo",
  booktitle =    "{IEEE 49th} Vehicular Technology Conference. 16--20
                 May 1999",
  title =        "Ratio statistic test assisted residue number system
                 based parallel communication schemes",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "894--898",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/VETEC.1999.780477",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A residue number system (RNS) based parallel
                 communication system is proposed and its performance is
                 evaluated using non-coherent demodulation. Diversity
                 reception techniques with equal gain combining (EGC) or
                 selection combining (SC) are considered \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Yap:1999:REI
author: C. Yap and K. Ouchi
title: Real/Expr: Implementation of Exact Computation
pages: 894--898
day: 22
month: jan
monthnumber: 1
year: 1999
bibdate: Tue Oct 22 06:22:39 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.22 06:22:39 ???
URL: https://cs.nyu.edu/exact/realexpr/
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: C. Yap and K. Ouchi
rawtitle: {Real/Expr}: Implementation of Exact Computation
entry:
@Misc{Yap:1999:REI,
  author =       "C. Yap and K. Ouchi",
  title =        "{Real/Expr}: Implementation of Exact Computation",
  howpublished = "Web site",
  day =          "22",
  month =        jan,
  year =         "1999",
  bibdate =      "Tue Oct 22 06:22:39 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://cs.nyu.edu/exact/realexpr/",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Yuan:1999:FPA
author: J. Yuan and J. Piper
title: Floating-Point Analog-To-Digital Converter
crossref: IEEE:1999:IPI
pages: 1385--1388
year: 1999
bibdate: Sat Jun 02 08:19:08 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 08:19:08 ???
acknowledgement: ack-nhfb
rawauthor: J. Yuan and J. Piper
rawtitle: Floating-Point Analog-To-Digital Converter
entry:
@InProceedings{Yuan:1999:FPA,
  author =       "J. Yuan and J. Piper",
  title =        "Floating-Point Analog-To-Digital Converter",
  crossref =     "IEEE:1999:IPI",
  pages =        "1385--1388",
  year =         "1999",
  bibdate =      "Sat Jun 02 08:19:08 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Zimmermann:1999:EVI
author: Reto Zimmermann
title: Efficient VLSI Implementation of Modulo $ (2^n pm 1) $ Addition and Multiplication
crossref: Koren:1999:ISC
pages: 158--167
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Reto Zimmermann
rawtitle: Efficient {VLSI} Implementation of Modulo $ (2^n \pm 1) $ Addition and Multiplication
URL:
http://euler.ecs.umass.edu/paper/final/paper-127.pdf; http://euler.ecs.umass.edu/paper/final/paper-127.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Zimmermann.pdf

abstract:
New VLSI circuit architectures for addition and multiplication modulo $ (2 n - 1) $ and $ (2 n + 1) $ are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are improved for higher speed and regularity. These allow the use of common multiplier speedup techniques like Wallace tree addition and Booth recoding, resulting in the fastest known modulo multipliers. Finally, a high-performance modulo multiplier-adder for the IDEA block cipher is presented. The resulting circuits are compared qualitatively and quantitatively, i.e., in a standard cell technology, with existing solutions and ordinary integer adders and multipliers.

rawabstract:
New VLSI circuit architectures for addition and multiplication modulo $ (2 n - 1) $ and $ (2 n + 1) $ are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are improved for higher speed and regularity. These allow the use of common multiplier speedup techniques like Wallace tree addition and Booth recoding, resulting in the fastest known modulo multipliers. Finally, a high-performance modulo multiplier-adder for the IDEA block cipher is presented. The resulting circuits are compared qualitatively and quantitatively, i.e., in a standard cell technology, with existing solutions and ordinary integer adders and multipliers.

entry:
@InProceedings{Zimmermann:1999:EVI,
  author =       "Reto Zimmermann",
  title =        "Efficient {VLSI} Implementation of Modulo $ (2^n \pm
                 1) $ Addition and Multiplication",
  crossref =     "Koren:1999:ISC",
  pages =        "158--167",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-127.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-127.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Zimmermann.pdf",
  abstract =     "New VLSI circuit architectures for addition and
                 multiplication modulo $ (2 n - 1) $ and $ (2 n + 1) $
                 are proposed that allow the implementation of highly
                 efficient combinational and pipelined circuits for
                 modular arithmetic. It is shown that the
                 parallel-prefix adder architecture is well suited to
                 realize fast end-around-carry adders used for modulo
                 addition. Existing modulo multiplier architectures are
                 improved for higher speed and regularity. These allow
                 the use of common multiplier speedup techniques like
                 Wallace tree addition and Booth recoding, resulting in
                 the fastest known modulo multipliers. Finally, a
                 high-performance modulo multiplier-adder for the IDEA
                 block cipher is presented. The resulting circuits are
                 compared qualitatively and quantitatively, i.e., in a
                 standard cell technology, with existing solutions and
                 ordinary integer adders and multipliers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: techreport
filename: fparith.bib
label: Zimmermann:1999:KSR
author: Paul Zimmermann
title: Karatsuba Square Root
type: Research Report
number: 3805
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 8
year: 1999
bibdate: Sun Sep 10 08:56:48 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 08:56:48 ???
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann
rawtitle: {Karatsuba} Square Root
URL:
ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-3805.pdf; ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-3805.ps.gz; http://www.inria.fr/rrrt/rr-3805.html

abstract:
We exhibit an algorithm to compute the square-root with remainder of a $n$-word number in $ 3 / 2 $ word operations, where $ K(n) $ is the number of words operations to multiply two $n$-word numbers using Karatsuba's algorithm. If the remainder is not needed, the cost can be reduced to $ K(n) $ on average. This algorithm can be used for floating-point or polynomial computations too; although not optimal asymptotically, its simplicity gives a wide range of use, from about 50 to 1,000,000 digits, as shown by computer experiments.

rawabstract:
We exhibit an algorithm to compute the square-root with remainder of a $n$-word number in $ 3 / 2 $ word operations, where $ K(n) $ is the number of words operations to multiply two $n$-word numbers using Karatsuba's algorithm. If the remainder is not needed, the cost can be reduced to $ K(n) $ on average. This algorithm can be used for floating-point or polynomial computations too; although not optimal asymptotically, its simplicity gives a wide range of use, from about 50 to 1,000,000 digits, as shown by computer experiments.

entry:
@TechReport{Zimmermann:1999:KSR,
  author =       "Paul Zimmermann",
  title =        "{Karatsuba} Square Root",
  type =         "Research Report",
  number =       "3805",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "8",
  year =         "1999",
  bibdate =      "Sun Sep 10 08:56:48 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-3805.pdf;
                 ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-3805.ps.gz;
                 http://www.inria.fr/rrrt/rr-3805.html",
  abstract =     "We exhibit an algorithm to compute the square-root
                 with remainder of a $n$-word number in $ 3 / 2 $ word
                 operations, where $ K(n) $ is the number of words
                 operations to multiply two $n$-word numbers using
                 Karatsuba's algorithm. If the remainder is not needed,
                 the cost can be reduced to $ K(n) $ on average. This
                 algorithm can be used for floating-point or polynomial
                 computations too; although not optimal asymptotically,
                 its simplicity gives a wide range of use, from about 50
                 to 1,000,000 digits, as shown by computer
                 experiments.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ziv:1999:SUR
author: Abraham Ziv
title: Sharp ULP rounding error bound for the hypotenuse function
journal: j-MATH-COMPUT
volume: 68
number: 227
pages: 1143--1148
month: jul
monthnumber: 7
year: 1999
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Fri Jul 16 10:39:05 MDT 1999
bibtimestamp: 1999.07.16 10:39:05 MDT
URL: http://www.ams.org/jourcgi/jour-pbprocess?fn=110&arg1=S0025-5718-99-01103-5&u=/mcom/1999-68-227/
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Abraham Ziv
rawtitle: Sharp {ULP} rounding error bound for the hypotenuse function
bibsource:
http://www.ams.org/mcom/1999-68-227; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp1990.bib

entry:
@Article{Ziv:1999:SUR,
  author =       "Abraham Ziv",
  title =        "Sharp {ULP} rounding error bound for the hypotenuse
                 function",
  journal =      j-MATH-COMPUT,
  volume =       "68",
  number =       "227",
  pages =        "1143--1148",
  month =        jul,
  year =         "1999",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Fri Jul 16 10:39:05 MDT 1999",
  bibsource =    "http://www.ams.org/mcom/1999-68-227;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp1990.bib",
  URL =          "http://www.ams.org/jourcgi/jour-pbprocess?fn=110&arg1=S0025-5718-99-01103-5&u=/mcom/1999-68-227/",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: periodical
filename: fparith.bib
label: FPS:19xx:R
author: Floating Point Systems, Inc.Users Group Meeting
title: Record
publisher: Floating Point Systems
address: Portland, OR, USA
pages: various
year: 19xx
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Array processors --- Congresses; Parallel processing (Electronic computers) --- Congresses
acknowledgement: ack-nhfb
key: FPS
rawauthor: {Floating Point Systems, Inc.Users Group Meeting}
rawtitle: Record
entry:
@Periodical{FPS:19xx:R,
  author =       "{Floating Point Systems, Inc.Users Group Meeting}",
  key =          "FPS",
  title =        "Record",
  publisher =    "Floating Point Systems",
  address =      "Portland, OR, USA",
  pages =        "various",
  year =         "19xx",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  alttitle =     "Record (Floating Point Systems, Inc. Users Group.
                 Meeting) ARRAY (Organization). Conference.
                 Proceedings",
  keywords =     "Array processors --- Congresses; Parallel processing
                 (Electronic computers) --- Congresses",
}


bibtype: manual
filename: fparith.bib
label: Intel:19xx:IAP
author: Intel
title: Intel 8231A Arithmetic Processing Unit
organization: Intel Corp
address: San Jose, CA, USA
pages: various
year: 19xx
bibdate: Thu Oct 14 15:14:43 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.14 15:14:43 ???
URL: http://www.datasheetarchive.com/pdf-datasheets/Datasheets-14/DSA-276911.html
remark: Undated processor datasheet.
acknowledgement: ack-nhfb
rawauthor: {Intel}
rawtitle: {Intel 8231A} Arithmetic Processing Unit
note:
From the datasheet (p. 3-5): ``The mantissa is expressed as a 24-bit (fractional) value; the exponent is expressed as a two's complement 7-bit value having the range $ - 64 $ to $ + 63 $. The most significant bit is the sign of the mantissa ($0$ = positive, $1$ = negative), for a total of 32 bits. The binary point is assumed to be [to] the left of the most significant mantissa bit (bit 23). All floating-point data values must be normalized. Bit 23 must be equal to 1, except for the value zero, which is represented by all zeros. The range of values that can be represented in this format is $ pm (2.7 time 10^-10 ldots 9.2 times 10^18) $ and zero.''

rawnote:
From the datasheet (p. 3-5): ``The mantissa is expressed as a 24-bit (fractional) value; the exponent is expressed as a two's complement 7-bit value having the range $ - 64 $ to $ + 63 $. The most significant bit is the sign of the mantissa ($0$ = positive, $1$ = negative), for a total of 32 bits. The binary point is assumed to be [to] the left of the most significant mantissa bit (bit 23). All floating-point data values must be normalized. Bit 23 must be equal to 1, except for the value zero, which is represented by all zeros. The range of values that can be represented in this format is $ \pm (2.7 \time 10^{-10} \ldots {} 9.2 \times 10^{18}) $ and zero.''

entry:
@Manual{Intel:19xx:IAP,
  author =       "{Intel}",
  title =        "{Intel 8231A} Arithmetic Processing Unit",
  organization = "Intel Corp",
  address =      "San Jose, CA, USA",
  year =         "19xx",
  bibdate =      "Thu Oct 14 15:14:43 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "From the datasheet (p. 3-5): ``The mantissa is
                 expressed as a 24-bit (fractional) value; the exponent
                 is expressed as a two's complement 7-bit value having
                 the range $ - 64 $ to $ + 63 $. The most significant
                 bit is the sign of the mantissa ($0$ = positive, $1$ =
                 negative), for a total of 32 bits. The binary point is
                 assumed to be [to] the left of the most significant
                 mantissa bit (bit 23). All floating-point data values
                 must be normalized. Bit 23 must be equal to 1, except
                 for the value zero, which is represented by all zeros.
                 The range of values that can be represented in this
                 format is $ \pm (2.7 \time 10^{-10} \ldots {} 9.2
                 \times 10^{18}) $ and zero.''",
  URL =          "http://www.datasheetarchive.com/pdf-datasheets/Datasheets-14/DSA-276911.html",
  acknowledgement = ack-nhfb,
  remark =       "Undated processor datasheet.",
}


bibtype: article
filename: fparith.bib
label: Anonymous:2000:BRCd
author: Anonymous
journal: j-COMPUT-MATH-APPL
volume: 39
number: 3--4
pages: 264--264
month: feb
monthnumber: 2
year: 2000
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:49:06 MST 2017
bibtimestamp: 2017.03.01 21:49:06 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122100900518
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: Anonymous
title:
Book Review: booktitle Computer arithmetic: Algorithms and hardware designs: By Behrooz Parhami. Oxford University Press, New York. (2000). 490 pages. $85.00

bibsource:
https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Book Review: {{\booktitle{Computer arithmetic: Algorithms and hardware designs}}: By Behrooz Parhami. Oxford University Press, New York. (2000). 490 pages. \$85.00}

entry:
@Article{Anonymous:2000:BRCd,
  author =       "Anonymous",
  title =        "Book Review: {{\booktitle{Computer arithmetic:
                 Algorithms and hardware designs}}: By Behrooz Parhami.
                 Oxford University Press, New York. (2000). 490 pages.
                 \$85.00}",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "39",
  number =       "3--4",
  pages =        "264--264",
  month =        feb,
  year =         "2000",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:49:06 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122100900518",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Anonymous:2000:BRCg
author: Anonymous
journal: j-COMPUT-MATH-APPL
volume: 39
number: 7--8
pages: 266--266
month: apr
monthnumber: 4
year: 2000
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:49:08 MST 2017
bibtimestamp: 2017.03.01 21:49:08 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122100902955
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: Anonymous
title:
Book Review: booktitle Computer arithmetic: Algorithms and hardware designs: By Behrooz Parhami. Oxford University Press, New York. (2000). 490 pages. $85.00

bibsource:
https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Book Review: {{\booktitle{Computer arithmetic: Algorithms and hardware designs}}: By Behrooz Parhami. Oxford University Press, New York. (2000). 490 pages. \$85.00}

entry:
@Article{Anonymous:2000:BRCg,
  author =       "Anonymous",
  title =        "Book Review: {{\booktitle{Computer arithmetic:
                 Algorithms and hardware designs}}: By Behrooz Parhami.
                 Oxford University Press, New York. (2000). 490 pages.
                 \$85.00}",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "39",
  number =       "7--8",
  pages =        "266--266",
  month =        apr,
  year =         "2000",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:49:08 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122100902955",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Antelo:2000:VHR
author: E. Antelo and T. Lang and J. D. Bruguera
title: Very-High Radix Circular CORDIC: Vectoring and Unified Rotation / Vectoring
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 727--739
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863043
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:47:55 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:47:55 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: E. Antelo and T. Lang and J. D. Bruguera
rawtitle: Very-High Radix Circular {CORDIC}: Vectoring and Unified Rotation\slash Vectoring
entry:
@Article{Antelo:2000:VHR,
  author =       "E. Antelo and T. Lang and J. D. Bruguera",
  title =        "Very-High Radix Circular {CORDIC}: Vectoring and
                 Unified Rotation\slash Vectoring",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "727--739",
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863043",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:47:55 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
}


bibtype: misc
filename: fparith.bib
label: Arnold:2000:EAS
author: D. Arnold
title: The Explosion of the Ariane 5. Some disasters attributable to bad numerical computing
pages: 727--739
day: 23
month: aug
monthnumber: 8
year: 2000
bibdate: Mon Aug 26 11:10:55 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.26 11:10:55 ???
URL: https://www-users.math.umn.edu/~arnold/disasters/ariane.html
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: D. Arnold
rawtitle: The Explosion of the {Ariane 5}. {Some} disasters attributable to bad numerical computing
entry:
@Misc{Arnold:2000:EAS,
  author =       "D. Arnold",
  title =        "The Explosion of the {Ariane 5}. {Some} disasters
                 attributable to bad numerical computing",
  howpublished = "Web site.",
  day =          "23",
  month =        aug,
  year =         "2000",
  bibdate =      "Mon Aug 26 11:10:55 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www-users.math.umn.edu/~arnold/disasters/ariane.html",
  acknowledgement = ack-nhfb,
}


bibtype: phdthesis
filename: fparith.bib
label: Baidas:2000:HLF
author: Zaher A. Baidas
title: High-level floating-point synthesis
type: Thesis (Ph.D.)
school: University of Southampton, Department of Electronics and Computer Science
address: Southampton, UK
pages: 327
year: 2000
bibdate: Thu May 09 08:47:14 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 08:47:14 ???
acknowledgement: ack-nhfb
rawauthor: Zaher A. Baidas
rawtitle: High-level floating-point synthesis
entry:
@PhdThesis{Baidas:2000:HLF,
  author =       "Zaher A. Baidas",
  title =        "High-level floating-point synthesis",
  type =         "Thesis ({Ph.D.})",
  school =       "University of Southampton, Department of Electronics
                 and Computer Science",
  address =      "Southampton, UK",
  pages =        "327",
  year =         "2000",
  bibdate =      "Thu May 09 08:47:14 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Batten:2000:NAD
author: D. Batten and S. Jinturkar and J. Glossner and M. Schulte and P. D'arcy
title: A New Approach to DSP Intrinsic Functions
crossref: Sprague:2000:PAH
pages: 2892--2901
year: 2000
bibdate: Sun Mar 04 11:18:38 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:18:38 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2000-01.pdf
acknowledgement: ack-nhfb
rawauthor: D. Batten and S. Jinturkar and J. Glossner and M. Schulte and P. D'arcy
rawtitle: A New Approach to {DSP} Intrinsic Functions
entry:
@InProceedings{Batten:2000:NAD,
  author =       "D. Batten and S. Jinturkar and J. Glossner and M.
                 Schulte and P. D'arcy",
  title =        "A New Approach to {DSP} Intrinsic Functions",
  crossref =     "Sprague:2000:PAH",
  pages =        "2892--2901",
  year =         "2000",
  bibdate =      "Sun Mar 04 11:18:38 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2000-01.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Becker:2000:JSE
author: Pete Becker
title: The Journeyman's Shop: Error in Floating-Point Calculations
journal: j-CCCUJ
volume: 18
number: 7
pages: 73--??
month: jul
monthnumber: 7
year: 2000
CODEN: CCUJEX
ISSN: 1075-2838 OR 10752838
bibdate: Tue May 14 18:09:27 MDT 2002
bibtimestamp: 2002.05.14 18:09:27 MDT
abstract: And you thought error, accuracy, precision, and significance were pretty synonymous.
fjournal: C/C++ Users Journal
acknowledgement: ack-nhfb
rawabstract: And you thought error, accuracy, precision, and significance were pretty synonymous.
rawauthor: Pete Becker
rawtitle: The Journeyman's Shop: Error in Floating-Point Calculations
bibsource:
http://www.cuj.com/articles/2000/0007/0007toc.htm?topic=articles; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Becker:2000:JSE,
  author =       "Pete Becker",
  title =        "The Journeyman's Shop: Error in Floating-Point
                 Calculations",
  journal =      j-CCCUJ,
  volume =       "18",
  number =       "7",
  pages =        "73--??",
  month =        jul,
  year =         "2000",
  CODEN =        "CCUJEX",
  ISSN =         "1075-2838",
  bibdate =      "Tue May 14 18:09:27 MDT 2002",
  bibsource =    "http://www.cuj.com/articles/2000/0007/0007toc.htm?topic=articles;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "And you thought error, accuracy, precision, and
                 significance were pretty synonymous.",
  acknowledgement = ack-nhfb,
  fjournal =     "C/C++ Users Journal",
}


bibtype: article
filename: fparith.bib
label: Becker:2000:JSF
author: Pete Becker
title: The Journeyman's Shop: Floating-Point Basics
journal: j-CCCUJ
volume: 18
number: 6
pages: ??--??
month: jun
monthnumber: 6
year: 2000
CODEN: CCUJEX
ISSN: 1075-2838 OR 10752838
bibdate: Tue May 14 18:09:26 MDT 2002
bibtimestamp: 2002.05.14 18:09:26 MDT
fjournal: C/C++ Users Journal
acknowledgement: ack-nhfb
rawauthor: Pete Becker
rawtitle: The Journeyman's Shop: Floating-Point Basics
bibsource:
http://www.cuj.com/articles/2000/0006/0006toc.htm?topic=articles; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
You can't overcome a fear of floating-point arithmetic --- or complacency about it --- until you understand what's going on.

rawabstract:
You can't overcome a fear of floating-point arithmetic --- or complacency about it --- until you understand what's going on.

entry:
@Article{Becker:2000:JSF,
  author =       "Pete Becker",
  title =        "The Journeyman's Shop: Floating-Point Basics",
  journal =      j-CCCUJ,
  volume =       "18",
  number =       "6",
  pages =        "??--??",
  month =        jun,
  year =         "2000",
  CODEN =        "CCUJEX",
  ISSN =         "1075-2838",
  bibdate =      "Tue May 14 18:09:26 MDT 2002",
  bibsource =    "http://www.cuj.com/articles/2000/0006/0006toc.htm?topic=articles;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "You can't overcome a fear of floating-point arithmetic
                 --- or complacency about it --- until you understand
                 what's going on.",
  acknowledgement = ack-nhfb,
  fjournal =     "C/C++ Users Journal",
}


bibtype: article
filename: fparith.bib
label: Becker:2000:JST
author: Pete Becker
title: The Journeyman's Shop: Trap Handlers, Sticky Bits, and Floating-Point Comparisons
journal: j-CCCUJ
volume: 18
number: 12
pages: 54--??
month: dec
monthnumber: 12
year: 2000
CODEN: CCUJEX
ISSN: 1075-2838 OR 10752838
bibdate: Tue May 14 18:09:29 MDT 2002
bibtimestamp: 2002.05.14 18:09:29 MDT
abstract: Pete wraps up his series on practical floating-point math.
fjournal: C/C++ Users Journal
acknowledgement: ack-nhfb
rawabstract: Pete wraps up his series on practical floating-point math.
rawauthor: Pete Becker
rawtitle: The Journeyman's Shop: Trap Handlers, Sticky Bits, and Floating-Point Comparisons
bibsource:
http://www.cuj.com/articles/2000/0012/0012toc.htm?topic=articles; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Becker:2000:JST,
  author =       "Pete Becker",
  title =        "The Journeyman's Shop: Trap Handlers, Sticky Bits, and
                 Floating-Point Comparisons",
  journal =      j-CCCUJ,
  volume =       "18",
  number =       "12",
  pages =        "54--??",
  month =        dec,
  year =         "2000",
  CODEN =        "CCUJEX",
  ISSN =         "1075-2838",
  bibdate =      "Tue May 14 18:09:29 MDT 2002",
  bibsource =    "http://www.cuj.com/articles/2000/0012/0012toc.htm?topic=articles;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Pete wraps up his series on practical floating-point
                 math.",
  acknowledgement = ack-nhfb,
  fjournal =     "C/C++ Users Journal",
}


bibtype: article
filename: fparith.bib
label: Becker:2000:JSWb
author: Pete Becker
title: The Journeyman's Shop: When Bad Things Happen to Good Numbers
journal: j-CCCUJ
volume: 18
number: 10
pages: 54--??
month: oct
monthnumber: 10
year: 2000
CODEN: CCUJEX
ISSN: 1075-2838 OR 10752838
bibdate: Tue May 14 18:09:28 MDT 2002
bibtimestamp: 2002.05.14 18:09:28 MDT
abstract: It takes a lot of preparation to write really robust floating-point code.
fjournal: C/C++ Users Journal
acknowledgement: ack-nhfb
rawabstract: It takes a lot of preparation to write really robust floating-point code.
rawauthor: Pete Becker
rawtitle: The Journeyman's Shop: When Bad Things Happen to Good Numbers
bibsource:
http://www.cuj.com/articles/2000/0010/0010toc.htm?topic=articles; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Becker:2000:JSWb,
  author =       "Pete Becker",
  title =        "The Journeyman's Shop: When Bad Things Happen to Good
                 Numbers",
  journal =      j-CCCUJ,
  volume =       "18",
  number =       "10",
  pages =        "54--??",
  month =        oct,
  year =         "2000",
  CODEN =        "CCUJEX",
  ISSN =         "1075-2838",
  bibdate =      "Tue May 14 18:09:28 MDT 2002",
  bibsource =    "http://www.cuj.com/articles/2000/0010/0010toc.htm?topic=articles;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "It takes a lot of preparation to write really robust
                 floating-point code.",
  acknowledgement = ack-nhfb,
  fjournal =     "C/C++ Users Journal",
}


bibtype: article
filename: fparith.bib
label: Bertossi:2000:RNS
author: A. A. Bertossi and A. Mei
journal: j-IEEE-TRANS-PAR-DIST-SYS
volume: 11
number: 11
pages: 1186--1199
month: nov
monthnumber: 11
year: 2000
CODEN: ITDSEO
DOI: https://doi.org/10.1109/71.888638
ISSN: 1045-9219 (print), 1558-2183 (electronic) OR 10459219 (print), 15582183 (electronic)
ISSNL: 1045-9219 OR 10459219
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=19224
fjournal: IEEE Transactions on Parallel and Distributed Systems
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/tpds/archives.htm
rawauthor: A. A. Bertossi and A. Mei
title:
A residue number system on reconfigurable mesh with applications to prefix sums and approximate string matching

rawtitle:
A residue number system on reconfigurable mesh with applications to prefix sums and approximate string matching

entry:
@Article{Bertossi:2000:RNS,
  author =       "A. A. Bertossi and A. Mei",
  title =        "A residue number system on reconfigurable mesh with
                 applications to prefix sums and approximate string
                 matching",
  journal =      j-IEEE-TRANS-PAR-DIST-SYS,
  volume =       "11",
  number =       "11",
  pages =        "1186--1199",
  month =        nov,
  year =         "2000",
  CODEN =        "ITDSEO",
  DOI =          "https://doi.org/10.1109/71.888638",
  ISSN =         "1045-9219 (print), 1558-2183 (electronic)",
  ISSN-L =       "1045-9219",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=19224",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Parallel and Distributed
                 Systems",
  journal-URL =  "http://www.computer.org/tpds/archives.htm",
  keywords =     "residue arithmetic; residue number system",
  summary =      "Several new number representations based on a residue
                 number system are presented which use the smallest
                 prime numbers as moduli and are suited for parallel
                 computations on a reconfigurable mesh architecture. The
                 bit model of linear reconfigurable \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Boldo:2000:QDP
author: Sylvie Boldo
title: Quad double precision specification and proofs about the addition
type: Traineeship report -- MIM2
institution: University of California, Berkeley, and Ecole Normale Superieure de Lyon
address: Berkeley, CA, USA and 69364 Lyon Cedex 07, France
pages: 51
month: jun
monthnumber: 6
year: 2000
bibdate: Tue Nov 23 10:59:46 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.23 10:59:46 ???
note: Under the direction of Jonathan Shewchuk.
URL: http://perso.ens-lyon.fr/sylvie.boldo/doc/qd.ps
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo
rawnote: Under the direction of Jonathan Shewchuk.
rawtitle: Quad double precision specification and proofs about the addition
entry:
@TechReport{Boldo:2000:QDP,
  author =       "Sylvie Boldo",
  title =        "Quad double precision specification and proofs about
                 the addition",
  type =         "Traineeship report -- {MIM2}",
  institution =  "University of California, Berkeley, and {\'E}cole
                 Normale Sup{\'e}rieure de Lyon",
  address =      "Berkeley, CA, USA and 69364 Lyon Cedex 07, France",
  pages =        "51",
  month =        jun # "\slash " # aug,
  year =         "2000",
  bibdate =      "Tue Nov 23 10:59:46 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Under the direction of Jonathan Shewchuk.",
  URL =          "http://perso.ens-lyon.fr/sylvie.boldo/doc/qd.ps",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Brooks:2000:VBC
author: David Brooks and Margaret Martonosi
journal: j-TOCS
volume: 18
number: 2
pages: 89--126
month: may
monthnumber: 5
year: 2000
CODEN: ACSYEC
ISSN: 0734-2071 (print), 1557-7333 (electronic) OR 07342071 (print), 15577333 (electronic)
ISSNL: 0734-2071 OR 07342071
bibdate: Tue Sep 26 07:54:31 MDT 2000
bibsource: http://www.acm.org/pubs/contents/journals/tocs/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.09.26 07:54:31 MDT
URL: http://www.acm.org/pubs/citations/journals/tocs/2000-18-2/p89-brooks/
fjournal: ACM Transactions on Computer Systems
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J774
rawauthor: David Brooks and Margaret Martonosi
title:
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance

abstract:
The large address space needs of many current applications have pushed processor designs toward 64-bit word widths. Although full 64-bit addresses and operations are indeed sometimes needed, arithmetic operations on much smaller quantities are still more common. In fact, another instruction set trend has been the introduction of instructions geared toward subword operations on 16-bit quantities. For examples, most major processors now include instruction set support for multimedia operations allowing parallel execution of several subword operations in the same ALU. This article presents our observations demonstrating that operations on ``narrow-width'' quantities are common not only in multimedia codes, but also in more general workloads. In fact, across the SPECint95 benchmarks, over half the integer operation executions require 16 bits or less. Based on this data, we propose two hardware mechanisms that dynamically recognize and capitalize on these narrow-width operations. The first, power-oriented optimization reduces processor power consumption by using operand-value-based clock gating to turn off portions of arithmetic units that will be unused by narrow-width operations. This optimization results in a 45%--60% reduction in the integer unit's power consumption for the SPECint95 and MediaBench benchmark suites. Applying this optimization to SPECfp95 benchmarks results in slightly smaller power reductions, but still seems warranted. These reductions in integer unit power consumption equate to a 5%--10% full-chip power savings. Our second, performance-oriented optimization improves processor performance by packing together narrow-width operations so that they share a single arithmetic unit. Conceptually similar to a dynamic form of MMX, this optimization offers speedups of 4.3%--6.2% for SPECint95 and 8.0%--10.4% for MediaBench.par Overall, these optimizations highlight an increasing opportunity for value-based optimizations to improve both power and performance in current microprocessors.

subject:
Hardware --- Arithmetic and Logic Structures (B.2); Computer Systems Organization --- Processor Architectures --- Single Data Stream Architectures (C.1.1): bf RISC/CISC, VLIW architectures

rawabstract:
The large address space needs of many current applications have pushed processor designs toward 64-bit word widths. Although full 64-bit addresses and operations are indeed sometimes needed, arithmetic operations on much smaller quantities are still more common. In fact, another instruction set trend has been the introduction of instructions geared toward subword operations on 16-bit quantities. For examples, most major processors now include instruction set support for multimedia operations allowing parallel execution of several subword operations in the same ALU. This article presents our observations demonstrating that operations on ``narrow-width'' quantities are common not only in multimedia codes, but also in more general workloads. In fact, across the SPECint95 benchmarks, over half the integer operation executions require 16 bits or less. Based on this data, we propose two hardware mechanisms that dynamically recognize and capitalize on these narrow-width operations. The first, power-oriented optimization reduces processor power consumption by using operand-value-based clock gating to turn off portions of arithmetic units that will be unused by narrow-width operations. This optimization results in a 45\%--60\% reduction in the integer unit's power consumption for the SPECint95 and MediaBench benchmark suites. Applying this optimization to SPECfp95 benchmarks results in slightly smaller power reductions, but still seems warranted. These reductions in integer unit power consumption equate to a 5\%--10\% full-chip power savings. Our second, performance-oriented optimization improves processor performance by packing together narrow-width operations so that they share a single arithmetic unit. Conceptually similar to a dynamic form of MMX, this optimization offers speedups of 4.3\%--6.2\% for SPECint95 and 8.0\%--10.4\% for MediaBench.\par Overall, these optimizations highlight an increasing opportunity for value-based optimizations to improve both power and performance in current microprocessors.

rawtitle:
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance

entry:
@Article{Brooks:2000:VBC,
  author =       "David Brooks and Margaret Martonosi",
  title =        "Value-based clock gating and operation packing:
                 dynamic strategies for improving processor power and
                 performance",
  journal =      j-TOCS,
  volume =       "18",
  number =       "2",
  pages =        "89--126",
  month =        may,
  year =         "2000",
  CODEN =        "ACSYEC",
  ISSN =         "0734-2071 (print), 1557-7333 (electronic)",
  ISSN-L =       "0734-2071",
  bibdate =      "Tue Sep 26 07:54:31 MDT 2000",
  bibsource =    "http://www.acm.org/pubs/contents/journals/tocs/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/citations/journals/tocs/2000-18-2/p89-brooks/",
  abstract =     "The large address space needs of many current
                 applications have pushed processor designs toward
                 64-bit word widths. Although full 64-bit addresses and
                 operations are indeed sometimes needed, arithmetic
                 operations on much smaller quantities are still more
                 common. In fact, another instruction set trend has been
                 the introduction of instructions geared toward subword
                 operations on 16-bit quantities. For examples, most
                 major processors now include instruction set support
                 for multimedia operations allowing parallel execution
                 of several subword operations in the same ALU. This
                 article presents our observations demonstrating that
                 operations on ``narrow-width'' quantities are common
                 not only in multimedia codes, but also in more general
                 workloads. In fact, across the SPECint95 benchmarks,
                 over half the integer operation executions require 16
                 bits or less. Based on this data, we propose two
                 hardware mechanisms that dynamically recognize and
                 capitalize on these narrow-width operations. The first,
                 power-oriented optimization reduces processor power
                 consumption by using operand-value-based clock gating
                 to turn off portions of arithmetic units that will be
                 unused by narrow-width operations. This optimization
                 results in a 45\%--60\% reduction in the integer unit's
                 power consumption for the SPECint95 and MediaBench
                 benchmark suites. Applying this optimization to
                 SPECfp95 benchmarks results in slightly smaller power
                 reductions, but still seems warranted. These reductions
                 in integer unit power consumption equate to a 5\%--10\%
                 full-chip power savings. Our second,
                 performance-oriented optimization improves processor
                 performance by packing together narrow-width operations
                 so that they share a single arithmetic unit.
                 Conceptually similar to a dynamic form of MMX, this
                 optimization offers speedups of 4.3\%--6.2\% for
                 SPECint95 and 8.0\%--10.4\% for
                 MediaBench.\par

                 Overall, these optimizations highlight an increasing
                 opportunity for value-based optimizations to improve
                 both power and performance in current
                 microprocessors.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Computer Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J774",
  subject =      "Hardware --- Arithmetic and Logic Structures (B.2);
                 Computer Systems Organization --- Processor
                 Architectures --- Single Data Stream Architectures
                 (C.1.1): {\bf RISC/CISC, VLIW architectures}",
}


bibtype: inproceedings
filename: fparith.bib
label: Cardarilli:2000:RPD
author: G. C. Cardarilli and A. Nannarelli and M. Re
booktitle: Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, 2000
title: Reducing power dissipation in FIR filters using the residue number system
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 320--323
year: 2000
DOI: https://doi.org/10.1109/MWSCAS.2000.951651
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: G. C. Cardarilli and A. Nannarelli and M. Re
rawbooktitle: Proceedings of the 43rd {IEEE} Midwest Symposium on Circuits and Systems, 2000
rawtitle: Reducing power dissipation in {FIR} filters using the residue number system
entry:
@InProceedings{Cardarilli:2000:RPD,
  author =       "G. C. Cardarilli and A. Nannarelli and M. Re",
  booktitle =    "Proceedings of the 43rd {IEEE} Midwest Symposium on
                 Circuits and Systems, 2000",
  title =        "Reducing power dissipation in {FIR} filters using the
                 residue number system",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "320--323",
  year =         "2000",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MWSCAS.2000.951651",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The aim of this work is to reduce the power dissipated
                 in high order finite impulse response (FIR) filters,
                 while maintaining the delay unchanged. We compare in
                 terms of performance, area, and power dissipation the
                 implementation of a traditional \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chen:2000:PCV
author: Chichyang Chen and Rui-Lin Chen and Chih-Huan Yang
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 716--726
month: jul
monthnumber: 7
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863041
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 16 16:14:38 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2005.07.16 16:14:38 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Chichyang Chen and Rui-Lin Chen and Chih-Huan Yang
title:
Pipelined Computation of Very Large Word-Length LNS Addition / Subtraction with Polynomial Hardware Cost

rawtitle:
Pipelined Computation of Very Large Word-Length {LNS} Addition\slash Subtraction with Polynomial Hardware Cost

entry:
@Article{Chen:2000:PCV,
  author =       "Chichyang Chen and Rui-Lin Chen and Chih-Huan Yang",
  title =        "Pipelined Computation of Very Large Word-Length {LNS}
                 Addition\slash Subtraction with Polynomial Hardware
                 Cost",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "716--726",
  month =        jul,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863041",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 16 16:14:38 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
  summary =      "A novel pipelined method is proposed to compute the
                 addition/subtraction in very large word-length
                 logarithmic number system (LNS) arithmetic.
                 Digit-parallel additive-normalization and digit on-line
                 multiplicative-normalization methods are adopted
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Cheng:2000:STC
author: F.-C. Cheng and S. H. Unger and M. Theobald
title: Self-Timed Carry-Lookahead Adders
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 659--672
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863035
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:47:55 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:47:55 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: F.-C. Cheng and S. H. Unger and M. Theobald
rawtitle: Self-Timed Carry-Lookahead Adders
entry:
@Article{Cheng:2000:STC,
  author =       "F.-C. Cheng and S. H. Unger and M. Theobald",
  title =        "Self-Timed Carry-Lookahead Adders",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "659--672",
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863035",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:47:55 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
}


bibtype: techreport
filename: fparith.bib
label: Cheng:2000:TID
author: Y.-T. Cheng
title: TMS320C60000 integer division
type: Application Report
number: SPRA707
institution: Texas Instruments
address: Post Office box 655303, Dallas, TX 75265, USA
pages: 659--672
month: oct
monthnumber: 10
year: 2000
bibdate: Fri Sep 22 16:24:20 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 16:24:20 ???
URL: https://www.ti.com/lit/an/spra707/spra707.pdf
acknowledgement: ack-nhfb
rawauthor: Y.-T. Cheng
rawtitle: {TMS320C60000} integer division
entry:
@TechReport{Cheng:2000:TID,
  author =       "Y.-T. Cheng",
  title =        "{TMS320C60000} integer division",
  type =         "Application Report",
  number =       "SPRA707",
  institution =  "Texas Instruments",
  address =      "Post Office box 655303, Dallas, TX 75265, USA",
  month =        oct,
  year =         "2000",
  bibdate =      "Fri Sep 22 16:24:20 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.ti.com/lit/an/spra707/spra707.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Cherri:2000:PCC
author: A. K. Cherri and M. S. Alam
title: Parallel computation of complex elementary functions using quaternary signed-digit arithmetic
journal: Optics and Laser Technology
volume: 32
number: 6
publisher: Elsevier Science
pages: 391--399
year: 2000
ISSN: 0030-3992 OR 00303992
bibdate: Sat Dec 7 09:21:28 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.12.07 09:21:28 MST
acknowledgement: ack-nhfb
rawauthor: A. K. Cherri and M. S. Alam
rawtitle: Parallel computation of complex elementary functions using quaternary signed-digit arithmetic
entry:
@Article{Cherri:2000:PCC,
  author =       "A. K. Cherri and M. S. Alam",
  title =        "Parallel computation of complex elementary functions
                 using quaternary signed-digit arithmetic",
  journal =      "Optics and Laser Technology",
  volume =       "32",
  number =       "6",
  publisher =    "Elsevier Science",
  pages =        "391--399",
  year =         "2000",
  CODEN =        "????",
  ISSN =         "0030-3992",
  bibdate =      "Sat Dec 7 09:21:28 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  acknowledgement = ack-nhfb,
  pagecount =    "9",
}


bibtype: inproceedings
filename: fparith.bib
label: Chu:2000:CPT
author: Wanming Chu and Yamin Li
booktitle: ACAC 2000: 5th Australasian Computer Architecture Conference
title: Cost / performance tradeoff of $n$-select square root implementations
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 9--16
year: 2000
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: Wanming Chu and Yamin Li
rawbooktitle: {ACAC 2000}: 5th Australasian Computer Architecture Conference
rawtitle: Cost\slash performance tradeoff of $n$-select square root implementations
entry:
@InProceedings{Chu:2000:CPT,
  author =       "Wanming Chu and Yamin Li",
  booktitle =    "{ACAC 2000}: 5th Australasian Computer Architecture
                 Conference",
  title =        "Cost\slash performance tradeoff of $n$-select square
                 root implementations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "9--16",
  year =         "2000",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Hardware square-root units require large numbers of
                 gates even for iterative implementations. In this paper
                 we present four low-cost high-performance
                 fully-pipelined n-select implementations (nS-Root)
                 based on a non-restoring-remainder square root
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Coleman:2000:AEL
author: J. N. Coleman and E. I. Chester and C. I. Softley and J. Kadlec
title: Arithmetic on the European Logarithmic Microprocessor
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 702--715
month: jul
monthnumber: 7
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863040
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 10:35:24 MDT 2011
bibtimestamp: 2011.07.05 10:35:24 MDT
note: See corrections cite Coleman:2000:CAE.
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863040
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. N. Coleman and E. I. Chester and C. I. Softley and J. Kadlec
rawnote: See corrections \cite{Coleman:2000:CAE}.
rawtitle: Arithmetic on the {European Logarithmic Microprocessor}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib; OCLC Proceedings database

entry:
@Article{Coleman:2000:AEL,
  author =       "J. N. Coleman and E. I. Chester and C. I. Softley and
                 J. Kadlec",
  title =        "Arithmetic on the {European Logarithmic
                 Microprocessor}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "702--715",
  month =        jul,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863040",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 10:35:24 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib;
                 OCLC Proceedings database",
  note =         "See corrections \cite{Coleman:2000:CAE}.",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863040",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
}


bibtype: article
filename: fparith.bib
label: Coleman:2000:CAE
author: J. N. Coleman and E. I. Chester and C. I. Softley and J. Kadlec
title: Corrections to ``Arithmetic on the European Logarithmic Microprocessor''
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 10
pages: 1152--1152
month: oct
monthnumber: 10
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2000.888057
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 10:35:26 MDT 2011
bibtimestamp: 2011.07.05 10:35:26 MDT
note: See cite Coleman:2000:AEL.
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=888057
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. N. Coleman and E. I. Chester and C. I. Softley and J. Kadlec
rawnote: See \cite{Coleman:2000:AEL}.
rawtitle: Corrections to {``Arithmetic on the European Logarithmic Microprocessor''}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib

entry:
@Article{Coleman:2000:CAE,
  author =       "J. N. Coleman and E. I. Chester and C. I. Softley and
                 J. Kadlec",
  title =        "Corrections to {``Arithmetic on the European
                 Logarithmic Microprocessor''}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "10",
  pages =        "1152--1152",
  month =        oct,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2000.888057",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 10:35:26 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  note =         "See \cite{Coleman:2000:AEL}.",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=888057",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Collins:2000:MFP
author: George E. Collins and Werner Krandick
title: Multiprecision floating point addition
crossref: Traverso:2000:IAU
pages: 71--77
year: 2000
bibdate: Tue Apr 17 09:15:54 MDT 2001
bibtimestamp: 2001.04.17 09:15:54 MDT
keywords: FSUM; interval arithmetic; LEDA; MPADD; MPFUN; polynomial root finding
acknowledgement: ack-nhfb
rawauthor: George E. Collins and Werner Krandick
rawtitle: Multiprecision floating point addition
bibsource:
http://www.acm.org/pubs/contents/proceedings/series/issac/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www.acm.org/pubs/articles/proceedings/issac/345542/p71-collins/p71-collins.pdf; http://www.acm.org/pubs/citations/proceedings/issac/345542/p71-collins/

entry:
@InProceedings{Collins:2000:MFP,
  author =       "George E. Collins and Werner Krandick",
  title =        "Multiprecision floating point addition",
  crossref =     "Traverso:2000:IAU",
  pages =        "71--77",
  year =         "2000",
  bibdate =      "Tue Apr 17 09:15:54 MDT 2001",
  bibsource =    "http://www.acm.org/pubs/contents/proceedings/series/issac/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/articles/proceedings/issac/345542/p71-collins/p71-collins.pdf;
                 http://www.acm.org/pubs/citations/proceedings/issac/345542/p71-collins/",
  acknowledgement = ack-nhfb,
  keywords =     "FSUM; interval arithmetic; LEDA; MPADD; MPFUN;
                 polynomial root finding",
}


bibtype: inproceedings
filename: fparith.bib
label: Constantinides:2000:MPR
author: G. A. Constantinides and P. Y. K. Cheung and W. Luk
booktitle: IEEE Symposium on Field-Programmable Custom Computing Machines, 17--19 April 2000
title: Multiple precision for resource minimization
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 307--308
year: 2000
bibdate: Sat Jul 16 16:53:44 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:53:44 MDT
acknowledgement: ack-nhfb
rawauthor: G. A. Constantinides and P. Y. K. Cheung and W. Luk
rawbooktitle: {IEEE} Symposium on Field-Programmable Custom Computing Machines, 17--19 April 2000
rawtitle: Multiple precision for resource minimization
entry:
@InProceedings{Constantinides:2000:MPR,
  author =       "G. A. Constantinides and P. Y. K. Cheung and W. Luk",
  booktitle =    "{IEEE} Symposium on Field-Programmable Custom
                 Computing Machines, 17--19 April 2000",
  title =        "Multiple precision for resource minimization",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "307--308",
  year =         "2000",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:53:44 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Presents the Synoptix high-level synthesis and
                 precision optimization system for FPGAs. Given abstract
                 specifications in the form of infinite-precision signal
                 flow graphs and a set of error constraints, Synoptix
                 creates hardware descriptions of \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2000:IDR
author: M. Cornea and C. Iordache and J. Harrison and P. Markstein
booktitle: Fourth conference on Real numbers and Computers, Schloss Dagstuhl, April 2000
title: Integer divide and remainder operations in the IA-64 architecture
pages: ??--??
year: 2000
bibdate: Fri Sep 22 16:50:51 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 16:50:51 ???
URL: http://www.imada.sdu.dk/kornerup/RNC4/papers/p17.ps
remark: I cannot yet find this online.
acknowledgement: ack-nhfb
rawauthor: M. Cornea and C. Iordache and J. Harrison and P. Markstein
rawbooktitle: {Fourth conference on Real numbers and Computers, Schlo{\ss} Dagstuhl, April 2000}
rawtitle: Integer divide and remainder operations in the {IA-64} architecture
entry:
@InProceedings{Cornea:2000:IDR,
  author =       "M. Cornea and C. Iordache and J. Harrison and P.
                 Markstein",
  editor =       "????",
  booktitle =    "{Fourth conference on Real numbers and Computers,
                 Schlo{\ss} Dagstuhl, April 2000}",
  title =        "Integer divide and remainder operations in the {IA-64}
                 architecture",
  publisher =    "????",
  address =      "????",
  pages =        "??--??",
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Sep 22 16:50:51 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.imada.sdu.dk/kornerup/RNC4/papers/p17.ps",
  acknowledgement = ack-nhfb,
  remark =       "I cannot yet find this online.",
}


bibtype: article
filename: fparith.bib
label: Corsonello:2000:PCB
author: P. Corsonello and S. Perri and G. Cocorullo
volume: 147
number: 6
pages: 347--355
month: dec
monthnumber: 12
year: 2000
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: P. Corsonello and S. Perri and G. Cocorullo
title:
Performance comparison between static and dynamic CMOS logic implementations of a pipelined square-rooting circuit

journal:
Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems]

rawtitle:
Performance comparison between static and dynamic {CMOS} logic implementations of a pipelined square-rooting circuit

entry:
@Article{Corsonello:2000:PCB,
  author =       "P. Corsonello and S. Perri and G. Cocorullo",
  title =        "Performance comparison between static and dynamic
                 {CMOS} logic implementations of a pipelined
                 square-rooting circuit",
  journal =      "Circuits, Devices and Systems, IEE Proceedings [see
                 also IEE Proceedings G- Circuits, Devices and
                 Systems]",
  volume =       "147",
  number =       "6",
  pages =        "347--355",
  month =        dec,
  year =         "2000",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Pipelined cellular array implementations of arithmetic
                 circuits are usually adopted to obtain high throughput
                 at reasonable cost. The circuit design style used to
                 implement the array greatly influences both performance
                 and cost. The designer has to \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: DAmora:2000:RPD
author: A. D'Amora and A. Nannarelli and M. Re and G. C. Cardarilli
booktitle: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, 2000
title: Reducing power dissipation in complex digital filters by using the quadratic residue number system
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 879--883
year: 2000
DOI: https://doi.org/10.1109/ACSSC.2000.910639
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. D'Amora and A. Nannarelli and M. Re and G. C. Cardarilli
rawbooktitle: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, 2000
rawtitle: Reducing power dissipation in complex digital filters by using the quadratic residue number system
entry:
@InProceedings{DAmora:2000:RPD,
  author =       "A. D'Amora and A. Nannarelli and M. Re and G. C.
                 Cardarilli",
  booktitle =    "Conference Record of the Thirty-Fourth Asilomar
                 Conference on Signals, Systems and Computers, 2000",
  title =        "Reducing power dissipation in complex digital filters
                 by using the quadratic residue number system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "879--883",
  year =         "2000",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ACSSC.2000.910639",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper compares in terms of performance, area and
                 power dissipation, a complex FIR filter realized in the
                 traditional two's complement system with a Quadratic
                 Residue Number System (QRNS) based one. The resulting
                 implementations, designed to \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Daumas:2000:EIT
author: Marc Daumas and Claire Moreau-Finot
booktitle: Real Numbers and Computers, Dagstuhl, Germany, 2000
title: Exponential: implementation trade-offs for hundred bit precision
pages: 61--74
year: 2000
bibdate: Wed Nov 24 12:44:20 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.24 12:44:20 ???
acknowledgement: ack-nhfb
rawauthor: Marc Daumas and Claire Moreau-Finot
rawbooktitle: Real Numbers and Computers, Dagstuhl, Germany, 2000
rawtitle: Exponential: implementation trade-offs for hundred bit precision
entry:
@InProceedings{Daumas:2000:EIT,
  author =       "Marc Daumas and Claire Moreau-Finot",
  editor =       "????",
  booktitle =    "Real Numbers and Computers, Dagstuhl, Germany, 2000",
  title =        "Exponential: implementation trade-offs for hundred bit
                 precision",
  publisher =    "????",
  address =      "????",
  pages =        "61--74",
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Wed Nov 24 12:44:20 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Delves:2000:MUI
author: L. M. Delves
title: Making Use of IEEE Arithmetic Facilities
journal: j-FORTRAN-FORUM
volume: 19
number: 3
pages: 9--12
month: dec
monthnumber: 12
year: 2000
DOI: https://doi.org/10.1145/570899.570902
ISSN: 1061-7264 (print), 1931-1311 (electronic) OR 10617264 (print), 19311311 (electronic)
ISSNL: 1061-7264 OR 10617264
bibdate: Wed Jun 18 16:26:21 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.18 16:26:21 MDT
fjournal: ACM Fortran Forum
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/toc.cfm?id=J286
issue: 59
rawauthor: L. M. Delves
rawtitle: Making Use of {IEEE} Arithmetic Facilities
entry:
@Article{Delves:2000:MUI,
  author =       "L. M. Delves",
  title =        "Making Use of {IEEE} Arithmetic Facilities",
  journal =      j-FORTRAN-FORUM,
  volume =       "19",
  number =       "3",
  pages =        "9--12",
  month =        dec,
  year =         "2000",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/570899.570902",
  ISSN =         "1061-7264 (print), 1931-1311 (electronic)",
  ISSN-L =       "1061-7264",
  bibdate =      "Wed Jun 18 16:26:21 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Fortran Forum",
  issue =        "59",
  journal-URL =  "http://portal.acm.org/toc.cfm?id=J286",
}


bibtype: article
filename: fparith.bib
label: Drmac:2000:AQS
author: Zlatko Drmac and Elizabeth R. Jessup
title: On accurate quotient singular value computation in floating-point arithmetic
journal: j-SIAM-J-MAT-ANA-APPL
volume: 22
number: 3
pages: 853--873
year: 2000
CODEN: SJMAEL
ISSN: 0895-4798 (print), 1095-7162 (electronic) OR 08954798 (print), 10957162 (electronic)
ISSNL: 0895-4798 OR 08954798
MRclass: 65F15 (65G20)
MRnumber: MR1799528 (2001j:65062)
MRreviewer: Fabio Di Benedetto
bibdate: Thu Nov 8 19:32:13 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:32:13 ???
fjournal: SIAM Journal on Matrix Analysis and Applications
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/simax
rawauthor: Zlatko Drma{\v{c}} and Elizabeth R. Jessup
rawtitle: On accurate quotient singular value computation in floating-point arithmetic
entry:
@Article{Drmac:2000:AQS,
  author =       "Zlatko Drma{\v{c}} and Elizabeth R. Jessup",
  title =        "On accurate quotient singular value computation in
                 floating-point arithmetic",
  journal =      j-SIAM-J-MAT-ANA-APPL,
  volume =       "22",
  number =       "3",
  pages =        "853--873",
  year =         "2000",
  CODEN =        "SJMAEL",
  ISSN =         "0895-4798 (print), 1095-7162 (electronic)",
  ISSN-L =       "0895-4798",
  MRclass =      "65F15 (65G20)",
  MRnumber =     "MR1799528 (2001j:65062)",
  MRreviewer =   "Fabio Di Benedetto",
  bibdate =      "Thu Nov 8 19:32:13 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Matrix Analysis and Applications",
  journal-URL =  "http://epubs.siam.org/simax",
}


bibtype: article
filename: fparith.bib
label: Ercegovac:2000:IGD
author: Milos D. Ercegovac and Laurent Imbert and David W. Matula and Jean-Michel Muller and Guoheng Wei
title: Improving Goldschmidt Division, Square Root, and Square Root Reciprocal
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 759--763
month: jul
monthnumber: 7
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863046
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 10:35:25 MDT 2011
bibtimestamp: 2011.07.05 10:35:25 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863046
fjournal: IEEE Transactions on Computers
keywords: ARITH-14; correct rounding; floating-point arithmetic
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Improving {Goldschmidt} Division, Square Root, and Square Root Reciprocal
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib; OCLC Proceedings database

rawauthor:
Milo{\v{s}} D. Ercegovac and Laurent Imbert and David W. Matula and Jean-Michel Muller and Guoheng Wei

entry:
@Article{Ercegovac:2000:IGD,
  author =       "Milo{\v{s}} D. Ercegovac and Laurent Imbert and David
                 W. Matula and Jean-Michel Muller and Guoheng Wei",
  title =        "Improving {Goldschmidt} Division, Square Root, and
                 Square Root Reciprocal",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "759--763",
  month =        jul,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863046",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 10:35:25 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib;
                 OCLC Proceedings database",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863046",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14; correct rounding; floating-point
                 arithmetic",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
  remark-2 =     "From the first column: ``These methods do not directly
                 produce the remainder and correct rounding (as required
                 by the IEEE-754 standard [8]) requires extra quotient
                 digits. According to [7], roughly twice as many digits
                 of intermediate result are needed as in the final
                 result unless the iterations are performed using a
                 fused multiply-accumulate operator [1].''",
  summary =      "The aim of this paper is to accelerate division,
                 square root, and square root reciprocal computations
                 when the Goldschmidt method is used on a pipelined
                 multiplier. This is done by replacing the last
                 iteration by the addition of a correcting term that can
                 be looked up during the early iterations. We describe
                 several variants of the Goldschmidt algorithm, assuming
                 4-cycle pipelined multiplier, and discuss obtained
                 number of cycles and error achieved. Extensions to
                 other than 4-cycle multipliers are given. If we call
                 $G_m$ the Goldschmidt algorithm with $m$ iterations,
                 our variants allow us to reach an accuracy that is
                 between that of $G_3$ and that of $G_4$, with a number
                 of cycles equal to that of $G_3$.",
}


bibtype: article
filename: fparith.bib
label: Ercegovac:2000:RSR
author: Milos D. Ercegovac and Tomas Lang and Jean-Michel Muller and Arnaud Tisserand
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 628--637
month: jul
monthnumber: 7
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863031
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
MRclass: 68M07 (65B15)
MRnumber: MR1783602 (2001e:68016)
bibdate: Tue Jul 5 10:35:24 MDT 2011
bibtimestamp: 2011.07.05 10:35:24 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863031
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Milo{\v{s}} D. Ercegovac and Tom{\'a}s Lang and Jean-Michel Muller and Arnaud Tisserand
title:
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib; OCLC Proceedings database

rawtitle:
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers

entry:
@Article{Ercegovac:2000:RSR,
  author =       "Milo{\v{s}} D. Ercegovac and Tom{\'a}s Lang and
                 Jean-Michel Muller and Arnaud Tisserand",
  title =        "Reciprocation, Square Root, Inverse Square Root, and
                 Some Elementary Functions Using Small Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "628--637",
  month =        jul,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863031",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  MRclass =      "68M07 (65B15)",
  MRnumber =     "MR1783602 (2001e:68016)",
  bibdate =      "Tue Jul 5 10:35:24 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib;
                 OCLC Proceedings database",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863031",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
  summary =      "This paper deals with the computation of reciprocals,
                 square roots, inverse square roots, and some elementary
                 functions using small tables, small multipliers, and,
                 for some functions, a final ``large'' (almost
                 full-length) multiplication. \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Eskritt:2000:DDF
author: J. Eskritt and R. Muscedere and G. A. Jullien and V. S. Dimitrov and W. C. Miller
editor: Magdy A. Bayoumi and Eby G. Friedman
title: A 2-Digit DBNS Filter Architecture
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 447--456
year: 2000
DOI: https://doi.org/10.1109/SIPS.2000.886743
ISBN: 0-7803-6488-0 OR 0780364880
ISBN13: 978-0-7803-6488-2 OR 9780780364882
LCCN: TK7874 .S58 2000
bibdate: Sat May 14 17:26:55 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.05.14 17:26:55 ???
keywords: Double-Based Number System (DBNS)
acknowledgement: ack-nhfb
bookpages: xv + 836
rawauthor: J. Eskritt and R. Muscedere and G. A. Jullien and V. S. Dimitrov and W. C. Miller
raweditor: Magdy A. Bayoumi and Eby G. Friedman
rawtitle: A 2-Digit {DBNS} Filter Architecture
booktitle:
SiPS 2000: 2000 IEEE Workshop on Signal Processing Systems: design and implementation: 11--13 October 2000: Lafayette, Louisiana

rawbooktitle:
{SiPS 2000: 2000 IEEE Workshop on Signal Processing Systems: design and implementation: 11--13 October 2000: Lafayette, Louisiana}

entry:
@InProceedings{Eskritt:2000:DDF,
  author =       "J. Eskritt and R. Muscedere and G. A. Jullien and V.
                 S. Dimitrov and W. C. Miller",
  editor =       "Magdy A. Bayoumi and Eby G. Friedman",
  booktitle =    "{SiPS 2000: 2000 IEEE Workshop on Signal Processing
                 Systems: design and implementation: 11--13 October
                 2000: Lafayette, Louisiana}",
  title =        "A 2-Digit {DBNS} Filter Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "xv + 836",
  pages =        "447--456",
  year =         "2000",
  DOI =          "https://doi.org/10.1109/SIPS.2000.886743",
  ISBN =         "0-7803-6488-0",
  ISBN-13 =      "978-0-7803-6488-2",
  LCCN =         "TK7874 .S58 2000",
  bibdate =      "Sat May 14 17:26:55 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Double-Based Number System (DBNS)",
}


bibtype: article
filename: fparith.bib
label: Even:2000:CTR
author: G. Even and P.-M. Seidel
title: A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 638--650
month: jul
monthnumber: 7
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863033
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 10:35:24 MDT 2011
bibtimestamp: 2011.07.05 10:35:24 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863033
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: G. Even and P.-M. Seidel
rawtitle: A Comparison of Three Rounding Algorithms for {IEEE} Floating-Point Multiplication
entry:
@Article{Even:2000:CTR,
  author =       "G. Even and P.-M. Seidel",
  title =        "A Comparison of Three Rounding Algorithms for {IEEE}
                 Floating-Point Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "638--650",
  month =        jul,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863033",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 10:35:24 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib;
                 OCLC Proceedings database",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863033",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
  summary =      "A new IEEE compliant floating-point rounding algorithm
                 for computing the rounded product from a carry-save
                 representation of the product is presented. The new
                 rounding algorithm is compared with the rounding
                 algorithms of Yu and Zyner (1995) and of \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Even:2000:DIC
author: G. Even and W. J. Paul
title: On the design of IEEE compliant floating point units
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 5
pages: 398--413
month: may
monthnumber: 5
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.859536
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
MRclass: 68M07
MRnumber: MR1764655
bibdate: Tue Jul 5 10:35:24 MDT 2011
bibtimestamp: 2011.07.05 10:35:24 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=859536
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: G. Even and W. J. Paul
rawtitle: On the design of {IEEE} compliant floating point units
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib

entry:
@Article{Even:2000:DIC,
  author =       "G. Even and W. J. Paul",
  title =        "On the design of {IEEE} compliant floating point
                 units",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "5",
  pages =        "398--413",
  month =        may,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.859536",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  MRclass =      "68M07",
  MRnumber =     "MR1764655",
  bibdate =      "Tue Jul 5 10:35:24 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=859536",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "Engineering design methodology recommends designing a
                 system as follows: Start with an unambiguous
                 specification, partition the system into blocks,
                 specify the functionality of each block, design each
                 block separately, and glue the blocks together.
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Even:2000:DPI
author: G. Even and S. M. Mueller and P.-M. Seidel
title: A dual precision IEEE floating-point multiplier
journal: j-INTEGRATION-VLSI-J
volume: 29
number: 2
publisher: Elsevier Science
pages: 167--180
month: sep
monthnumber: 9
year: 2000
CODEN: IVJODL
ISSN: 0167-9260 (print), 1872-7522 (electronic) OR 01679260 (print), 18727522 (electronic)
ISSNL: 0167-9260 OR 01679260
bibdate: Fri Nov 8 05:39:32 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.11.08 05:39:32 MST
fjournal: Integration, the VLSI journal
acknowledgement: ack-nhfb
rawauthor: G. Even and S. M. Mueller and P.-M. Seidel
rawtitle: A dual precision {IEEE} floating-point multiplier
entry:
@Article{Even:2000:DPI,
  author =       "G. Even and S. M. Mueller and P.-M. Seidel",
  title =        "A dual precision {IEEE} floating-point multiplier",
  journal =      j-INTEGRATION-VLSI-J,
  volume =       "29",
  number =       "2",
  publisher =    "Elsevier Science",
  pages =        "167--180",
  month =        sep,
  year =         "2000",
  CODEN =        "IVJODL",
  ISSN =         "0167-9260 (print), 1872-7522 (electronic)",
  ISSN-L =       "0167-9260",
  bibdate =      "Fri Nov 8 05:39:32 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  acknowledgement = ack-nhfb,
  fjournal =     "Integration, the VLSI journal",
  pagecount =    "14",
}


bibtype: inproceedings
filename: fparith.bib
label: Ferguson:2000:IRM
author: M. I. Ferguson and M. D. Ercegovac
booktitle: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, 2000
title: The IEEE rounding for multiplier with redundant operands
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1334--1338
year: 2000
bibdate: Sat Jul 16 11:25:05 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:05 MDT
acknowledgement: ack-nhfb
rawauthor: M. I. Ferguson and M. D. Ercegovac
rawbooktitle: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, 2000
rawtitle: The {IEEE} rounding for multiplier with redundant operands
entry:
@InProceedings{Ferguson:2000:IRM,
  author =       "M. I. Ferguson and M. D. Ercegovac",
  booktitle =    "Conference Record of the Thirty-Fourth Asilomar
                 Conference on Signals, Systems and Computers, 2000",
  title =        "The {IEEE} rounding for multiplier with redundant
                 operands",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1334--1338",
  year =         "2000",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:05 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "We present a design for a multiplier with redundant
                 operands which conforms to the IEEE-754 floating-point
                 standard. The design consists of a multiplier core and
                 a rounding unit which conforms to the rounding modes
                 specified by the IEEE standard and \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Fernandez:2000:FRB
author: Pedro G. Fernandez and Antonio Garcia and Javier Ramirez and Luis Parrilla and Antonio Lloris
title: Fast RNS-based DCT Computation with Fewer Multiplication Stages
crossref: Anonymous:2000:DPX
pages: 276--281
year: 2000
bibdate: Fri Jun 24 18:22:06 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 18:22:06 ???
URL: http://ditec.ugr.es/~grios/papers/dcis00_dct.pdf
keywords: Discrete Cosine Transform (DCT); Residue Number System (RNS)
acknowledgement: ack-nhfb
rawtitle: Fast {RNS}-based {DCT} Computation with Fewer Multiplication Stages
rawauthor:
Pedro G. Fern{\'a}ndez and Anton{\'\i}o Garc{\'\i}a and Javier Ram{\'\i}rez and Luis Parrilla and Anton{\'\i}o Lloris

entry:
@InProceedings{Fernandez:2000:FRB,
  author =       "Pedro G. Fern{\'a}ndez and Anton{\'\i}o Garc{\'\i}a
                 and Javier Ram{\'\i}rez and Luis Parrilla and
                 Anton{\'\i}o Lloris",
  title =        "Fast {RNS}-based {DCT} Computation with Fewer
                 Multiplication Stages",
  crossref =     "Anonymous:2000:DPX",
  pages =        "276--281",
  year =         "2000",
  bibdate =      "Fri Jun 24 18:22:06 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ditec.ugr.es/~grios/papers/dcis00_dct.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "Discrete Cosine Transform (DCT); Residue Number System
                 (RNS)",
}


bibtype: article
filename: fparith.bib
label: Fey:2000:DPA
author: Dietmar Fey and Marko Degenkolb
title: Digit Pipelined Arithmetic for $3$-D Massively Parallel Optoelectronic Circuits
journal: j-J-SUPERCOMPUTING
volume: 16
number: 3
pages: 177--196
month: jul
monthnumber: 7
year: 2000
CODEN: JOSUED
DOI: https://doi.org/10.1023/A:1008160925753
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Wed Jul 6 12:13:14 MDT 2005
bibtimestamp: 2005.07.06 12:13:14 MDT
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: Dietmar Fey and Marko Degenkolb
rawtitle: Digit Pipelined Arithmetic for {$3$-D} Massively Parallel Optoelectronic Circuits
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0920-8542&volume=16&issue=3; http://www.wkap.nl/issuetoc.htm/0920-8542+16+3+2000; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www.springerlink.com/openurl.asp?genre=article&issn=0920-8542&volume=16&issue=3&spage=177; http://www.wkap.nl/oasis.htm/262637

entry:
@Article{Fey:2000:DPA,
  author =       "Dietmar Fey and Marko Degenkolb",
  title =        "Digit Pipelined Arithmetic for {$3$-D} Massively
                 Parallel Optoelectronic Circuits",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "16",
  number =       "3",
  pages =        "177--196",
  month =        jul,
  year =         "2000",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1023/A:1008160925753",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Wed Jul 6 12:13:14 MDT 2005",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0920-8542&volume=16&issue=3;
                 http://www.wkap.nl/issuetoc.htm/0920-8542+16+3+2000;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0920-8542&volume=16&issue=3&spage=177;
                 http://www.wkap.nl/oasis.htm/262637",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: phdthesis
filename: fparith.bib
label: FigueroadelCid:2000:RFF
author: Samuel Figueroa del Cid
type: Ph.D. Thesis
school: Department of Computer Science, New York University
address: New York, NY, USA
pages: 345
month: jan
monthnumber: 1
year: 2000
ISBN: 0-599-59894-8 OR 0599598948
ISBN13: 978-0-599-59894-2 OR 9780599598942
bibdate: Fri Oct 25 17:16:24 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.10.25 17:16:24 ???
keywords: double rounding
acknowledgement: ack-nhfb
rawauthor: Samuel {Figueroa del Cid}
title:
A Rigorous Framework for Fully Supporting the IEEE Standard for Floating-Point Arithmetic in High-Level Programming Languages

URL:
http://www.cs.nyu.edu/csweb/Research/theses.html; http://www.cs.nyu.edu/csweb/Research/Theses/figueroa_sam.html; http://www.cs.nyu.edu/csweb/Research/Theses/figueroa_sam.pdf; http://www.cs.nyu.edu/csweb/Research/Theses/figueroa_sam.ps.gz; http://wwwlib.umi.com/dissertations/fullcit/9956669; http://wwwlib.umi.com/dissertations/preview/9956669

abstract:
Processors conforming to the IEEE Standard for Floating-Point Arithmetic have been commonplace for some years, and now several programming languages seem to support or conform to this standard, from hereon referred to as ``the IEEE Standard.'' For example, The Java Language Specification by Gosling, Joy, and Steele, which defines the Java language, frequently mentions the IEEE Standard. Indeed, Java, as do other languages, supports some of the features of the IEEE Standard, including a couple floating-point data formats, and even requires (in section 4.2.4 ``Floating-Point Operations'' of the aforementioned book) that ``operators on floating-point numbers behave exactly as specified by IEEE 754.'' Arguing that the support current languages offer is not enough, this thesis establishes clear criteria for what it means to fully support the IEEE Standard in a programming language. Each aspect of the IEEE Standard is examined in detail from the point of view of how various arithmetic engines implement that aspect of the IEEE Standard, how different languages (and implementations thereof) support it, and what the range of options are in supporting that aspect. Practical recommendations are then offered (particularly, but not exclusively, for Ada and Java), taking, for example, programmer convenience and impact on performance into consideration. A detailed model specification following these recommendations is provided for the Ada language. In addition, a variety of issues related to the floating-point aspects of programming languages are discussed, so as to serve as a more complete guide to language designers. One such issue is floating-point expression evaluation schemes, and, more specifically, whether bit-for-bit identical results are actually achievable on a variety of platforms that conform to the IEEE Standard, as the Java language promises. Closely tied to this issue is that of double rounding, which occurs when a (possibly intermediate) result is rounded more than once before subsequent use or before being delivered to its final destination. So this thesis discusses when double rounding makes a difference, how it can be avoided, and what the performance impact is in avoiding it.

TOC:
List of Tables / vii 1 Introduction / 1 1.1 The IEEE Standard for Floating-Point Arithmetic / 1 1.2 What does it mean to support the IEEE Standard? / 2 1.3 Considerations in deciding how to support the IEEE Standard in high-level languages / 2 1.4 Prior Related Work / 3 2 What Does It Mean to Support the IEEE Standard? / 5 3 Supporting Data Formats in High-Level Languages / 9 3.1 IEEE Standard requirements in regards to data formats / 9 3.2 Hardware facilities supporting data formats / 10 3.3 Making data formats available in high-level languages / 11 3.4 Associating floating-point literals with data formats / 13 3.5 Other issues related to numeric literals / 13 3.6 Issues related to mixed-language programming / 14 3.7 What support exists in high-level languages / 15 3.7.1 Traditional language designs / 15 3.7.2 Implementations of traditional languages / 16 3.7.3 Extensions to traditional languages / 16 3.7.4 New language designs / 17 3.8 What support should exist in high-level languages / 17 4 Supporting Rounding Modes in High-Level Languages / 21 4.1 IEEE Standard requirements in regards to rounding modes / 21 4.2 Hardware facilities for accessing rounding modes / 22 4.2.1 Processors with dynamic rounding modes / 22 4.2.2 Processors with static rounding modes / 24 4.3 Making rounding modes available in high-level languages / 25 4.4 Handling static evaluation and numeric literals / 27 4.5 Issues related to mixed-language programming / 29 4.6 What support exists in high-level languages / 30 4.6.1 Existing language designs / 30 4.6.2 Compilers for existing languages / 30 4.6.3 Extensions to existing languages / 30 4.6.4 New language designs / 31 4.7 Why having more than one rounding mode available is useful / 32 4.8 What support should exist in high-level languages / 33 5 Supporting Precision Modes in High-Level Languages / 35 5.1 IEEE Standard requirements in regards to precision modes / 35 5.2 Hardware facilities for accessing precision modes / 36 5.2.1 Processors with dynamic precision modes / 36 5.2.2 Processors with static precision modes / 36 5.2.3 Processors without precision modes / 38 5.3 Different ways of making precision modes available in a high-level language / 39 5.4 Handling static evaluation and numeric literals / 39 5.5 Issues related to mixed-language programming / 39 5.6 What support exists in high-level languages / 39 5.6.1 Compilers for existing languages / 39 5.6.2 Extensions to existing languages / 39 5.6.3 Experimental language designs / 40 5.7 Why it is useful to be able to change the precision mode / 41 5.8 Why compiler support is required in order to avoid double rounding / 42 5.9 What support should exist in high-level languages / 43 6 Double Rounding / 47 6.1 Why double rounding can be undesirable / 48 6.2 When is double rounding innocuous? / 50 6.2.1 Addition / 51 6.2.2 Subtraction / 52 6.2.3 Multiplication / 53 6.2.4 Division / 54 6.2.5 Square root / 55 6.2.6 Additional comments / 57 6.3 On avoiding double rounding / 58 6.4 Practical ways of avoiding double rounding / 60 7 Supporting the Standard Operations in High-Level Languages / 63 7.1 IEEE Standard requirements in regards to operations / 63 7.2 How different architectures implement these operations / 66 7.2.1 CISC architectures / 66 7.2.2 RISC architectures / 68 7.2.3 How different architectures implement comparison / 69 7.3 Making the standard operations available in high-level languages / 70 7.4 Handling static evaluation / 72 7.5 What support exists in high-level languages / 72 7.5.1 Existing language designs / 72 7.5.2 Compilers for existing languages / 74 7.5.3 Extensions to existing languages / 74 7.5.4 New language designs / 75 7.6 What support should exist in high-level languages / 76 8 Supporting Exceptional Situations in High-Level Languages / 79 8.1 IEEE Standard requirements in regards to special computational situations / 79 8.2 Different architectures' support for exceptional situations / 81 8.2.1 CISC architectures / 81 8.2.2 RISC architectures / 84 8.2.3 How different architectures distinguish between signaling and quiet NaNs / 87 8.2.4 How different architectures detect underflow / 88 8.3 Handling special computational situations in high-level languages / 89 8.3.1 Ways of representing special values / 89 8.3.2 Handling static evaluation and numeric literals / 90 8.3.3 Supporting arithmetic involving special computational situations / 91 8.3.4 Ways of allowing access to status flags / 92 8.3.5 Ways of managing the status flags / 93 8.3.6 Facilities for exception handling / 95 8.4 Issues related to mixed-language programming / 96 8.5 What support exists in high-level languages / 97 8.5.1 Existing language designs / 97 8.5.2 Compilers for existing languages / 98 8.5.3 Extensions to existing languages / 98 8.5.4 New language designs / 99 8.6 What support should exist in high-level languages / 100 9 Floating-Point Expression Evaluation Schemes / 105 9.1 Predictable expression evaluation schemes / 106 9.2 Advantages and disadvantages of various evaluation schemes / 106 9.3 Bit-for-bit identical results and the IEEE Standard / 108 9.3.1 Optional and implementation defined features of the IEEE Standard / 108 9.3.2 Are bit-for-bit identical results achievable in Java? / 110 10 Supporting the IEEE Standard in Ada and Java / 113 10.1 Ada / 114 10.1.1 Data formats / 114 10.1.2 Rounding and rounding precision modes / 114 10.1.3 Operations / 114 10.1.4 Exceptional situations / 115 10.1.5 Expression evaluation / 117 10.1.6 Pragmas related to floating-point arithmetic / 117 10.2 Java / 118 10.2.1 Data formats / 118 10.2.2 Rounding and (rounding) precision modes / 119 10.2.3 Operations / 120 10.2.4 Exceptional situations / 120 11 Conclusion / 123 11.1 How well current languages support the IEEE Standard / 123 11.2 Related unfinished work and open issues / 126 A Supporting the IEEE Standard in Ada / 127 A.1 The Package Standard FP Arithmetic / 127 A.1.1 Data Formats / 130 A.1.2 Operations of Floating-Point Types / 131 A.1.3 Rounding Modes / 132 A.1.4 Status Flags / 132 A.1.5 Trap Handlers / 132 A.2 Floating-Point Operations / 132 A.2.1 The Package Generic FP Operations / 132 A.2.2 Required Functions and Predicates / 136 A.2.3 Recommended Functions and Predicate / 138 A.3 Model of Floating-Point Arithmetic / 138 A.3.1 Floating-Point Evaluation Format / 139 A.3.2 Exception Handling / 139 A.4 Pragmas Related to Floating-Point Arithmetic / 144 A.4.1 Pragmas Related to the Accuracy of Results / 144 A.4.2 Pragmas Related to Rounding Modes / 146 A.4.3 Other Pragmas / 148 Bibliography / 151

rawabstract:
Processors conforming to the IEEE Standard for Floating-Point Arithmetic have been commonplace for some years, and now several programming languages seem to support or conform to this standard, from hereon referred to as ``the IEEE Standard.'' For example, The Java Language Specification by Gosling, Joy, and Steele, which defines the Java language, frequently mentions the IEEE Standard. Indeed, Java, as do other languages, supports some of the features of the IEEE Standard, including a couple floating-point data formats, and even requires (in section 4.2.4 ``Floating-Point Operations'' of the aforementioned book) that ``operators on floating-point numbers behave exactly as specified by IEEE 754.'' Arguing that the support current languages offer is not enough, this thesis establishes clear criteria for what it means to fully support the IEEE Standard in a programming language. Each aspect of the IEEE Standard is examined in detail from the point of view of how various arithmetic engines implement that aspect of the IEEE Standard, how different languages (and implementations thereof) support it, and what the range of options are in supporting that aspect. Practical recommendations are then offered (particularly, but not exclusively, for Ada and Java), taking, for example, programmer convenience and impact on performance into consideration. A detailed model specification following these recommendations is provided for the Ada language. In addition, a variety of issues related to the floating-point aspects of programming languages are discussed, so as to serve as a more complete guide to language designers. One such issue is floating-point expression evaluation schemes, and, more specifically, whether bit-for-bit identical results are actually achievable on a variety of platforms that conform to the IEEE Standard, as the Java language promises. Closely tied to this issue is that of double rounding, which occurs when a (possibly intermediate) result is rounded more than once before subsequent use or before being delivered to its final destination. So this thesis discusses when double rounding makes a difference, how it can be avoided, and what the performance impact is in avoiding it.

rawtitle:
A Rigorous Framework for Fully Supporting the {IEEE Standard} for Floating-Point Arithmetic in High-Level Programming Languages

rawTOC:
List of Tables / vii \\ 1 Introduction / 1 \\ 1.1 The IEEE Standard for Floating-Point Arithmetic / 1 \\ 1.2 What does it mean to support the IEEE Standard? / 2 \\ 1.3 Considerations in deciding how to support the IEEE Standard in high-level languages / 2 \\ 1.4 Prior Related Work / 3 \\ 2 What Does It Mean to Support the IEEE Standard? / 5 \\ 3 Supporting Data Formats in High-Level Languages / 9 \\ 3.1 IEEE Standard requirements in regards to data formats / 9 \\ 3.2 Hardware facilities supporting data formats / 10 \\ 3.3 Making data formats available in high-level languages / 11 \\ 3.4 Associating floating-point literals with data formats / 13 \\ 3.5 Other issues related to numeric literals / 13 \\ 3.6 Issues related to mixed-language programming / 14 \\ 3.7 What support exists in high-level languages / 15 \\ 3.7.1 Traditional language designs / 15 \\ 3.7.2 Implementations of traditional languages / 16 \\ 3.7.3 Extensions to traditional languages / 16 \\ 3.7.4 New language designs / 17 \\ 3.8 What support should exist in high-level languages / 17 \\ 4 Supporting Rounding Modes in High-Level Languages / 21 \\ 4.1 IEEE Standard requirements in regards to rounding modes / 21 \\ 4.2 Hardware facilities for accessing rounding modes / 22 \\ 4.2.1 Processors with dynamic rounding modes / 22 \\ 4.2.2 Processors with static rounding modes / 24 \\ 4.3 Making rounding modes available in high-level languages / 25 \\ 4.4 Handling static evaluation and numeric literals / 27 \\ 4.5 Issues related to mixed-language programming / 29 \\ 4.6 What support exists in high-level languages / 30 \\ 4.6.1 Existing language designs / 30 \\ 4.6.2 Compilers for existing languages / 30 \\ 4.6.3 Extensions to existing languages / 30 \\ 4.6.4 New language designs / 31 \\ 4.7 Why having more than one rounding mode available is useful / 32 \\ 4.8 What support should exist in high-level languages / 33 \\ 5 Supporting Precision Modes in High-Level Languages / 35 \\ 5.1 IEEE Standard requirements in regards to precision modes / 35 \\ 5.2 Hardware facilities for accessing precision modes / 36 \\ 5.2.1 Processors with dynamic precision modes / 36 \\ 5.2.2 Processors with static precision modes / 36 \\ 5.2.3 Processors without precision modes / 38 \\ 5.3 Different ways of making precision modes available in a high-level language / 39 \\ 5.4 Handling static evaluation and numeric literals / 39 \\ 5.5 Issues related to mixed-language programming / 39 \\ 5.6 What support exists in high-level languages / 39 \\ 5.6.1 Compilers for existing languages / 39 \\ 5.6.2 Extensions to existing languages / 39 \\ 5.6.3 Experimental language designs / 40 \\ 5.7 Why it is useful to be able to change the precision mode / 41 \\ 5.8 Why compiler support is required in order to avoid double rounding / 42 \\ 5.9 What support should exist in high-level languages / 43 \\ 6 Double Rounding / 47 \\ 6.1 Why double rounding can be undesirable / 48 \\ 6.2 When is double rounding innocuous? / 50 \\ 6.2.1 Addition / 51 \\ 6.2.2 Subtraction / 52 \\ 6.2.3 Multiplication / 53 \\ 6.2.4 Division / 54 \\ 6.2.5 Square root / 55 \\ 6.2.6 Additional comments / 57 \\ 6.3 On avoiding double rounding / 58 \\ 6.4 Practical ways of avoiding double rounding / 60 \\ 7 Supporting the Standard Operations in High-Level Languages / 63 \\ 7.1 IEEE Standard requirements in regards to operations / 63 \\ 7.2 How different architectures implement these operations / 66 \\ 7.2.1 CISC architectures / 66 \\ 7.2.2 RISC architectures / 68 \\ 7.2.3 How different architectures implement comparison / 69 \\ 7.3 Making the standard operations available in high-level languages / 70 \\ 7.4 Handling static evaluation / 72 \\ 7.5 What support exists in high-level languages / 72 \\ 7.5.1 Existing language designs / 72 \\ 7.5.2 Compilers for existing languages / 74 \\ 7.5.3 Extensions to existing languages / 74 \\ 7.5.4 New language designs / 75 \\ 7.6 What support should exist in high-level languages / 76 \\ 8 Supporting Exceptional Situations in High-Level Languages / 79 \\ 8.1 IEEE Standard requirements in regards to special computational situations / 79 \\ 8.2 Different architectures' support for exceptional situations / 81 \\ 8.2.1 CISC architectures / 81 \\ 8.2.2 RISC architectures / 84 \\ 8.2.3 How different architectures distinguish between signaling and quiet NaNs / 87 \\ 8.2.4 How different architectures detect underflow / 88 \\ 8.3 Handling special computational situations in high-level languages / 89 \\ 8.3.1 Ways of representing special values / 89 \\ 8.3.2 Handling static evaluation and numeric literals / 90 \\ 8.3.3 Supporting arithmetic involving special computational situations / 91 \\ 8.3.4 Ways of allowing access to status flags / 92 \\ 8.3.5 Ways of managing the status flags / 93 \\ 8.3.6 Facilities for exception handling / 95 \\ 8.4 Issues related to mixed-language programming / 96 \\ 8.5 What support exists in high-level languages / 97 \\ 8.5.1 Existing language designs / 97 \\ 8.5.2 Compilers for existing languages / 98 \\ 8.5.3 Extensions to existing languages / 98 \\ 8.5.4 New language designs / 99 \\ 8.6 What support should exist in high-level languages / 100 \\ 9 Floating-Point Expression Evaluation Schemes / 105 \\ 9.1 Predictable expression evaluation schemes / 106 \\ 9.2 Advantages and disadvantages of various evaluation schemes / 106 \\ 9.3 Bit-for-bit identical results and the IEEE Standard / 108 \\ 9.3.1 Optional and implementation defined features of the IEEE Standard / 108 \\ 9.3.2 Are bit-for-bit identical results achievable in Java? / 110 \\ 10 Supporting the IEEE Standard in Ada and Java / 113 \\ 10.1 Ada / 114 \\ 10.1.1 Data formats / 114 \\ 10.1.2 Rounding and rounding precision modes / 114 \\ 10.1.3 Operations / 114 \\ 10.1.4 Exceptional situations / 115 \\ 10.1.5 Expression evaluation / 117 \\ 10.1.6 Pragmas related to floating-point arithmetic / 117 \\ 10.2 Java / 118 \\ 10.2.1 Data formats / 118 \\ 10.2.2 Rounding and (rounding) precision modes / 119 \\ 10.2.3 Operations / 120 \\ 10.2.4 Exceptional situations / 120 \\ 11 Conclusion / 123 \\ 11.1 How well current languages support the IEEE Standard / 123 \\ 11.2 Related unfinished work and open issues / 126 \\ A Supporting the IEEE Standard in Ada / 127 \\ A.1 The Package Standard FP Arithmetic / 127 \\ A.1.1 Data Formats / 130 \\ A.1.2 Operations of Floating-Point Types / 131 \\ A.1.3 Rounding Modes / 132 \\ A.1.4 Status Flags / 132 \\ A.1.5 Trap Handlers / 132 \\ A.2 Floating-Point Operations / 132 \\ A.2.1 The Package Generic FP Operations / 132 \\ A.2.2 Required Functions and Predicates / 136 \\ A.2.3 Recommended Functions and Predicate / 138 \\ A.3 Model of Floating-Point Arithmetic / 138 \\ A.3.1 Floating-Point Evaluation Format / 139 \\ A.3.2 Exception Handling / 139 \\ A.4 Pragmas Related to Floating-Point Arithmetic / 144 \\ A.4.1 Pragmas Related to the Accuracy of Results / 144 \\ A.4.2 Pragmas Related to Rounding Modes / 146 \\ A.4.3 Other Pragmas / 148 \\ Bibliography / 151

entry:
@PhdThesis{FigueroadelCid:2000:RFF,
  author =       "Samuel {Figueroa del Cid}",
  title =        "A Rigorous Framework for Fully Supporting the {IEEE
                 Standard} for Floating-Point Arithmetic in High-Level
                 Programming Languages",
  type =         "{Ph.D.} Thesis",
  school =       "Department of Computer Science, New York University",
  address =      "New York, NY, USA",
  pages =        "345",
  month =        jan,
  year =         "2000",
  ISBN =         "0-599-59894-8",
  ISBN-13 =      "978-0-599-59894-2",
  bibdate =      "Fri Oct 25 17:16:24 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.nyu.edu/csweb/Research/theses.html;
                 http://www.cs.nyu.edu/csweb/Research/Theses/figueroa_sam.html;
                 http://www.cs.nyu.edu/csweb/Research/Theses/figueroa_sam.pdf;
                 http://www.cs.nyu.edu/csweb/Research/Theses/figueroa_sam.ps.gz;
                 http://wwwlib.umi.com/dissertations/fullcit/9956669;
                 http://wwwlib.umi.com/dissertations/preview/9956669",
  abstract =     "Processors conforming to the IEEE Standard for
                 Floating-Point Arithmetic have been commonplace for
                 some years, and now several programming languages seem
                 to support or conform to this standard, from hereon
                 referred to as ``the IEEE Standard.'' For example, The
                 Java Language Specification by Gosling, Joy, and
                 Steele, which defines the Java language, frequently
                 mentions the IEEE Standard. Indeed, Java, as do other
                 languages, supports some of the features of the IEEE
                 Standard, including a couple floating-point data
                 formats, and even requires (in section 4.2.4
                 ``Floating-Point Operations'' of the aforementioned
                 book) that ``operators on floating-point numbers behave
                 exactly as specified by IEEE 754.'' Arguing that the
                 support current languages offer is not enough, this
                 thesis establishes clear criteria for what it means to
                 fully support the IEEE Standard in a programming
                 language. Each aspect of the IEEE Standard is examined
                 in detail from the point of view of how various
                 arithmetic engines implement that aspect of the IEEE
                 Standard, how different languages (and implementations
                 thereof) support it, and what the range of options are
                 in supporting that aspect. Practical recommendations
                 are then offered (particularly, but not exclusively,
                 for Ada and Java), taking, for example, programmer
                 convenience and impact on performance into
                 consideration. A detailed model specification following
                 these recommendations is provided for the Ada language.
                 In addition, a variety of issues related to the
                 floating-point aspects of programming languages are
                 discussed, so as to serve as a more complete guide to
                 language designers. One such issue is floating-point
                 expression evaluation schemes, and, more specifically,
                 whether bit-for-bit identical results are actually
                 achievable on a variety of platforms that conform to
                 the IEEE Standard, as the Java language promises.
                 Closely tied to this issue is that of double rounding,
                 which occurs when a (possibly intermediate) result is
                 rounded more than once before subsequent use or before
                 being delivered to its final destination. So this
                 thesis discusses when double rounding makes a
                 difference, how it can be avoided, and what the
                 performance impact is in avoiding it.",
  acknowledgement = ack-nhfb,
  keywords =     "double rounding",
  tableofcontents = "List of Tables / vii \\
                 1 Introduction / 1 \\
                 1.1 The IEEE Standard for Floating-Point Arithmetic / 1
                 \\
                 1.2 What does it mean to support the IEEE Standard? / 2
                 \\
                 1.3 Considerations in deciding how to support the IEEE
                 Standard in high-level languages / 2 \\
                 1.4 Prior Related Work / 3 \\
                 2 What Does It Mean to Support the IEEE Standard? / 5
                 \\
                 3 Supporting Data Formats in High-Level Languages / 9
                 \\
                 3.1 IEEE Standard requirements in regards to data
                 formats / 9 \\
                 3.2 Hardware facilities supporting data formats / 10
                 \\
                 3.3 Making data formats available in high-level
                 languages / 11 \\
                 3.4 Associating floating-point literals with data
                 formats / 13 \\
                 3.5 Other issues related to numeric literals / 13 \\
                 3.6 Issues related to mixed-language programming / 14
                 \\
                 3.7 What support exists in high-level languages / 15
                 \\
                 3.7.1 Traditional language designs / 15 \\
                 3.7.2 Implementations of traditional languages / 16 \\
                 3.7.3 Extensions to traditional languages / 16 \\
                 3.7.4 New language designs / 17 \\
                 3.8 What support should exist in high-level languages /
                 17 \\
                 4 Supporting Rounding Modes in High-Level Languages /
                 21 \\
                 4.1 IEEE Standard requirements in regards to rounding
                 modes / 21 \\
                 4.2 Hardware facilities for accessing rounding modes /
                 22 \\
                 4.2.1 Processors with dynamic rounding modes / 22 \\
                 4.2.2 Processors with static rounding modes / 24 \\
                 4.3 Making rounding modes available in high-level
                 languages / 25 \\
                 4.4 Handling static evaluation and numeric literals /
                 27 \\
                 4.5 Issues related to mixed-language programming / 29
                 \\
                 4.6 What support exists in high-level languages / 30
                 \\
                 4.6.1 Existing language designs / 30 \\
                 4.6.2 Compilers for existing languages / 30 \\
                 4.6.3 Extensions to existing languages / 30 \\
                 4.6.4 New language designs / 31 \\
                 4.7 Why having more than one rounding mode available is
                 useful / 32 \\
                 4.8 What support should exist in high-level languages /
                 33 \\
                 5 Supporting Precision Modes in High-Level Languages /
                 35 \\
                 5.1 IEEE Standard requirements in regards to precision
                 modes / 35 \\
                 5.2 Hardware facilities for accessing precision modes /
                 36 \\
                 5.2.1 Processors with dynamic precision modes / 36 \\
                 5.2.2 Processors with static precision modes / 36 \\
                 5.2.3 Processors without precision modes / 38 \\
                 5.3 Different ways of making precision modes available
                 in a high-level language / 39 \\
                 5.4 Handling static evaluation and numeric literals /
                 39 \\
                 5.5 Issues related to mixed-language programming / 39
                 \\
                 5.6 What support exists in high-level languages / 39
                 \\
                 5.6.1 Compilers for existing languages / 39 \\
                 5.6.2 Extensions to existing languages / 39 \\
                 5.6.3 Experimental language designs / 40 \\
                 5.7 Why it is useful to be able to change the precision
                 mode / 41 \\
                 5.8 Why compiler support is required in order to avoid
                 double rounding / 42 \\
                 5.9 What support should exist in high-level languages /
                 43 \\
                 6 Double Rounding / 47 \\
                 6.1 Why double rounding can be undesirable / 48 \\
                 6.2 When is double rounding innocuous? / 50 \\
                 6.2.1 Addition / 51 \\
                 6.2.2 Subtraction / 52 \\
                 6.2.3 Multiplication / 53 \\
                 6.2.4 Division / 54 \\
                 6.2.5 Square root / 55 \\
                 6.2.6 Additional comments / 57 \\
                 6.3 On avoiding double rounding / 58 \\
                 6.4 Practical ways of avoiding double rounding / 60 \\
                 7 Supporting the Standard Operations in High-Level
                 Languages / 63 \\
                 7.1 IEEE Standard requirements in regards to operations
                 / 63 \\
                 7.2 How different architectures implement these
                 operations / 66 \\
                 7.2.1 CISC architectures / 66 \\
                 7.2.2 RISC architectures / 68 \\
                 7.2.3 How different architectures implement comparison
                 / 69 \\
                 7.3 Making the standard operations available in
                 high-level languages / 70 \\
                 7.4 Handling static evaluation / 72 \\
                 7.5 What support exists in high-level languages / 72
                 \\
                 7.5.1 Existing language designs / 72 \\
                 7.5.2 Compilers for existing languages / 74 \\
                 7.5.3 Extensions to existing languages / 74 \\
                 7.5.4 New language designs / 75 \\
                 7.6 What support should exist in high-level languages /
                 76 \\
                 8 Supporting Exceptional Situations in High-Level
                 Languages / 79 \\
                 8.1 IEEE Standard requirements in regards to special
                 computational situations / 79 \\
                 8.2 Different architectures' support for exceptional
                 situations / 81 \\
                 8.2.1 CISC architectures / 81 \\
                 8.2.2 RISC architectures / 84 \\
                 8.2.3 How different architectures distinguish between
                 signaling and quiet NaNs / 87 \\
                 8.2.4 How different architectures detect underflow / 88
                 \\
                 8.3 Handling special computational situations in
                 high-level languages / 89 \\
                 8.3.1 Ways of representing special values / 89 \\
                 8.3.2 Handling static evaluation and numeric literals /
                 90 \\
                 8.3.3 Supporting arithmetic involving special
                 computational situations / 91 \\
                 8.3.4 Ways of allowing access to status flags / 92 \\
                 8.3.5 Ways of managing the status flags / 93 \\
                 8.3.6 Facilities for exception handling / 95 \\
                 8.4 Issues related to mixed-language programming / 96
                 \\
                 8.5 What support exists in high-level languages / 97
                 \\
                 8.5.1 Existing language designs / 97 \\
                 8.5.2 Compilers for existing languages / 98 \\
                 8.5.3 Extensions to existing languages / 98 \\
                 8.5.4 New language designs / 99 \\
                 8.6 What support should exist in high-level languages /
                 100 \\
                 9 Floating-Point Expression Evaluation Schemes / 105
                 \\
                 9.1 Predictable expression evaluation schemes / 106 \\
                 9.2 Advantages and disadvantages of various evaluation
                 schemes / 106 \\
                 9.3 Bit-for-bit identical results and the IEEE Standard
                 / 108 \\
                 9.3.1 Optional and implementation defined features of
                 the IEEE Standard / 108 \\
                 9.3.2 Are bit-for-bit identical results achievable in
                 Java? / 110 \\
                 10 Supporting the IEEE Standard in Ada and Java / 113
                 \\
                 10.1 Ada / 114 \\
                 10.1.1 Data formats / 114 \\
                 10.1.2 Rounding and rounding precision modes / 114 \\
                 10.1.3 Operations / 114 \\
                 10.1.4 Exceptional situations / 115 \\
                 10.1.5 Expression evaluation / 117 \\
                 10.1.6 Pragmas related to floating-point arithmetic /
                 117 \\
                 10.2 Java / 118 \\
                 10.2.1 Data formats / 118 \\
                 10.2.2 Rounding and (rounding) precision modes / 119
                 \\
                 10.2.3 Operations / 120 \\
                 10.2.4 Exceptional situations / 120 \\
                 11 Conclusion / 123 \\
                 11.1 How well current languages support the IEEE
                 Standard / 123 \\
                 11.2 Related unfinished work and open issues / 126 \\
                 A Supporting the IEEE Standard in Ada / 127 \\
                 A.1 The Package Standard FP Arithmetic / 127 \\
                 A.1.1 Data Formats / 130 \\
                 A.1.2 Operations of Floating-Point Types / 131 \\
                 A.1.3 Rounding Modes / 132 \\
                 A.1.4 Status Flags / 132 \\
                 A.1.5 Trap Handlers / 132 \\
                 A.2 Floating-Point Operations / 132 \\
                 A.2.1 The Package Generic FP Operations / 132 \\
                 A.2.2 Required Functions and Predicates / 136 \\
                 A.2.3 Recommended Functions and Predicate / 138 \\
                 A.3 Model of Floating-Point Arithmetic / 138 \\
                 A.3.1 Floating-Point Evaluation Format / 139 \\
                 A.3.2 Exception Handling / 139 \\
                 A.4 Pragmas Related to Floating-Point Arithmetic / 144
                 \\
                 A.4.1 Pragmas Related to the Accuracy of Results / 144
                 \\
                 A.4.2 Pragmas Related to Rounding Modes / 146 \\
                 A.4.3 Other Pragmas / 148 \\
                 Bibliography / 151",
}


bibtype: inproceedings
filename: fparith.bib
label: Freking:2000:MMR
author: W. L. Freking and K. K. Parhi
booktitle: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, 2000
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1339--1343
year: 2000
DOI: https://doi.org/10.1109/ACSSC.2000.911210
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: W. L. Freking and K. K. Parhi
rawbooktitle: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, 2000
title:
Modular multiplication in the residue number system with application to massively-parallel public-key cryptography systems

rawtitle:
Modular multiplication in the residue number system with application to massively-parallel public-key cryptography systems

entry:
@InProceedings{Freking:2000:MMR,
  author =       "W. L. Freking and K. K. Parhi",
  booktitle =    "Conference Record of the Thirty-Fourth Asilomar
                 Conference on Signals, Systems and Computers, 2000",
  title =        "Modular multiplication in the residue number system
                 with application to massively-parallel public-key
                 cryptography systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1339--1343",
  year =         "2000",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ACSSC.2000.911210",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Modular multiplication is a fundamental operation in
                 many public-key cryptography systems including RSA.
                 Residue number system (RNS) implementation of modular
                 multiplication has been of recent interest due to
                 inherent RNS properties of \ldots{}",
}


bibtype: phdthesis
filename: fparith.bib
label: Fu:2000:CPO
author: Steve Fu
title: Cost Performance Optimizations of Microprocessors
type: Ph.D. Thesis
school: Department of Electrical Engineering, Stanford University
address: Stanford, CA, USA
year: 2000
bibdate: Mon Dec 24 11:02:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.12.24 11:02:14 ???
acknowledgement: ack-nhfb
rawauthor: Steve Fu
rawtitle: Cost Performance Optimizations of Microprocessors
entry:
@PhdThesis{Fu:2000:CPO,
  author =       "Steve Fu",
  title =        "Cost Performance Optimizations of Microprocessors",
  type =         "{Ph.D.} Thesis",
  school =       "Department of Electrical Engineering, Stanford
                 University",
  address =      "Stanford, CA, USA",
  pages =        "????",
  year =         "2000",
  bibdate =      "Mon Dec 24 11:02:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Gallagher:2000:FTN
author: W. L. Gallagher and E. E. Swartzlander, Jr.
title: Fault-tolerant Newton--Raphson and Goldschmidt dividers using time shared TMR
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 6
pages: 588--595
month: jun
monthnumber: 6
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.862218
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 10:35:24 MDT 2011
bibtimestamp: 2011.07.05 10:35:24 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=862218
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: W. L. Gallagher and E. E. {Swartzlander, Jr.}
rawtitle: Fault-tolerant {Newton--Raphson} and {Goldschmidt} dividers using time shared {TMR}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib

entry:
@Article{Gallagher:2000:FTN,
  author =       "W. L. Gallagher and E. E. {Swartzlander, Jr.}",
  title =        "Fault-tolerant {Newton--Raphson} and {Goldschmidt}
                 dividers using time shared {TMR}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "6",
  pages =        "588--595",
  month =        jun,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.862218",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 10:35:24 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=862218",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: techreport
filename: fparith.bib
label: Gay:2000:SAC
author: David M. Gay
title: Symbolic-Algebraic Computations in a Modeling Language for Mathematical Programming
type: Technical Report
number: 00-3-02
institution: Computing Sciences Research Center, Bell Laboratories
address: Murray Hill, NJ, USA
pages: 588--595
month: jul
monthnumber: 7
year: 2000
bibdate: Wed Jan 29 16:34:27 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.01.29 16:34:27 ???
keywords: correct rounding; decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: David M. Gay
rawtitle: Symbolic-Algebraic Computations in a Modeling Language for Mathematical Programming
remark:
From cite Steele:2004:RHP: ``AMPL and its solver interface library use correctly rounded binary-decimal conversions, which is now possible on all machines where AMPL has run other than old Cray machines.''

entry:
@TechReport{Gay:2000:SAC,
  author =       "David M. Gay",
  title =        "Symbolic-Algebraic Computations in a Modeling Language
                 for Mathematical Programming",
  type =         "Technical Report",
  number =       "00-3-02",
  institution =  "Computing Sciences Research Center, Bell
                 Laboratories",
  address =      "Murray Hill, NJ, USA",
  month =        jul,
  year =         "2000",
  bibdate =      "Wed Jan 29 16:34:27 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; decimal floating-point arithmetic",
  remark =       "From \cite{Steele:2004:RHP}: ``AMPL and its solver
                 interface library use correctly rounded binary-decimal
                 conversions, which is now possible on all machines
                 where AMPL has run other than old Cray machines.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Goldovsky:2000:DIL
author: A. Goldovsky and B. Patel and M. Schulte and R. Kolagotla and H. Srinivas and G. Burns
title: Design and Implementation of a $ 16 $ by $ 16 $ Low Power Two's Complement Multiplier
crossref: IEEE:2000:IGP
pages: 345--348
year: 2000
bibdate: Sun Mar 04 11:22:03 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:22:03 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2000-03.pdf
acknowledgement: ack-nhfb
rawauthor: A. Goldovsky and B. Patel and M. Schulte and R. Kolagotla and H. Srinivas and G. Burns
rawtitle: Design and Implementation of a $ 16 $ by $ 16 $ Low Power Two's Complement Multiplier
entry:
@InProceedings{Goldovsky:2000:DIL,
  author =       "A. Goldovsky and B. Patel and M. Schulte and R.
                 Kolagotla and H. Srinivas and G. Burns",
  title =        "Design and Implementation of a $ 16 $ by $ 16 $ Low
                 Power Two's Complement Multiplier",
  crossref =     "IEEE:2000:IGP",
  pages =        "345--348",
  year =         "2000",
  bibdate =      "Sun Mar 04 11:22:03 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2000-03.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Groza:2000:FPA
author: V. Groza
title: Floating-Point Analog-to-Digital Converters with Predictive Auto-Ranging
crossref: IEEE:2000:IPI
pages: 759--762
year: 2000
bibdate: Sat Jun 02 08:27:44 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 08:27:44 ???
acknowledgement: ack-nhfb
rawauthor: V. Groza
rawtitle: Floating-Point Analog-to-Digital Converters with Predictive Auto-Ranging
entry:
@InProceedings{Groza:2000:FPA,
  author =       "V. Groza",
  title =        "Floating-Point Analog-to-Digital Converters with
                 Predictive Auto-Ranging",
  crossref =     "IEEE:2000:IPI",
  pages =        "759--762",
  year =         "2000",
  bibdate =      "Sat Jun 02 08:27:44 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Hanrot:2000:ML
title: The MPFR Library
pages: 759--762
year: 2000
bibdate: Fri Jun 24 14:53:37 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 14:53:37 ???
URL: http://www.mpfr.org/
acknowledgement: ack-nhfb
howpublished: World-Wide Web software project archive.
rawtitle: The {MPFR} Library
author:
Guillaume Hanrot and Vincent Lefevre and Patrick Pelissier and Paul Zimmermann and Sylvie Boldo and David Daney and Mathieu Dutour and Emmanuel Jeandel and Laurent Fousse and Fabrice Rouillier and Kevin Ryde

abstract:
The MPFR library is a C library for multiple-precision floating-point computations with exact rounding (also called correct rounding). It is based on the GMP multiple-precision library.par The main goal of MPFR is to provide a library for multiple-precision floating-point computation which is both efficient and has a well-defined semantics. It copies the good ideas from the ANSI/IEEE-754 standard for double-precision floating-point arithmetic (53-bit mantissa).

rawabstract:
The MPFR library is a C library for multiple-precision floating-point computations with exact rounding (also called correct rounding). It is based on the GMP multiple-precision library.\par The main goal of MPFR is to provide a library for multiple-precision floating-point computation which is both efficient and has a well-defined semantics. It copies the good ideas from the ANSI/IEEE-754 standard for double-precision floating-point arithmetic (53-bit mantissa).

rawauthor:
Guillaume Hanrot and Vincent Lef{\`e}vre and Patrick P{\'e}lissier and Paul Zimmermann and Sylvie Boldo and David Daney and Mathieu Dutour and Emmanuel Jeandel and Laurent Fousse and Fabrice Rouillier and Kevin Ryde

entry:
@Misc{Hanrot:2000:ML,
  author =       "Guillaume Hanrot and Vincent Lef{\`e}vre and Patrick
                 P{\'e}lissier and Paul Zimmermann and Sylvie Boldo and
                 David Daney and Mathieu Dutour and Emmanuel Jeandel and
                 Laurent Fousse and Fabrice Rouillier and Kevin Ryde",
  title =        "The {MPFR} Library",
  howpublished = "World-Wide Web software project archive.",
  year =         "2000",
  bibdate =      "Fri Jun 24 14:53:37 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.mpfr.org/",
  abstract =     "The MPFR library is a C library for multiple-precision
                 floating-point computations with exact rounding (also
                 called correct rounding). It is based on the GMP
                 multiple-precision library.\par

                 The main goal of MPFR is to provide a library for
                 multiple-precision floating-point computation which is
                 both efficient and has a well-defined semantics. It
                 copies the good ideas from the ANSI/IEEE-754 standard
                 for double-precision floating-point arithmetic (53-bit
                 mantissa).",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Hanrot:2000:SDS
author: Guillaume Hanrot and Michel Quercia and Paul Zimmermann
title: Speeding up the division and square root of power series
type: Research Report
number: 3973
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 23
day: 17
month: jul
monthnumber: 7
year: 2000
ISSN: 0249-6399 OR 02496399
bibdate: Sun Sep 10 08:52:54 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 08:52:54 ???
URL: ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-3973.ps.gz
keywords: division; Karatsuba's algorithm; Newton method; square root
acknowledgement: ack-nhfb
rawauthor: Guillaume Hanrot and Michel Quercia and Paul Zimmermann
rawtitle: Speeding up the division and square root of power series
abstract:
We present new algorithms for the inverse, quotient, or square root of power series. The key trick is a new algorithm RecursiveMiddleProduct or RMP computing the $n$ middle coefficients of a $ 2 n times n $ product in essentially the same number of operations $ K(n) $ than a full $ n times n $ product with Karatsuba's method. This improves previous work of Mulders, Karp and Markstein, Burnikel and Ziegler. These results apply both to series, polynomials, and multiple precision floating-point numbers.

rawabstract:
We present new algorithms for the inverse, quotient, or square root of power series. The key trick is a new algorithm RecursiveMiddleProduct or RMP computing the $n$ middle coefficients of a $ 2 n \times n $ product in essentially the same number of operations $ K(n) $ than a full $ n \times n $ product with Karatsuba's method. This improves previous work of Mulders, Karp and Markstein, Burnikel and Ziegler. These results apply both to series, polynomials, and multiple precision floating-point numbers.

entry:
@TechReport{Hanrot:2000:SDS,
  author =       "Guillaume Hanrot and Michel Quercia and Paul
                 Zimmermann",
  title =        "Speeding up the division and square root of power
                 series",
  type =         "Research Report",
  number =       "3973",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "23",
  day =          "17",
  month =        jul,
  year =         "2000",
  ISSN =         "0249-6399",
  bibdate =      "Sun Sep 10 08:52:54 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-3973.ps.gz",
  abstract =     "We present new algorithms for the inverse, quotient,
                 or square root of power series. The key trick is a new
                 algorithm RecursiveMiddleProduct or RMP computing the
                 $n$ middle coefficients of a $ 2 n \times n $ product
                 in essentially the same number of operations $ K(n) $
                 than a full $ n \times n $ product with Karatsuba's
                 method. This improves previous work of Mulders, Karp
                 and Markstein, Burnikel and Ziegler. These results
                 apply both to series, polynomials, and multiple
                 precision floating-point numbers.",
  acknowledgement = ack-nhfb,
  keywords =     "division; Karatsuba's algorithm; Newton method; square
                 root",
}


bibtype: article
filename: fparith.bib
label: Harrison:2000:FPV
author: John Harrison
title: Floating Point Verification in HOL Light: The Exponential Function
journal: j-FORM-METHODS-SYST-DES
volume: 16
number: 3
pages: 271--305
year: 2000
CODEN: FMSDE6
ISSN: 0925-9856 (print), 1572-8102 (electronic) OR 09259856 (print), 15728102 (electronic)
ISSNL: 0925-9856 OR 09259856
bibdate: Thu May 09 09:43:30 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 09:43:30 ???
fjournal: Formal Methods in System Design
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/fmsd
rawauthor: John Harrison
rawtitle: Floating Point Verification in {HOL Light}: The Exponential Function
abstract:
Since they often embody compact but mathematically sophisticated algorithms, operations for computing the common transcendental functions in floating point arithmetic seem good targets for formal verification using a mechanical theorem prover. We discuss some of the general issues that arise in verifications of this class, and then present a machine-checked verification of an algorithm for computing the exponential function in IEEE-754 standard binary floating point arithmetic. We confirm (indeed strengthen) the main result of a previousl published error analysis, though we uncover a minor error in the hand proof and are forced to confront several subtle issues that might easily be overlooked informally. The development described here includes, apart from the proof itself, a formalization of IEEE arithmetic, a mathematical semantics for the programming language in which the algorithm is expressed, and the body of pure mathematics needed. All this is developed logically from first principles using the HOL Light prover, which guarantees strict adherence to simple rules of inference while allowing the user to perform proofs using higher-level derived rules.

rawabstract:
Since they often embody compact but mathematically sophisticated algorithms, operations for computing the common transcendental functions in floating point arithmetic seem good targets for formal verification using a mechanical theorem prover. We discuss some of the general issues that arise in verifications of this class, and then present a machine-checked verification of an algorithm for computing the exponential function in IEEE-754 standard binary floating point arithmetic. We confirm (indeed strengthen) the main result of a previousl published error analysis, though we uncover a minor error in the hand proof and are forced to confront several subtle issues that might easily be overlooked informally. The development described here includes, apart from the proof itself, a formalization of IEEE arithmetic, a mathematical semantics for the programming language in which the algorithm is expressed, and the body of pure mathematics needed. All this is developed logically from first principles using the HOL Light prover, which guarantees strict adherence to simple rules of inference while allowing the user to perform proofs using higher-level derived rules.

entry:
@Article{Harrison:2000:FPV,
  author =       "John Harrison",
  title =        "Floating Point Verification in {HOL Light}: The
                 Exponential Function",
  journal =      j-FORM-METHODS-SYST-DES,
  volume =       "16",
  number =       "3",
  pages =        "271--305",
  year =         "2000",
  CODEN =        "FMSDE6",
  ISSN =         "0925-9856 (print), 1572-8102 (electronic)",
  ISSN-L =       "0925-9856",
  bibdate =      "Thu May 09 09:43:30 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Since they often embody compact but mathematically
                 sophisticated algorithms, operations for computing the
                 common transcendental functions in floating point
                 arithmetic seem good targets for formal verification
                 using a mechanical theorem prover. We discuss some of
                 the general issues that arise in verifications of this
                 class, and then present a machine-checked verification
                 of an algorithm for computing the exponential function
                 in IEEE-754 standard binary floating point arithmetic.
                 We confirm (indeed strengthen) the main result of a
                 previousl published error analysis, though we uncover a
                 minor error in the hand proof and are forced to
                 confront several subtle issues that might easily be
                 overlooked informally. The development described here
                 includes, apart from the proof itself, a formalization
                 of IEEE arithmetic, a mathematical semantics for the
                 programming language in which the algorithm is
                 expressed, and the body of pure mathematics needed. All
                 this is developed logically from first principles using
                 the HOL Light prover, which guarantees strict adherence
                 to simple rules of inference while allowing the user to
                 perform proofs using higher-level derived rules.",
  acknowledgement = ack-nhfb,
  fjournal =     "Formal Methods in System Design",
  journal-URL =  "https://dl.acm.org/loi/fmsd",
}


bibtype: article
filename: fparith.bib
label: Harrison:2000:FVF
author: John Harrison
title: Formal Verification of Floating Point Trigonometric Functions
journal: j-LECT-NOTES-COMP-SCI
volume: 1954
pages: 217--233
year: 2000
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:08:55 MDT 2002
bibtimestamp: 2002.09.10 19:08:55 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: John Harrison
rawtitle: Formal Verification of Floating Point Trigonometric Functions
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t1954.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/1954/19540217.htm; http://link.springer-ny.com/link/service/series/0558/papers/1954/19540217.pdf

entry:
@Article{Harrison:2000:FVF,
  author =       "John Harrison",
  title =        "Formal Verification of Floating Point Trigonometric
                 Functions",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "1954",
  pages =        "217--233",
  year =         "2000",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:08:55 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t1954.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/1954/19540217.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/1954/19540217.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: inproceedings
filename: fparith.bib
label: Harrison:2000:FVI
author: John Harrison
editor: Mark Aagaard and John Harrison
title: Formal Verification of IA-64 Division Algorithms
publisher: pub-SV
address: pub-SV:adr
pages: 233--251
year: 2000
CODEN: 1869
DOI: https://doi.org/10.1007/3-540-44659-1_15
ISBN: 3-540-44659-1 (e-book), 3-540-67863-8 (paper) OR 3540446591 (ebook), 3540678638 (paper)
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
LCCN: QA76.9.A96 T655 2000
bibdate: Fri Sep 22 16:31:35 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 16:31:35 ???
series: ser-LNCS
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/3-540-44659-1
bookpages: xi + 533
rawauthor: John Harrison
raweditor: Mark Aagaard and John Harrison
rawtitle: Formal Verification of {IA-64} Division Algorithms
booktitle:
Theorem Proving in Higher Order Logics: 13th International Conference, TPHOLs 2000 Portland, OR, USA, August 14-18, 2000 Proceedings

ISBN13:
978-3-540-44659-0 (e-book), 978-3-540-67863-2 (paper) OR 9783540446590 (ebook), 9783540678632 (paper)

rawbooktitle:
Theorem Proving in Higher Order Logics: {13th International Conference, TPHOLs 2000 Portland, OR, USA, August 14-18, 2000 Proceedings}

entry:
@InProceedings{Harrison:2000:FVI,
  author =       "John Harrison",
  editor =       "Mark Aagaard and John Harrison",
  booktitle =    "Theorem Proving in Higher Order Logics: {13th
                 International Conference, TPHOLs 2000 Portland, OR,
                 USA, August 14-18, 2000 Proceedings}",
  title =        "Formal Verification of {IA-64} Division Algorithms",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  bookpages =    "xi + 533",
  pages =        "233--251",
  year =         "2000",
  CODEN =        "1869",
  DOI =          "https://doi.org/10.1007/3-540-44659-1_15",
  ISBN =         "3-540-44659-1 (e-book), 3-540-67863-8 (paper)",
  ISBN-13 =      "978-3-540-44659-0 (e-book), 978-3-540-67863-2
                 (paper)",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  LCCN =         "QA76.9.A96 T655 2000",
  bibdate =      "Fri Sep 22 16:31:35 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       ser-LNCS,
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/3-540-44659-1",
}


bibtype: techreport
filename: fparith.bib
label: Harrison:2000:HOM
author: John Harrison and Ted Kubaska and Bob Norin and Shane Story and Ping Tak Peter Tang
title: Highly Optimized Mathematical Functions for the IA-64 Architectures
type: Technical report
number: 245410-002
institution: Intel Corporation
address: San Jose, CA, USA
pages: 233--251
month: apr
monthnumber: 4
year: 2000
bibdate: Sat Jun 02 11:04:28 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 11:04:28 ???
URL: ftp://download.intel.com/design/IA-64/Downloads/libm.pdf
acknowledgement: ack-nhfb
rawauthor: John Harrison and Ted Kubaska and Bob Norin and Shane Story and Ping Tak Peter Tang
rawtitle: Highly Optimized Mathematical Functions for the {IA-64} Architectures
entry:
@TechReport{Harrison:2000:HOM,
  author =       "John Harrison and Ted Kubaska and Bob Norin and Shane
                 Story and Ping Tak Peter Tang",
  title =        "Highly Optimized Mathematical Functions for the
                 {IA-64} Architectures",
  type =         "Technical report",
  number =       "245410-002",
  institution =  "Intel Corporation",
  address =      "San Jose, CA, USA",
  month =        apr,
  year =         "2000",
  bibdate =      "Sat Jun 02 11:04:28 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://download.intel.com/design/IA-64/Downloads/libm.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hasan:2000:FPI
author: M. A. Hasan and A. A. Hasan and S. Rahman
booktitle: Proceedings of the 39th IEEE Conference on Decision and Control
title: Fixed point iterations for computing square roots and the matrix sign function of complex matrices
volume: 5
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 4253--4258
year: 2000
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: M. A. Hasan and A. A. Hasan and S. Rahman
rawbooktitle: Proceedings of the 39th {IEEE} Conference on Decision and Control
rawtitle: Fixed point iterations for computing square roots and the matrix sign function of complex matrices
entry:
@InProceedings{Hasan:2000:FPI,
  author =       "M. A. Hasan and A. A. Hasan and S. Rahman",
  booktitle =    "Proceedings of the 39th {IEEE} Conference on Decision
                 and Control",
  title =        "Fixed point iterations for computing square roots and
                 the matrix sign function of complex matrices",
  volume =       "5",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "4253--4258",
  year =         "2000",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The purpose of this work has been the development of
                 new set of rational iterations for computing square
                 roots and the matrix sign function of complex matrices.
                 Given any positive integer r{\&}ges;2, we presented a
                 systematic way of deriving rth order \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Hasan:2000:LTB
author: M. A. Hasan
title: Look-Up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 749--758
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863045
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:47:55 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:47:55 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. A. Hasan
rawtitle: Look-Up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems
entry:
@Article{Hasan:2000:LTB,
  author =       "M. A. Hasan",
  title =        "Look-Up Table-Based Large Finite Field Multiplication
                 in Memory Constrained Cryptosystems",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "749--758",
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863045",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:47:55 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Hassibi:2000:ESR
author: B. Hassibi
title: An efficient square-root algorithm for BLAST
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II737--II740
year: 2000
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: B. Hassibi
rawtitle: An efficient square-root algorithm for {BLAST}
booktitle:
Proceedings. 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing: ICASSP '00, 5--9 June 2000

rawbooktitle:
Proceedings. 2000 {IEEE} International Conference on Acoustics, Speech, and Signal Processing: {ICASSP '00}, 5--9 June 2000

entry:
@InProceedings{Hassibi:2000:ESR,
  author =       "B. Hassibi",
  booktitle =    "Proceedings. 2000 {IEEE} International Conference on
                 Acoustics, Speech, and Signal Processing: {ICASSP '00},
                 5--9 June 2000",
  title =        "An efficient square-root algorithm for {BLAST}",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II737--II740",
  year =         "2000",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Bell Labs Layered Space-Time (BLAST) is a scheme for
                 transmitting information over a rich-scattering
                 wireless environment using multiple receive and
                 transmit antennas. The main computational bottleneck in
                 the BLAST algorithm is a ``nulling and \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Hassibi:2000:FSR
author: B. Hassibi
booktitle: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, 2000
title: A fast square-root implementation for BLAST
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1255--1259
year: 2000
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: B. Hassibi
rawbooktitle: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, 2000
rawtitle: A fast square-root implementation for {BLAST}
entry:
@InProceedings{Hassibi:2000:FSR,
  author =       "B. Hassibi",
  booktitle =    "Conference Record of the Thirty-Fourth Asilomar
                 Conference on Signals, Systems and Computers, 2000",
  title =        "A fast square-root implementation for {BLAST}",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1255--1259",
  year =         "2000",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Bell Labs Layered Space-Time (BLAST) is a scheme for
                 transmitting information over a rich-scattering
                 wireless environment using multiple receive and
                 transmit antennas. The main computational bottleneck in
                 the BLAST algorithm is a ``nulling and \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: He:2000:UAA
author: Yun He and Chris H. Q. Ding
crossref: Reynders:2000:IPI
pages: 225--234
year: 2000
DOI: https://doi.org/10.1145/335231.335253
bibdate: Sat Feb 8 18:35:50 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pvm.bib
bibtimestamp: 2020.02.08 18:35:50 ???
URL: https://dl.acm.org/doi/abs/10.1145/335231.335253
acknowledgement: ack-nhfb
rawauthor: Yun He and Chris H. Q. Ding
title:
Using accurate arithmetics to improve numerical reproducibility and stability in parallel applications

abstract:
Numerical reproducibility and stability of large scale scientific simulations, especially climate modeling, on distributed memory parallel computers are becoming critical issues. In particular, global summation of distributed arrays is most susceptible to rounding errors, and their propagation and accumulation cause uncertainty in final simulation results. We analyzed several accurate summation methods and found that two methods are particularly effective to improve (ensure) reproducibility and stability: Kahan's self-compensated summation and Bailey's double-double precision summation. We provide an MPI operator MPLSUMDD to work with MPI collective operations to ensure a scalable implementation on large number of processors. The final methods are particularly simple to adopt in practical codes.

rawabstract:
Numerical reproducibility and stability of large scale scientific simulations, especially climate modeling, on distributed memory parallel computers are becoming critical issues. In particular, global summation of distributed arrays is most susceptible to rounding errors, and their propagation and accumulation cause uncertainty in final simulation results. We analyzed several accurate summation methods and found that two methods are particularly effective to improve (ensure) reproducibility and stability: Kahan's self-compensated summation and Bailey's double-double precision summation. We provide an MPI operator MPLSUMDD to work with MPI collective operations to ensure a scalable implementation on large number of processors. The final methods are particularly simple to adopt in practical codes.

rawtitle:
Using accurate arithmetics to improve numerical reproducibility and stability in parallel applications

entry:
@InProceedings{He:2000:UAA,
  author =       "Yun He and Chris H. Q. Ding",
  title =        "Using accurate arithmetics to improve numerical
                 reproducibility and stability in parallel
                 applications",
  crossref =     "Reynders:2000:IPI",
  pages =        "225--234",
  year =         "2000",
  DOI =          "https://doi.org/10.1145/335231.335253",
  bibdate =      "Sat Feb 8 18:35:50 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pvm.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/335231.335253",
  abstract =     "Numerical reproducibility and stability of large scale
                 scientific simulations, especially climate modeling, on
                 distributed memory parallel computers are becoming
                 critical issues. In particular, global summation of
                 distributed arrays is most susceptible to rounding
                 errors, and their propagation and accumulation cause
                 uncertainty in final simulation results. We analyzed
                 several accurate summation methods and found that two
                 methods are particularly effective to improve (ensure)
                 reproducibility and stability: Kahan's self-compensated
                 summation and Bailey's double-double precision
                 summation. We provide an MPI operator MPLSUMDD to work
                 with MPI collective operations to ensure a scalable
                 implementation on large number of processors. The final
                 methods are particularly simple to adopt in practical
                 codes.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hiasat:2000:NES
author: A. A. Hiasat
title: New efficient structure for a modular multiplier for RNS
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 2
pages: 170--174
month: feb
monthnumber: 2
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.833113
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 10:35:23 MDT 2011
bibtimestamp: 2011.07.05 10:35:23 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=833113
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. A. Hiasat
rawtitle: New efficient structure for a modular multiplier for {RNS}
entry:
@Article{Hiasat:2000:NES,
  author =       "A. A. Hiasat",
  title =        "New efficient structure for a modular multiplier for
                 {RNS}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "2",
  pages =        "170--174",
  month =        feb,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.833113",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 10:35:23 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=833113",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: techreport
filename: fparith.bib
label: Hida:2000:QDA
author: Yozo Hida and Xiaoye S. Li and David H. Bailey
title: Quad-Double Arithmetic: Algorithms, Implementation, and Application
type: Technical report
number: LBNL-46996
institution: Lawrence Berkeley National Laboratory
address: 1 Cycloton Rd, Berkeley, CA 94720
pages: 28
day: 30
month: oct
monthnumber: 10
year: 2000
bibdate: Wed Nov 24 08:18:07 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.24 08:18:07 ???
URL: http://www.cs.berkeley.edu/~yozo/papers/LBNL-46996.ps.gz
acknowledgement: ack-nhfb
rawauthor: Yozo Hida and Xiaoye S. Li and David H. Bailey
rawtitle: Quad-Double Arithmetic: Algorithms, Implementation, and Application
entry:
@TechReport{Hida:2000:QDA,
  author =       "Yozo Hida and Xiaoye S. Li and David H. Bailey",
  title =        "Quad-Double Arithmetic: Algorithms, Implementation,
                 and Application",
  type =         "Technical report",
  number =       "LBNL-46996",
  institution =  "Lawrence Berkeley National Laboratory",
  address =      "1 Cycloton Rd, Berkeley, CA 94720",
  pages =        "28",
  day =          "30",
  month =        oct,
  year =         "2000",
  bibdate =      "Wed Nov 24 08:18:07 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.berkeley.edu/~yozo/papers/LBNL-46996.ps.gz",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Higuchi:2000:FAA
author: Akira Higuchi and Naofumi Takagi
journal: j-INFO-PROC-LETT
volume: 76
number: 3
pages: 101--103
day: 15
month: dec
monthnumber: 12
year: 2000
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Wed Apr 18 07:11:20 MDT 2001
bibtimestamp: 2001.04.18 07:11:20 MDT
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Akira Higuchi and Naofumi Takagi
title:
A fast addition algorithm for elliptic curve arithmetic in $ rm GF(2 n) $ using projective coordinates

URL:
http://www.elsevier.nl/gej-ng/10/23/20/67/27/25/abstract.html; http://www.elsevier.nl/gej-ng/10/23/20/67/27/25/article.pdf

rawtitle:
A fast addition algorithm for elliptic curve arithmetic in {$ {\rm GF}(2 n) $} using projective coordinates

entry:
@Article{Higuchi:2000:FAA,
  author =       "Akira Higuchi and Naofumi Takagi",
  title =        "A fast addition algorithm for elliptic curve
                 arithmetic in {$ {\rm GF}(2 n) $} using projective
                 coordinates",
  journal =      j-INFO-PROC-LETT,
  volume =       "76",
  number =       "3",
  pages =        "101--103",
  day =          "15",
  month =        dec,
  year =         "2000",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Wed Apr 18 07:11:20 MDT 2001",
  bibsource =    "http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.elsevier.nl/gej-ng/10/23/20/67/27/25/abstract.html;
                 http://www.elsevier.nl/gej-ng/10/23/20/67/27/25/article.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: inproceedings
filename: fparith.bib
label: Hormigo:2000:HAVa
author: J. Hormigo and J. Villalba and M. Schulte
booktitle: Proceedings of the 4th Conference on Real Numbers and Computers, Dagstuhl, Germany, April, 2000
title: A Hardware Algorithm for Variable-Precision Division
pages: 104--112
year: 2000
bibdate: Sun Mar 04 11:20:37 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:20:37 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2000-02.pdf
acknowledgement: ack-nhfb
rawauthor: J. Hormigo and J. Villalba and M. Schulte
rawbooktitle: Proceedings of the 4th Conference on Real Numbers and Computers, Dagstuhl, Germany, April, 2000
rawtitle: A Hardware Algorithm for Variable-Precision Division
entry:
@InProceedings{Hormigo:2000:HAVa,
  author =       "J. Hormigo and J. Villalba and M. Schulte",
  editor =       "????",
  booktitle =    "Proceedings of the 4th Conference on Real Numbers and
                 Computers, Dagstuhl, Germany, April, 2000",
  title =        "A Hardware Algorithm for Variable-Precision Division",
  publisher =    "????",
  address =      "????",
  pages =        "104--112",
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Sun Mar 04 11:20:37 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2000-02.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hormigo:2000:HAVb
author: J. Hormigo and J. Villalba and M. Schulte
title: A Hardware Algorithm for Variable-Precision Logarithm
crossref: Swartzlander:2000:IIC
pages: 215--224
year: 2000
bibdate: Sun Mar 04 11:20:37 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:20:37 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2000-04.pdf
acknowledgement: ack-nhfb
rawauthor: J. Hormigo and J. Villalba and M. Schulte
rawtitle: A Hardware Algorithm for Variable-Precision Logarithm
entry:
@InProceedings{Hormigo:2000:HAVb,
  author =       "J. Hormigo and J. Villalba and M. Schulte",
  title =        "A Hardware Algorithm for Variable-Precision
                 Logarithm",
  crossref =     "Swartzlander:2000:IIC",
  pages =        "215--224",
  year =         "2000",
  bibdate =      "Sun Mar 04 11:20:37 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2000-04.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ide:2000:GMF
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 35
number: 7
pages: 1025--1033
month: jul
monthnumber: 7
year: 2000
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
URL: http://www.hwswworld.com/downloads/a7/1025ide.pdf
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
author:
Nobuhiro Ide and Masashi Hirano and Yukio Endo and Shin ichi Yoshioka and Hiroaki Murakami and Atsushi Kunimatsu and Toshinori Sato and Takayuki Kamei and Toyoshi Okada and Masakazu Suzuoki

title:
2.44 GFLOPS 300-MHz Floating-Point Vector-Processing Unit for High-Performance $3$-D Graphics Computing

rawauthor:
Nobuhiro Ide and Masashi Hirano and Yukio Endo and Shin ichi Yoshioka and Hiroaki Murakami and Atsushi Kunimatsu and Toshinori Sato and Takayuki Kamei and Toyoshi Okada and Masakazu Suzuoki

rawtitle:
{2.44 GFLOPS 300-MHz} Floating-Point Vector-Processing Unit for High-Performance {$3$-D} Graphics Computing

entry:
@Article{Ide:2000:GMF,
  author =       "Nobuhiro Ide and Masashi Hirano and Yukio Endo and
                 Shin ichi Yoshioka and Hiroaki Murakami and Atsushi
                 Kunimatsu and Toshinori Sato and Takayuki Kamei and
                 Toyoshi Okada and Masakazu Suzuoki",
  title =        "{2.44 GFLOPS 300-MHz} Floating-Point Vector-Processing
                 Unit for High-Performance {$3$-D} Graphics Computing",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "35",
  number =       "7",
  pages =        "1025--1033",
  month =        jul,
  year =         "2000",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.hwswworld.com/downloads/a7/1025ide.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "A vector unit for high-performance three-dimensional
                 graphics computing has been developed. We implement
                 four floating-point multiply-accumulate units, which
                 execute multiply-add operations with one throughput;
                 one floating-point divide/square root \ldots{}",
}


bibtype: book
filename: fparith.bib
label: Ifrah:2000:UHN
author: Georges Ifrah
title: The Universal History of Numbers from Prehistory to the Invention of the Computer
publisher: pub-WILEY
address: pub-WILEY:adr
pages: xxii + 633
year: 2000
ISBN: 0-471-37568-3 OR 0471375683
ISBN13: 978-0-471-37568-5 OR 9780471375685
LCCN: QA141.I3713 2000
bibdate: Mon Dec 06 16:02:33 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.12.06 16:02:33 ???
acknowledgement: ack-nhfb
rawauthor: Georges Ifrah
rawtitle: The Universal History of Numbers from Prehistory to the Invention of the Computer
note:
Translated from the French edition, em Histoire universelle des chiffres, by David Bellos, E. F. Harding, Sophie Wood, and Ian Monk.

rawnote:
Translated from the French edition, {\em Histoire universelle des chiffres}, by David Bellos, E. F. Harding, Sophie Wood, and Ian Monk.

entry:
@Book{Ifrah:2000:UHN,
  author =       "Georges Ifrah",
  title =        "The Universal History of Numbers from Prehistory to
                 the Invention of the Computer",
  publisher =    pub-WILEY,
  address =      pub-WILEY:adr,
  pages =        "xxii + 633",
  year =         "2000",
  ISBN =         "0-471-37568-3",
  ISBN-13 =      "978-0-471-37568-5",
  LCCN =         "QA141.I3713 2000",
  bibdate =      "Mon Dec 06 16:02:33 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Translated from the French edition, {\em Histoire
                 universelle des chiffres}, by David Bellos, E. F.
                 Harding, Sophie Wood, and Ian Monk.",
  price =        "US\$39.95",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Imajo:2000:CSB
title: COBOL Script: a Business-Oriented Scripting Language
crossref: IEEE:2000:EPI
pages: 231--??
year: 2000
bibdate: Thu Aug 07 17:50:59 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 17:50:59 ???
acknowledgement: ack-nhfb
rawtitle: {COBOL Script}: a Business-Oriented Scripting Language
author:
Tetsuji Imajo and Tatsuki Miyake and Shinobu Sato and Toshiyuki Ito and Daisuke Yokotsuka and Yoshihide Tsujihata and Shunsuke Uemura

abstract:
This paper describes COBOL Script, a Web-oriented script language developed by Hitachi. COBOL Script includes the following features: (1) The language specifications, which consist of functions required for Web computing, are a subset of COBOL85, the most frequently used programming language in business information systems. (2) COBOL Script supports decimal arithmetic functions that have the same precision as in standard COBOL85 on mainframe computers. (3) Efficient implementation was based on analysis of the pros and cons of the COBOL processing system. Using COBOL Script, users can: (1) Process applications requiring high precision, such as account-related applications, over the Web. (2) Use a test debugger and a Coverage Function with COBOL Script for large-scale development projects. (3) Use Japanese in programs. (4) Achieve good run-time performance.

keywords:
account-related applications; business information systems; business-oriented scripting language; COBOL; COBOL processing system; COBOL Script; COBOL85; decimal arithmetic functions; decimal floating-point arithmetic; language specifications; large-scale development projects; test debugger; Web computing; Web-oriented script language

rawabstract:
This paper describes COBOL Script, a Web-oriented script language developed by Hitachi. COBOL Script includes the following features: (1) The language specifications, which consist of functions required for Web computing, are a subset of COBOL85, the most frequently used programming language in business information systems. (2) COBOL Script supports decimal arithmetic functions that have the same precision as in standard COBOL85 on mainframe computers. (3) Efficient implementation was based on analysis of the pros and cons of the COBOL processing system. Using COBOL Script, users can: (1) Process applications requiring high precision, such as account-related applications, over the Web. (2) Use a test debugger and a Coverage Function with COBOL Script for large-scale development projects. (3) Use Japanese in programs. (4) Achieve good run-time performance.

rawauthor:
Tetsuji Imajo and Tatsuki Miyake and Shinobu Sato and Toshiyuki Ito and Daisuke Yokotsuka and Yoshihide Tsujihata and Shunsuke Uemura

entry:
@InProceedings{Imajo:2000:CSB,
  author =       "Tetsuji Imajo and Tatsuki Miyake and Shinobu Sato and
                 Toshiyuki Ito and Daisuke Yokotsuka and Yoshihide
                 Tsujihata and Shunsuke Uemura",
  title =        "{COBOL Script}: a Business-Oriented Scripting
                 Language",
  crossref =     "IEEE:2000:EPI",
  pages =        "231--??",
  year =         "2000",
  bibdate =      "Thu Aug 07 17:50:59 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper describes COBOL Script, a Web-oriented
                 script language developed by Hitachi. COBOL Script
                 includes the following features: (1) The language
                 specifications, which consist of functions required for
                 Web computing, are a subset of COBOL85, the most
                 frequently used programming language in business
                 information systems. (2) COBOL Script supports decimal
                 arithmetic functions that have the same precision as in
                 standard COBOL85 on mainframe computers. (3) Efficient
                 implementation was based on analysis of the pros and
                 cons of the COBOL processing system. Using COBOL
                 Script, users can: (1) Process applications requiring
                 high precision, such as account-related applications,
                 over the Web. (2) Use a test debugger and a Coverage
                 Function with COBOL Script for large-scale development
                 projects. (3) Use Japanese in programs. (4) Achieve
                 good run-time performance.",
  acknowledgement = ack-nhfb,
  keywords =     "account-related applications; business information
                 systems; business-oriented scripting language; COBOL;
                 COBOL processing system; COBOL Script; COBOL85; decimal
                 arithmetic functions; decimal floating-point
                 arithmetic; language specifications; large-scale
                 development projects; test debugger; Web computing;
                 Web-oriented script language",
}


bibtype: misc
filename: fparith.bib
label: Intel:2000:DSR
author: Intel
title: Divide, Square Root, and Remainder Algorithms for the Itanium Architecture
pages: 231--??
month: jul
monthnumber: 7
year: 2000
bibdate: Fri Sep 22 17:06:23 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 17:06:23 ???
URL: https://studylib.net/doc/7921762/divide--square-root-and-remainder-algorithms-for-the-ia-64
acknowledgement: ack-nhfb
howpublished: Intel Software Development Products
rawauthor: {Intel}
rawtitle: Divide, Square Root, and Remainder Algorithms for the {Itanium} Architecture
entry:
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                 {Itanium} Architecture",
  howpublished = "Intel Software Development Products",
  month =        jul,
  year =         "2000",
  bibdate =      "Fri Sep 22 17:06:23 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://studylib.net/doc/7921762/divide--square-root-and-remainder-algorithms-for-the-ia-64",
  acknowledgement = ack-nhfb,
}


bibtype: manual
filename: fparith.bib
label: Intel:2000:IPF
title: Itanium Processor Floating-point Software Assistance and Floating-point Exception Handling
number: 245415-001
organization: pub-INTEL
address: pub-INTEL:adr
pages: 231--??
month: jan
monthnumber: 1
year: 2000
bibdate: Tue Nov 18 16:18:52 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.11.18 16:18:52 ???
URL: http://cache-www.intel.com/cd/00/00/21/92/219290_fpswa_software.pdf
acknowledgement: ack-nhfb
rawtitle: {Itanium} Processor Floating-point Software Assistance and Floating-point Exception Handling
entry:
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  title =        "{Itanium} Processor Floating-point Software Assistance
                 and Floating-point Exception Handling",
  number =       "245415-001",
  organization = pub-INTEL,
  address =      pub-INTEL:adr,
  month =        jan,
  year =         "2000",
  bibdate =      "Tue Nov 18 16:18:52 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://cache-www.intel.com/cd/00/00/21/92/219290_fpswa_software.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: ISO:2000:FSI
author: ISO/IEC JTC1/SC22/WG5
edition: Second
pages: 231--??
day: 19
month: jan
monthnumber: 1
year: 2000
bibdate: Thu May 09 10:24:52 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 10:24:52 ???
URL: ftp://ftp.nag.co.uk/sc22wg5/N1351-N1400/N1378.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web document.
rawauthor: {ISO/IEC JTC1/SC22/WG5}
title:
Information technology --- Programming languages --- Fortran -- Floating-point exception handing (draft)

rawtitle:
Information technology --- Programming languages --- {Fortran} -- Floating-point exception handing (draft)

entry:
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  author =       "{ISO/IEC JTC1/SC22/WG5}",
  title =        "Information technology --- Programming languages ---
                 {Fortran} -- Floating-point exception handing (draft)",
  howpublished = "World-Wide Web document.",
  edition =      "Second",
  day =          "19",
  month =        jan,
  year =         "2000",
  bibdate =      "Thu May 09 10:24:52 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.nag.co.uk/sc22wg5/N1351-N1400/N1378.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Joye:2000:OLR
author: M. Joye and S.-M. Yen
title: Optimal Left-to-Right Binary Signed-Digit Recoding
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 740--748
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863044
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:47:55 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:47:55 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Joye and S.-M. Yen
rawtitle: Optimal Left-to-Right Binary Signed-Digit Recoding
entry:
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  author =       "M. Joye and S.-M. Yen",
  title =        "Optimal Left-to-Right Binary Signed-Digit Recoding",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "740--748",
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863044",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:47:55 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
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  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
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  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
}


bibtype: misc
filename: fparith.bib
label: Kahan:2000:MAA
author: W. Kahan
title: Miscalculating Area and Angles of a Needle-like Triangle
pages: 740--748
day: 24
month: mar
monthnumber: 3
year: 2000
bibdate: Fri Jul 15 12:30:24 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.15 12:30:24 ???
URL: http://www.cs.berkeley.edu/~wkahan/Triangle.pdf
keywords: floating-point arithmetic
acknowledgement: ack-nhfb
howpublished: World-Wide Web lecture notes for introductory numerical analysis classes.
rawauthor: W. Kahan
rawtitle: Miscalculating Area and Angles of a Needle-like Triangle
entry:
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  author =       "W. Kahan",
  title =        "Miscalculating Area and Angles of a Needle-like
                 Triangle",
  howpublished = "World-Wide Web lecture notes for introductory
                 numerical analysis classes.",
  day =          "24",
  month =        mar,
  year =         "2000",
  bibdate =      "Fri Jul 15 12:30:24 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.berkeley.edu/~wkahan/Triangle.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic",
}


bibtype: techreport
filename: fparith.bib
label: Kahan:2000:MVM
author: W. Kahan
title: Marketing versus Mathematics and other Ruminations on the design of floating-point arithmetic
address: Berkeley, CA, USA
pages: 48
day: 27
month: aug
monthnumber: 8
year: 2000
bibdate: Fri May 03 12:19:56 2002
bibtimestamp: 2002.05.03 12:19:56 ???
acknowledgement: ack-nhfb
howpublished: World-Wide Web document.
rawauthor: W. Kahan
rawtitle: Marketing versus Mathematics and other Ruminations on the design of floating-point arithmetic
institution:
Mathematics Department and Electrical Engineering and Computer Science Department, University of California, Berkeley

URL:
http://www.cs.berkeley.edu/~wkahan/MktgMath.pdf; http://www.cs.nyu.edu/cs/faculty/overton/book/docs/KahanTalk.pdf

entry:
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  author =       "W. Kahan",
  title =        "Marketing versus Mathematics and other Ruminations on
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  howpublished = "World-Wide Web document.",
  institution =  "Mathematics Department and Electrical Engineering and
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  address =      "Berkeley, CA, USA",
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  month =        aug,
  year =         "2000",
  bibdate =      "Fri May 03 12:19:56 2002",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.berkeley.edu/~wkahan/MktgMath.pdf;
                 http://www.cs.nyu.edu/cs/faculty/overton/book/docs/KahanTalk.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Kahan:2000:RDFa
author: W. Kahan
title: Ruminations on the Design of Floating-Point Arithmetic
pages: 29
day: 25
month: apr
monthnumber: 4
year: 2000
bibdate: Sat Mar 03 18:19:26 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.03 18:19:26 ???
URL: http://cs.nyu.edu/cs/faculty/overton/book/docs/KahanTalk.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: W. Kahan
rawtitle: Ruminations on the Design of Floating-Point Arithmetic
entry:
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  author =       "W. Kahan",
  title =        "Ruminations on the Design of Floating-Point
                 Arithmetic",
  howpublished = "World-Wide Web document",
  pages =        "29",
  day =          "25",
  month =        apr,
  year =         "2000",
  bibdate =      "Sat Mar 03 18:19:26 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://cs.nyu.edu/cs/faculty/overton/book/docs/KahanTalk.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Kahan:2000:RDFb
author: W. Kahan
title: Marketing versus Mathematics and other Ruminations on the design of floating-point arithmetic
address: Berkeley, CA, USA
pages: 48
day: 27
month: aug
monthnumber: 8
year: 2000
bibdate: Fri May 03 12:19:56 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.03 12:19:56 ???
acknowledgement: ack-nhfb
howpublished: World-Wide Web document.
rawauthor: W. Kahan
rawtitle: Marketing versus Mathematics and other Ruminations on the design of floating-point arithmetic
institution:
Mathematics Department and Electrical Engineering and Computer Science Department, University of California, Berkeley

URL:
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entry:
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  author =       "W. Kahan",
  title =        "Marketing versus Mathematics and other Ruminations on
                 the design of floating-point arithmetic",
  howpublished = "World-Wide Web document.",
  institution =  "Mathematics Department and Electrical Engineering and
                 Computer Science Department, University of California,
                 Berkeley",
  address =      "Berkeley, CA, USA",
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bibtype: article
filename: fparith.bib
label: Kalampoukas:2000:HSP
author: L. Kalampoukas and D. Nikolos and C. Efstathiou and H. T. Vergos and J. Kalamatianos
title: High-Speed Parallel-Prefix Modulo $ 2^n - 1 $ Adders
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 673--680
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.863036
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:47:55 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:47:55 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
remark: Selected papers from ARITH'14 cite Koren:1999:ISC.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: L. Kalampoukas and D. Nikolos and C. Efstathiou and H. T. Vergos and J. Kalamatianos
rawtitle: High-Speed Parallel-Prefix Modulo $ 2^{n - 1} $ Adders
entry:
@Article{Kalampoukas:2000:HSP,
  author =       "L. Kalampoukas and D. Nikolos and C. Efstathiou and H.
                 T. Vergos and J. Kalamatianos",
  title =        "High-Speed Parallel-Prefix Modulo $ 2^{n - 1} $
                 Adders",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "673--680",
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.863036",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:47:55 MDT 2002",
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  acknowledgement = ack-nhfb,
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  keywords =     "ARITH-14",
  remark =       "Selected papers from ARITH'14 \cite{Koren:1999:ISC}.",
}


bibtype: article
filename: fparith.bib
label: Kao:2000:LTA
author: Ming-Yang Kao and Jie Wang
title: Linear-Time Approximation Algorithms for Computing Numerical Summation with Provably Small Errors
journal: j-SIAM-J-COMPUT
volume: 29
number: 5
pages: 1568--1576
month: oct
monthnumber: 10
year: 2000
CODEN: SMJCAT
DOI: https://doi.org/10.1137/S0097539798341594
ISSN: 0097-5397 (print), 1095-7111 (electronic) OR 00975397 (print), 10957111 (electronic)
ISSNL: 0097-5397 OR 00975397
bibdate: Fri Oct 27 06:28:34 MDT 2000
bibtimestamp: 2000.10.27 06:28:34 MDT
URL: http://epubs.siam.org/sam-bin/dbq/article/34159
fjournal: SIAM Journal on Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sicomp
rawauthor: Ming-Yang Kao and Jie Wang
rawtitle: Linear-Time Approximation Algorithms for Computing Numerical Summation with Provably Small Errors
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entry:
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  bibdate =      "Fri Oct 27 06:28:34 MDT 2000",
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bibtype: article
filename: fparith.bib
label: Kapur:2000:UIP
author: Deepak Kapur and Mahadevan Subramaniam
title: Using an induction prover for verifying arithmetic circuits
journal: j-INT-J-SOFTW-TOOLS-TECHNOL-TRANSFER
volume: 3
number: 1
pages: 32--65
month: sep
monthnumber: 9
year: 2000
ISSN: 1433-2779 (print), 1433-2787 (electronic) OR 14332779 (print), 14332787 (electronic)
ISSNL: 1433-2779 OR 14332779
bibdate: Tue Nov 23 15:01:40 MST 2004
bibtimestamp: 2004.11.23 15:01:40 MST
fjournal: International Journal on Software Tools for Technology Transfer: STTT
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10009
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rawtitle: Using an induction prover for verifying arithmetic circuits
bibsource:
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entry:
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  title =        "Using an induction prover for verifying arithmetic
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  number =       "1",
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  month =        sep,
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  CODEN =        "????",
  ISSN =         "1433-2779 (print), 1433-2787 (electronic)",
  ISSN-L =       "1433-2779",
  bibdate =      "Tue Nov 23 15:01:40 MST 2004",
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  acknowledgement = ack-nhfb,
  fjournal =     "International Journal on Software Tools for Technology
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  journal-URL =  "http://link.springer.com/journal/10009",
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bibtype: article
filename: fparith.bib
label: Kawamura:2000:CRA
author: Shinichi Kawamura and Masanobu Koike and Fumihiko Sano and Atsushi Shimbo
title: Cox-Rower Architecture for Fast Parallel Montgomery Multiplication
journal: j-LECT-NOTES-COMP-SCI
volume: 1807
pages: 523--??
year: 2000
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Fri Feb 1 09:16:29 MST 2002
bibtimestamp: 2002.02.01 09:16:29 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Shinichi Kawamura and Masanobu Koike and Fumihiko Sano and Atsushi Shimbo
rawtitle: {Cox-Rower} Architecture for Fast Parallel {Montgomery} Multiplication
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t1807.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/1807/18070523.htm; http://link.springer-ny.com/link/service/series/0558/papers/1807/18070523.pdf

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  title =        "{Cox-Rower} Architecture for Fast Parallel
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                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/1807/18070523.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/1807/18070523.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Keller:2000:ARR
author: T. Keller and T. H. Liew and Lajos Hanzo
title: Adaptive redundant residue number system coded multicarrier modulation
journal: j-IEEE-J-SEL-AREAS-COMMUN
volume: 18
number: 11
pages: 2292--2301
month: nov
monthnumber: 11
year: 2000
CODEN: ISACEM
DOI: https://doi.org/10.1109/49.895034
ISSN: 0733-8716 (print), 1558-0008 (electronic) OR 07338716 (print), 15580008 (electronic)
ISSNL: 0733-8716 OR 07338716
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=19376
fjournal: IEEE Journal on Selected Areas in Communications
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: T. Keller and T. H. Liew and Lajos Hanzo
rawtitle: Adaptive redundant residue number system coded multicarrier modulation
entry:
@Article{Keller:2000:ARR,
  author =       "T. Keller and T. H. Liew and Lajos Hanzo",
  title =        "Adaptive redundant residue number system coded
                 multicarrier modulation",
  journal =      j-IEEE-J-SEL-AREAS-COMMUN,
  volume =       "18",
  number =       "11",
  pages =        "2292--2301",
  month =        nov,
  year =         "2000",
  CODEN =        "ISACEM",
  DOI =          "https://doi.org/10.1109/49.895034",
  ISSN =         "0733-8716 (print), 1558-0008 (electronic)",
  ISSN-L =       "0733-8716",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=19376",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal on Selected Areas in Communications",
  keywords =     "residue arithmetic; residue number system",
  summary =      "The novel class of nonbinary maximum minimum distance
                 redundant residue number system (RRNS) codes is invoked
                 in the context of adaptively RRNS coded,
                 symbol-by-symbol adaptive multicarrier modulation, in
                 order to combat the effects of frequency- \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kim:2000:PSA
author: Hyun-Sung Kim and Sung-Woo Lee and Kee-Young Yoo
title: Partitioned systolic architecture for modular multiplication in GF (2 m )
journal: j-INFO-PROC-LETT
volume: 76
number: 3
pages: 135--139
day: 15
month: dec
monthnumber: 12
year: 2000
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Wed Apr 18 07:11:20 MDT 2001
bibtimestamp: 2001.04.18 07:11:20 MDT
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Hyun-Sung Kim and Sung-Woo Lee and Kee-Young Yoo
rawtitle: Partitioned systolic architecture for modular multiplication in {GF} (2 { m })
URL:
http://www.elsevier.nl/gej-ng/10/23/20/67/27/30/abstract.html; http://www.elsevier.nl/gej-ng/10/23/20/67/27/30/article.pdf

entry:
@Article{Kim:2000:PSA,
  author =       "Hyun-Sung Kim and Sung-Woo Lee and Kee-Young Yoo",
  title =        "Partitioned systolic architecture for modular
                 multiplication in {GF} (2 { m })",
  journal =      j-INFO-PROC-LETT,
  volume =       "76",
  number =       "3",
  pages =        "135--139",
  day =          "15",
  month =        dec,
  year =         "2000",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Wed Apr 18 07:11:20 MDT 2001",
  bibsource =    "http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.elsevier.nl/gej-ng/10/23/20/67/27/30/abstract.html;
                 http://www.elsevier.nl/gej-ng/10/23/20/67/27/30/article.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: article
filename: fparith.bib
label: Kobayashi:2000:HBF
author: Shiro Kobayashi and Gerhard P. Fettweis
title: A Hierarchical Block-Floating-Point Arithmetic
journal: j-J-VLSI-SIGNAL-PROC
volume: 24
number: 1
pages: 19--30
month: feb
monthnumber: 2
year: 2000
CODEN: JVSPED
DOI: https://doi.org/10.1023/A:1008110410087
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Fri Nov 8 05:39:32 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.11.08 05:39:32 MST
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: Shiro Kobayashi and Gerhard P. Fettweis
rawtitle: A Hierarchical Block-Floating-Point Arithmetic
abstract:
In order to give an answer to a question of the arithmetic in future DSP architectures for mobile communication applications, the signal processing quality of different arithmetic representations has been studied. Based on the result, a new approach for implementing block-floating-point arithmetic is proposed. This approach intends to preserve the least-significant-bits (LSBs) to improve signal processing quality. The preservation of LSBs is automatically and perfectly done by hardware. Several simulation results show that the proposed block-floating-point implementation provides improved SNRs over conventional block-floating-point implementations. For the same number of bits in the memory for each representation, the SNRs better than floating-point are also observed. For multiple datapath DSPs, this implementation also requires significantly less hardware complexity than floating-point.

rawabstract:
In order to give an answer to a question of the arithmetic in future DSP architectures for mobile communication applications, the signal processing quality of different arithmetic representations has been studied. Based on the result, a new approach for implementing block-floating-point arithmetic is proposed. This approach intends to preserve the least-significant-bits (LSBs) to improve signal processing quality. The preservation of LSBs is automatically and perfectly done by hardware. Several simulation results show that the proposed block-floating-point implementation provides improved SNRs over conventional block-floating-point implementations. For the same number of bits in the memory for each representation, the SNRs better than floating-point are also observed. For multiple datapath DSPs, this implementation also requires significantly less hardware complexity than floating-point.

entry:
@Article{Kobayashi:2000:HBF,
  author =       "Shiro Kobayashi and Gerhard P. Fettweis",
  title =        "A Hierarchical Block-Floating-Point Arithmetic",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "24",
  number =       "1",
  pages =        "19--30",
  month =        feb,
  year =         "2000",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1023/A:1008110410087",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Fri Nov 8 05:39:32 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  abstract =     "In order to give an answer to a question of the
                 arithmetic in future DSP architectures for mobile
                 communication applications, the signal processing
                 quality of different arithmetic representations has
                 been studied. Based on the result, a new approach for
                 implementing block-floating-point arithmetic is
                 proposed. This approach intends to preserve the
                 least-significant-bits (LSBs) to improve signal
                 processing quality. The preservation of LSBs is
                 automatically and perfectly done by hardware. Several
                 simulation results show that the proposed
                 block-floating-point implementation provides improved
                 SNRs over conventional block-floating-point
                 implementations. For the same number of bits in the
                 memory for each representation, the SNRs better than
                 floating-point are also observed. For multiple datapath
                 DSPs, this implementation also requires significantly
                 less hardware complexity than floating-point.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
  pagecount =    "12",
}


bibtype: article
filename: fparith.bib
label: Koren:2000:GEI
author: Israel Koren and Peter Kornerup
title: Guest Editors' Introduction: Special Issue on Computer Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 49
number: 7
pages: 625--627
month: jul
monthnumber: 7
year: 2000
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2000.863030
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 10:35:24 MDT 2011
bibtimestamp: 2011.07.05 10:35:24 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863030
fjournal: IEEE Transactions on Computers
keywords: ARITH-14
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Israel Koren and Peter Kornerup
rawtitle: {Guest Editors}' Introduction: Special Issue on Computer Arithmetic
remark:
From the article: ``The papers included in this special issue were selected from 56 manuscripts submitted in response to the call for papers. Submissions were also solicited from the authors of papers presented at the 14th Symposium on Computer Arithmetic (ARITH-14), held in Adelaide, Australia, on April 14--16 1999. This symposium was the most recent in a series of biannual events whose proceedings have provided a wealth of much cited and often seminal papers. As a result of the review process, 14 papers were selected to be included in this special issue. Four of these papers are extensions of papers presented at ARITH-14, some are further descendents of such papers and the rest have originated from the open call for papers.''

entry:
@Article{Koren:2000:GEI,
  author =       "Israel Koren and Peter Kornerup",
  title =        "{Guest Editors}' Introduction: Special Issue on
                 Computer Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "49",
  number =       "7",
  pages =        "625--627",
  month =        jul,
  year =         "2000",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2000.863030",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 10:35:24 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=863030",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-14",
  remark =       "From the article: ``The papers included in this
                 special issue were selected from 56 manuscripts
                 submitted in response to the call for papers.
                 Submissions were also solicited from the authors of
                 papers presented at the 14th Symposium on Computer
                 Arithmetic (ARITH-14), held in Adelaide, Australia, on
                 April 14--16 1999. This symposium was the most recent
                 in a series of biannual events whose proceedings have
                 provided a wealth of much cited and often seminal
                 papers. As a result of the review process, 14 papers
                 were selected to be included in this special issue.
                 Four of these papers are extensions of papers presented
                 at ARITH-14, some are further descendents of such
                 papers and the rest have originated from the open call
                 for papers.''",
}


