# bibtab

bibtype: manual
filename: fparith.bib
label: Motorola:1989:DIF
title: DSP96002: IEEE floating-point dual-port processor: user's manual
organization: Motorola, Inc.
address: Phoeniz, AZ, USA
pages: various
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Floating-point arithmetic.; Signal processing.
remark: Cover title. Spine title: DSP96002 user's manual. ``DSP96002UM/AD''--Cover.
acknowledgement: ack-nhfb
rawtitle: {DSP96002}: {IEEE} floating-point dual-port processor: user's manual
entry:
@Manual{Motorola:1989:DIF,
  title =        "{DSP96002}: {IEEE} floating-point dual-port processor:
                 user's manual",
  organization = "{Motorola, Inc.}",
  address =      "Phoeniz, AZ, USA",
  pages =        "various",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.; Signal processing.",
  remark =       "Cover title. Spine title: DSP96002 user's manual.
                 ``DSP96002UM/AD''--Cover.",
}


bibtype: book
filename: fparith.bib
label: Motorola:1989:FPC
author: Motorola, Inc.
title: MC68881 / MC68882 Floating-Point Coprocessor User's Manual
publisher: pub-PH
address: pub-PH:adr
edition: Second
pages: various
year: 1989
ISBN: 0-13-567009-8 OR 0135670098
ISBN13: 978-0-13-567009-5 OR 9780135670095
bibdate: Fri Dec 08 13:02:55 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 13:02:55 ???
acknowledgement: ack-nj
rawauthor: {Motorola, Inc.}
rawtitle: {MC68881}\slash {MC68882} Floating-Point Coprocessor User's Manual
entry:
@Book{Motorola:1989:FPC,
  author =       "{Motorola, Inc.}",
  title =        "{MC68881}\slash {MC68882} Floating-Point Coprocessor
                 User's Manual",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Second",
  pages =        "various",
  year =         "1989",
  ISBN =         "0-13-567009-8",
  ISBN-13 =      "978-0-13-567009-5",
  LCCN =         "????",
  bibdate =      "Fri Dec 08 13:02:55 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: book
filename: fparith.bib
label: Motorola:1989:MFP
author: Motorola, Inc.Staff
title: MC 68881 and 68882 Floating-Point Coprocessor User's Manual
publisher: pub-PH
address: pub-PH:adr
edition: 0002
pages: various
month: aug
monthnumber: 8
year: 1989
ISBN: 0-13-567009-8 OR 0135670098
ISBN13: 978-0-13-567009-5 OR 9780135670095
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: MICROPROCESSORS; TECHNOLOGY --- COMPUTERS AND COMPUTER TECHNOLOGY
language: eng
acknowledgement: ack-nhfb
rawauthor: {Motorola, Inc.Staff}
rawtitle: {MC} 68881 and 68882 Floating-Point Coprocessor User's Manual
entry:
@Book{Motorola:1989:MFP,
  author =       "{Motorola, Inc.Staff}",
  title =        "{MC} 68881 and 68882 Floating-Point Coprocessor User's
                 Manual",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "0002",
  month =        aug,
  year =         "1989",
  ISBN =         "0-13-567009-8",
  ISBN-13 =      "978-0-13-567009-5",
  LCCN =         "????",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$27.00",
  acknowledgement = ack-nhfb,
  keywords =     "MICROPROCESSORS; TECHNOLOGY --- COMPUTERS AND COMPUTER
                 TECHNOLOGY",
  language =     "eng",
}


bibtype: book
filename: fparith.bib
label: Motorola:1989:MMF
author: Motorola, Inc.
title: MC68881 / MC68882 floating-point coprocessor user's manual
publisher: pub-PH
address: pub-PH:adr
edition: Second
pages: various
year: 1989
ISBN: 0-13-567009-8 (pbk.) OR 0135670098 (pbk.)
ISBN13: 978-0-13-567009-5 (pbk.) OR 9780135670095 (pbk.)
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
remark: Spine title: MC68881/882 user's manual. ``MC68881UM/AD REV 2''--Cover.
acknowledgement: ack-nhfb
rawauthor: {Motorola, Inc.}
rawtitle: {MC68881\slash MC68882} floating-point coprocessor user's manual
keywords:
Floating-point arithmetic.; Microprocessors --- Handbooks, manuals, etc.; Motorola 68881 (Microprocessor); Motorola 68882 (Microprocessor)

entry:
@Book{Motorola:1989:MMF,
  author =       "{Motorola, Inc.}",
  title =        "{MC68881\slash MC68882} floating-point coprocessor
                 user's manual",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Second",
  pages =        "various",
  year =         "1989",
  ISBN =         "0-13-567009-8 (pbk.)",
  ISBN-13 =      "978-0-13-567009-5 (pbk.)",
  LCCN =         "????",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.; Microprocessors ---
                 Handbooks, manuals, etc.; Motorola 68881
                 (Microprocessor); Motorola 68882 (Microprocessor)",
  remark =       "Spine title: MC68881/882 user's manual. ``MC68881UM/AD
                 REV 2''--Cover.",
}


bibtype: book
filename: fparith.bib
label: Motorola:1989:MRM
author: Motorola
title: MC88100 RISC Microprocessor User's Manual
publisher: pub-MOTOROLA
address: pub-MOTOROLA:adr
edition: Second
pages: various
year: 1989
ISBN: 0-13-567090-X OR 013567090X
ISBN13: 978-0-13-567090-3 OR 9780135670903
LCCN: QA76.8.M75 M3 1990
bibdate: Wed Jul 6 14:23:15 1994
bibtimestamp: 1994.07.06 14:23:15 ???
acknowledgement: ack-nhfb
rawauthor: Motorola
rawtitle: {MC88100} {RISC} Microprocessor User's Manual
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib; https://www.math.utah.edu/pub/tex/bib/microchip.bib

TOC:
Overview Features Introduction Execution Units and Register File Execution Model Programming Model Processor States Reset State Flow-Control Instructions Register with 9-Bit Vector Table Index Instruction Categories Programming Tips Instruction Set Opcode Summary Signal Description Data Processor Bus Signals Exceptions Exception Overview Exception Vectors and Vector Base Register (VBR) Exception Priority Exception Processing Instruction Unit Exceptions Integer Overflow Exception (Vector Offset $48) Memory Access Exceptions FPU Exception Processing FPU Exception Processing Registers Timing Factors Execution Example Instruction Set Timing Summary Applications Information Cache Memory Management Units Power and Ground Considerations Master/Checker Operations Synchronization Operations Electrical Characteristics

rawTOC:
Overview \\ Features \\ Introduction \\ Execution Units and Register File \\ Execution Model \\ Programming Model \\ Processor States \\ Reset State \\ Flow-Control Instructions \\ Register with 9-Bit Vector Table Index \\ Instruction Categories \\ Programming Tips \\ Instruction Set \\ Opcode Summary \\ Signal Description \\ Data Processor Bus Signals \\ Exceptions \\ Exception Overview \\ Exception Vectors and Vector Base Register (VBR) \\ Exception Priority \\ Exception Processing \\ Instruction Unit Exceptions \\ Integer Overflow Exception (Vector Offset \$48) \\ Memory Access Exceptions \\ FPU Exception Processing \\ FPU Exception Processing Registers \\ Timing Factors \\ Execution Example \\ Instruction Set Timing Summary \\ Applications Information \\ Cache Memory Management Units \\ Power and Ground Considerations \\ Master/Checker Operations \\ Synchronization Operations \\ Electrical Characteristics

entry:
@Book{Motorola:1989:MRM,
  author =       "Motorola",
  title =        "{MC88100} {RISC} Microprocessor User's Manual",
  publisher =    pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  edition =      "Second",
  year =         "1989",
  ISBN =         "0-13-567090-X",
  ISBN-13 =      "978-0-13-567090-3",
  LCCN =         "QA76.8.M75 M3 1990",
  bibdate =      "Wed Jul 6 14:23:15 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  tableofcontents = "Overview \\
                 Features \\
                 Introduction \\
                 Execution Units and Register File \\
                 Execution Model \\
                 Programming Model \\
                 Processor States \\
                 Reset State \\
                 Flow-Control Instructions \\
                 Register with 9-Bit Vector Table Index \\
                 Instruction Categories \\
                 Programming Tips \\
                 Instruction Set \\
                 Opcode Summary \\
                 Signal Description \\
                 Data Processor Bus Signals \\
                 Exceptions \\
                 Exception Overview \\
                 Exception Vectors and Vector Base Register (VBR) \\
                 Exception Priority \\
                 Exception Processing \\
                 Instruction Unit Exceptions \\
                 Integer Overflow Exception (Vector Offset \$48) \\
                 Memory Access Exceptions \\
                 FPU Exception Processing \\
                 FPU Exception Processing Registers \\
                 Timing Factors \\
                 Execution Example \\
                 Instruction Set Timing Summary \\
                 Applications Information \\
                 Cache Memory Management Units \\
                 Power and Ground Considerations \\
                 Master/Checker Operations \\
                 Synchronization Operations \\
                 Electrical Characteristics",
}


bibtype: article
filename: fparith.bib
label: Mulcahy:1989:FPR
author: L. P. Mulcahy
title: On fixed-point roundoff error analysis
journal: j-IEEE-TRANS-ACOUST-SPEECH
volume: 37
number: 10
pages: 1623
month: oct
monthnumber: 10
year: 1989
CODEN: IETABA
ISSN: 0096-3518 OR 00963518
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Acoustics, Speech, and Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29
rawauthor: L. P. Mulcahy
rawtitle: On fixed-point roundoff error analysis
entry:
@Article{Mulcahy:1989:FPR,
  author =       "L. P. Mulcahy",
  title =        "On fixed-point roundoff error analysis",
  journal =      j-IEEE-TRANS-ACOUST-SPEECH,
  volume =       "37",
  number =       "10",
  pages =        "1623",
  month =        oct,
  year =         "1989",
  CODEN =        "IETABA",
  ISSN =         "0096-3518",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Acoustics, Speech, and Signal
                 Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29",
  summary =      "The author points out the existence of work published
                 by the author (US Department of Commerce, Tech. Rep.
                 AD-A086826, 57 pp., Apr. 1980) prior to the appearance
                 of the paper by Barnes et al. (ibid., vol.ASSP-33,
                 p.595-606, June 1985) covering the same \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Nakayama:1989:BMF
author: T. Nakayama and S. Kojima and H. Harigai and H. Igarashi and K. Tamada and T. Toba
title: An 80 b, 6.7 MFLOPS floating-point processor with vector / matrix instructions
crossref: Wuorinen:1989:DTP
pages: 52--53, 289
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: NEC, Kawasaki, Japan
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; VLSI
rawauthor: T. Nakayama and S. Kojima and H. Harigai and H. Igarashi and K. Tamada and T. Toba
rawtitle: An 80 b, 6.7 {MFLOPS} floating-point processor with vector\slash matrix instructions
abstract:
A description is given of an 80-b CMOS VLSI floating-point processor (FPP) in 1.2- mu m double-metal layer CMOS which contains 433000 transistors on an 11.6-mm*14.9-mm die. It operates at 20 MHz, dissipates 1.5 W, and is assembled in a 68-lead pin-grid-array package. The FPP is designed as a coprocessor for 32-b microprocessors. It implements data formats, arithmetic rounding modes, and exception types which are defined by the IEEE 754 standard. The chip can handle single (32 b), double (64 b), and double-extended (80 b) floating-point data formats. The complex-instruction-set-computer- (CISC-) like 78-instruction set includes 22 mathematical functions such as sin, cos, arctan, exp, and log, and 24 vector/matrix operations such as add, multiply, and inner product. The features and performance of the device are summarized.

keywords:
1.2 Micron; 1.5 W; 20 MHz; 6.7 MFLOPS; 80 Bit; Arithmetic rounding modes; CMOS VLSI floating-point processor; Complex instruction set computer; Data formats; Double-metal layer CMOS; Exception types; Mathematical functions; Pin-grid-array package; Power dissipation; Vector/matrix instructions

rawabstract:
A description is given of an 80-b CMOS VLSI floating-point processor (FPP) in 1.2- mu m double-metal layer CMOS which contains 433000 transistors on an 11.6-mm*14.9-mm die. It operates at 20 MHz, dissipates 1.5 W, and is assembled in a 68-lead pin-grid-array package. The FPP is designed as a coprocessor for 32-b microprocessors. It implements data formats, arithmetic rounding modes, and exception types which are defined by the IEEE 754 standard. The chip can handle single (32 b), double (64 b), and double-extended (80 b) floating-point data formats. The complex-instruction-set-computer- (CISC-) like 78-instruction set includes 22 mathematical functions such as sin, cos, arctan, exp, and log, and 24 vector/matrix operations such as add, multiply, and inner product. The features and performance of the device are summarized.

entry:
@InProceedings{Nakayama:1989:BMF,
  author =       "T. Nakayama and S. Kojima and H. Harigai and H.
                 Igarashi and K. Tamada and T. Toba",
  title =        "An 80 b, 6.7 {MFLOPS} floating-point processor with
                 vector\slash matrix instructions",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "52--53, 289",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A description is given of an 80-b CMOS VLSI
                 floating-point processor (FPP) in 1.2- mu m
                 double-metal layer CMOS which contains 433000
                 transistors on an 11.6-mm*14.9-mm die. It operates at
                 20 MHz, dissipates 1.5 W, and is assembled in a 68-lead
                 pin-grid-array package. The FPP is designed as a
                 coprocessor for 32-b microprocessors. It implements
                 data formats, arithmetic rounding modes, and exception
                 types which are defined by the IEEE 754 standard. The
                 chip can handle single (32 b), double (64 b), and
                 double-extended (80 b) floating-point data formats. The
                 complex-instruction-set-computer- (CISC-) like
                 78-instruction set includes 22 mathematical functions
                 such as sin, cos, arctan, exp, and log, and 24
                 vector/matrix operations such as add, multiply, and
                 inner product. The features and performance of the
                 device are summarized.",
  acknowledgement = ack-nhfb,
  affiliation =  "NEC, Kawasaki, Japan",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  keywords =     "1.2 Micron; 1.5 W; 20 MHz; 6.7 MFLOPS; 80 Bit;
                 Arithmetic rounding modes; CMOS VLSI floating-point
                 processor; Complex instruction set computer; Data
                 formats; Double-metal layer CMOS; Exception types;
                 Mathematical functions; Pin-grid-array package; Power
                 dissipation; Vector/matrix instructions",
  numericalindex = "Word length 8.0E+01 bit; Computer speed 6.7E+06
                 FLOPS; Size 1.2E-06 m; Frequency 2.0E+07 Hz; Power
                 1.5E+00 W",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; VLSI",
}


bibtype: article
filename: fparith.bib
label: Nakayama:1989:FCV
title: A 6.7-MFLOPS floating-point coprocessor with vector / matrix instructions
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1324--1330
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawtitle: A 6.7-{MFLOPS} floating-point coprocessor with vector\slash matrix instructions
author:
T. Nakayama and H. Harigai and S. Kojima and H. Kaneko and H. Igarashi and T. Toba and Y. Yamagami and Y. Yano

abstract:
An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.

keywords:
1.2 Micron; 20 MHz; 6.7 MFLOPS; 80 Bit; CMOS process; CORDIC trigonometrical algorithm; Double-metal layer; Floating-point coprocessor; Horizontal-type microinstructions; Mathematical functions; Parallel operations; Pipelined multiplication; SRT division method; Vector/matrix instructions; VLSI microprocessor

thesaurus:
CMOS integrated circuits; Digital arithmetic; Instruction sets; Microprocessor chips; Parallel architectures; Pipeline processing; Satellite computers; VLSI

rawabstract:
An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.

rawauthor:
T. Nakayama and H. Harigai and S. Kojima and H. Kaneko and H. Igarashi and T. Toba and Y. Yamagami and Y. Yano

entry:
@Article{Nakayama:1989:FCV,
  author =       "T. Nakayama and H. Harigai and S. Kojima and H. Kaneko
                 and H. Igarashi and T. Toba and Y. Yamagami and Y.
                 Yano",
  title =        "A 6.7-{MFLOPS} floating-point coprocessor with
                 vector\slash matrix instructions",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1324--1330",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An 80-bit floating-point coprocessor which implements
                 24 vector/matrix instructions and 22 mathematical
                 functions is described. This processor can execute
                 floating-point addition/rounding and pipelined
                 multiplication concurrently, under the control of
                 horizontal-type microinstructions. The SRT division
                 method and CORDIC trigonometrical algorithm are used
                 for a favorable cost/performance implementation. The
                 performance of 6.7 MFLOPS in the vector-matrix
                 multiplication at 20 MHz has been attained by the use
                 of parallel operations. The vector/matrix instruction
                 is about three times faster than conventional add and
                 multiply instructions. The chip has been fabricated in
                 1.2- mu m double-metal layer CMOS process containing
                 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "1.2 Micron; 20 MHz; 6.7 MFLOPS; 80 Bit; CMOS process;
                 CORDIC trigonometrical algorithm; Double-metal layer;
                 Floating-point coprocessor; Horizontal-type
                 microinstructions; Mathematical functions; Parallel
                 operations; Pipelined multiplication; SRT division
                 method; Vector/matrix instructions; VLSI
                 microprocessor",
  numericalindex = "Word length 8.0E+01 bit; Size 1.2E-06 m; Computer
                 speed 6.7E+06 FLOPS; Frequency 2.0E+07 Hz",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Instruction sets; Microprocessor chips; Parallel
                 architectures; Pipeline processing; Satellite
                 computers; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: Nakayama:1989:MFPa
author: T. Nakayama and S. Kojima and H. Harigai and H. Igarashi and K. Tamada and T. Toba
title: An 80b, 6.7 MFLOPS Floating-Point Processor with Vector/Matrix Instructions
crossref: Wuorinen:1989:DTP
pages: 52--53, 289
year: 1989
bibdate: Fri Dec 08 13:04:53 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 13:04:53 ???
acknowledgement: ack-nj
rawauthor: T. Nakayama and S. Kojima and H. Harigai and H. Igarashi and K. Tamada and T. Toba
rawtitle: An 80b, 6.7 {MFLOPS} Floating-Point Processor with {Vector/Matrix} Instructions
entry:
@InProceedings{Nakayama:1989:MFPa,
  author =       "T. Nakayama and S. Kojima and H. Harigai and H.
                 Igarashi and K. Tamada and T. Toba",
  title =        "An 80b, 6.7 {MFLOPS} Floating-Point Processor with
                 {Vector/Matrix} Instructions",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "52--53, 289",
  year =         "1989",
  bibdate =      "Fri Dec 08 13:04:53 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Nakayama:1989:MFPb
title: A 6.7-MFLOPS Floating-Point Coprocessor with Vector / Matrix Instructions
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1324--1330
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nj
rawtitle: A 6.7-{MFLOPS} Floating-Point Coprocessor with Vector\slash Matrix Instructions
author:
T. Nakayama and H. Harigai and S. Kojima and H. Kaneko and H. Igarashi and T. Toba and Y. Yamagami and Y. Yano

entry:
@Article{Nakayama:1989:MFPb,
  author =       "T. Nakayama and H. Harigai and S. Kojima and H. Kaneko
                 and H. Igarashi and T. Toba and Y. Yamagami and Y.
                 Yano",
  title =        "A 6.7-{MFLOPS} Floating-Point Coprocessor with
                 Vector\slash Matrix Instructions",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1324--1330",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "An 80-bit floating-point coprocessor which implements
                 24 vector/matrix instructions and 22 mathematical
                 functions is described. This processor can execute
                 floating-point addition/rounding and pipelined
                 multiplication concurrently, under the control
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Nowacki:1989:ABQ
author: C. L. Nowacki and J. D. Harris and M. N. Richard
title: Adaptive beamforming in quadratic residue number systems on a cluster array processor
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 624--628
year: 1989
DOI: https://doi.org/10.1109/MILCOM.1989.104000
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: C. L. Nowacki and J. D. Harris and M. N. Richard
rawtitle: Adaptive beamforming in quadratic residue number systems on a cluster array processor
entry:
@InProceedings{Nowacki:1989:ABQ,
  author =       "C. L. Nowacki and J. D. Harris and M. N. Richard",
  booktitle =    "{IEEE} Military Communications Conference, 1989.
                 {MILCOM '89}. Conference Record. Bridging the Gap.
                 Interoperability, Survivability, Security, 1989",
  title =        "Adaptive beamforming in quadratic residue number
                 systems on a cluster array processor",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "624--628",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MILCOM.1989.104000",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The authors describe a quadratic residue number system
                 (QRNS) implementation of the Leverrier algorithm for
                 computing the adjoint and determinant of a matrix on a
                 prototype parallel signal processor, called the cluster
                 array processor (CAP). Some \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ochs:1989:TPF
author: T. Ochs
title: Theory and practice (floating point arithmetic)
journal: j-COMP-LANG-MAG
volume: 6
number: 3
pages: 67--70, 72, 74, 77--78, 80--81
month: mar
monthnumber: 3
year: 1989
CODEN: COMLEF
ISSN: 0749-2839 OR 07492839
bibdate: Tue Dec 12 09:20:14 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:14 MST
fjournal: Computer Language Magazine
acknowledgement: ack-nhfb
thesaurus: Digital arithmetic; Program compilers
rawauthor: T. Ochs
rawtitle: Theory and practice (floating point arithmetic)
abstract:
The IEEE-754 standard for floating point arithmetic has inherent limits. The author presents a guide to NaNs, unnormals, underflows and signal infinite quantities.

keywords:
Compilers; Floating point arithmetic; IEEE-754 standard; NaNs; Signal infinite quantities; Underflows; Unnormals

rawabstract:
The IEEE-754 standard for floating point arithmetic has inherent limits. The author presents a guide to NaNs, unnormals, underflows and signal infinite quantities.

entry:
@Article{Ochs:1989:TPF,
  author =       "T. Ochs",
  title =        "Theory and practice (floating point arithmetic)",
  journal =      j-COMP-LANG-MAG,
  volume =       "6",
  number =       "3",
  pages =        "67--70, 72, 74, 77--78, 80--81",
  month =        mar,
  year =         "1989",
  CODEN =        "COMLEF",
  ISSN =         "0749-2839",
  bibdate =      "Tue Dec 12 09:20:14 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IEEE-754 standard for floating point arithmetic
                 has inherent limits. The author presents a guide to
                 NaNs, unnormals, underflows and signal infinite
                 quantities.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  classification = "C5230 (Digital arithmetic methods); C6150C
                 (Compilers, interpreters and other processors)",
  fjournal =     "Computer Language Magazine",
  keywords =     "Compilers; Floating point arithmetic; IEEE-754
                 standard; NaNs; Signal infinite quantities; Underflows;
                 Unnormals",
  thesaurus =    "Digital arithmetic; Program compilers",
}


bibtype: inproceedings
filename: fparith.bib
label: Petkovsek:1989:CDS
author: M. Petkovsek
title: Contiguous digit sets and local roundings
crossref: Ercegovac:1989:PSC
pages: 136--143
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Petkovsek.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: M. Petkovsek
rawtitle: Contiguous digit sets and local roundings
entry:
@InProceedings{Petkovsek:1989:CDS,
  author =       "M. Petkovsek",
  title =        "Contiguous digit sets and local roundings",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "136--143",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Petkovsek.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Pincin:1989:NAM
author: A. Pincin
title: A new algorithm for multiplication in finite fields
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 7
pages: 1045--1049
month: jul
monthnumber: 7
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.30855
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:40 MDT 2011
bibtimestamp: 2011.07.08 19:00:40 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=30855
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Pincin
rawtitle: A new algorithm for multiplication in finite fields
entry:
@Article{Pincin:1989:NAM,
  author =       "A. Pincin",
  title =        "A new algorithm for multiplication in finite fields",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "7",
  pages =        "1045--1049",
  month =        jul,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.30855",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=30855",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Prince:1989:FTF
author: Timothy Prince
title: Float Trig Functions For The C Preprocessor
journal: j-CUJ
volume: 7
number: 8
pages: 103--??
month: aug
monthnumber: 8
year: 1989
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: Timothy Prince
rawtitle: Float Trig Functions For The {C} Preprocessor
entry:
@Article{Prince:1989:FTF,
  author =       "Timothy Prince",
  title =        "Float Trig Functions For The {C} Preprocessor",
  journal =      j-CUJ,
  volume =       "7",
  number =       "8",
  pages =        "103--??",
  month =        aug,
  year =         "1989",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: inproceedings
filename: fparith.bib
label: Ramamoorthy:1989:HSA
author: P. A. Ramamoorthy and B. Potu
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
title: High-speed ADC using residue number system
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1063--1066
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266615
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: P. A. Ramamoorthy and B. Potu
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
rawtitle: High-speed {ADC} using residue number system
entry:
@InProceedings{Ramamoorthy:1989:HSA,
  author =       "P. A. Ramamoorthy and B. Potu",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "High-speed {ADC} using residue number system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1063--1066",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266615",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "An ADC (analog/digital converter) architecture based
                 on a residue number system (RNS) and multiple folding
                 of the input signal is described. The number of
                 comparators used is equal to the sum of moduli for
                 obtaining the dynamic range desired. An \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Rao:1989:RNF
author: B. D. Rao
booktitle: IEEE International Symposium on Circuits and Systems, 8--11 May 1989
title: Roundoff noise in floating point state space digital filters
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 724--727
year: 1989
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: B. D. Rao
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 8--11 May 1989
rawtitle: Roundoff noise in floating point state space digital filters
entry:
@InProceedings{Rao:1989:RNF,
  author =       "B. D. Rao",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 8--11 May 1989",
  title =        "Roundoff noise in floating point state space digital
                 filters",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "724--727",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The roundoff noise properties of floating-point
                 state-space digital filters are examined. It is shown
                 that the roundoff noise behavior of these filters is
                 related to their coefficient sensitivity. Expressions
                 for the variance of the output roundoff \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Ray:1989:MCA
author: G. A. Ray
booktitle: Proceedings of the 32nd Midwest Symposium on Circuits and Systems, 1989
title: Multiple core algorithms for residue number systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 833--836
year: 1989
DOI: https://doi.org/10.1109/MWSCAS.1989.101984
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: G. A. Ray
rawbooktitle: Proceedings of the 32nd Midwest Symposium on Circuits and Systems, 1989
rawtitle: Multiple core algorithms for residue number systems
entry:
@InProceedings{Ray:1989:MCA,
  author =       "G. A. Ray",
  booktitle =    "Proceedings of the 32nd Midwest Symposium on Circuits
                 and Systems, 1989",
  title =        "Multiple core algorithms for residue number systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "833--836",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MWSCAS.1989.101984",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The core function provides an easily implemented and
                 efficient means for performing the traditionally
                 difficult residue operations. However, two problems
                 with core algorithms are the difficulty in choosing
                 core coefficients and the many iterations \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Rishe:1989:LEN
author: Naphtali Rishe
title: Lexicographic Encoding of Numeric Data Fields
crossref: Ercegovac:1989:PSC
pages: 241--246
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Rishe.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Naphtali Rishe
rawtitle: Lexicographic Encoding of Numeric Data Fields
abstract:
This paper proposes a method of variable-radix representation of numeric data. The method allows compact representation of arbitrary numbers. Among its properties is that bitwise lexicographic comparison ($<$, $>$) is consistent with correct numeric comparison of numbers.

rawabstract:
This paper proposes a method of variable-radix representation of numeric data. The method allows compact representation of arbitrary numbers. Among its properties is that bitwise lexicographic comparison ($<$, $>$) is consistent with correct numeric comparison of numbers.

entry:
@InProceedings{Rishe:1989:LEN,
  author =       "Naphtali Rishe",
  title =        "Lexicographic Encoding of Numeric Data Fields",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "241--246",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Rishe.pdf",
  abstract =     "This paper proposes a method of variable-radix
                 representation of numeric data. The method allows
                 compact representation of arbitrary numbers. Among its
                 properties is that bitwise lexicographic comparison
                 ($<$, $>$) is consistent with correct numeric
                 comparison of numbers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: book
filename: fparith.bib
label: Robbins:1989:CXM
author: Kay A. Robbins and Steven Robbins
title: The Cray X-MP / Model 24
publisher: pub-SV
address: pub-SV:adr
pages: vi + 165
year: 1989
ISBN: 0-387-97089-4, 3-540-97089-4 OR 0387970894, 3540970894
ISBN13: 978-0-387-97089-9, 978-3-540-97089-7 OR 9780387970899, 9783540970897
LCCN: QA76.8 C72 R63 1989
bibdate: Sat Jan 29 18:17:38 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.01.29 18:17:38 ???
acknowledgement: ack-nhfb
rawauthor: Kay A. Robbins and Steven Robbins
rawtitle: The {Cray X-MP}\slash {Model} 24
entry:
@Book{Robbins:1989:CXM,
  author =       "Kay A. Robbins and Steven Robbins",
  title =        "The {Cray X-MP}\slash {Model} 24",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "vi + 165",
  year =         "1989",
  ISBN =         "0-387-97089-4, 3-540-97089-4",
  ISBN-13 =      "978-0-387-97089-9, 978-3-540-97089-7",
  LCCN =         "QA76.8 C72 R63 1989",
  bibdate =      "Sat Jan 29 18:17:38 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Saffari:1989:PDW
author: B. Saffari
title: Putting DSPs to work
journal: j-BYTE
volume: 14
number: 13
pages: 259--272
month: dec
monthnumber: 12
year: 1989
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 12 17:47:21 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.12 17:47:21 MDT
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
rawauthor: B. Saffari
rawtitle: Putting {DSPs} to work
keywords:
Digital filters; Feature extraction; Floating-point application-specific-IC DSPs; Image processing; Moments; Pattern recognition architecture; Sound; Space correction; Time

thesaurus:
Application specific integrated circuits; Computerised signal processing; Digital signal processing chips

entry:
@Article{Saffari:1989:PDW,
  author =       "B. Saffari",
  title =        "Putting {DSPs} to work",
  journal =      j-BYTE,
  volume =       "14",
  number =       "13",
  pages =        "259--272",
  month =        dec,
  year =         "1989",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 12 17:47:21 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B2570
                 (Semiconductor integrated circuits); B6140 (Signal
                 processing and detection); C5130 (Microprocessor
                 chips); C5260 (Digital signal processing)",
  fjournal =     "BYTE Magazine",
  keywords =     "Digital filters; Feature extraction; Floating-point
                 application-specific-IC DSPs; Image processing;
                 Moments; Pattern recognition architecture; Sound; Space
                 correction; Time",
  thesaurus =    "Application specific integrated circuits; Computerised
                 signal processing; Digital signal processing chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Santoro:1989:RAI
author: M. R. Santoro and G. Bewick and M. A. Horowitz
title: Rounding Algorithms for IEEE Multipliers
crossref: Ercegovac:1989:PSC
pages: 176--183
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Santoro.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: M. R. Santoro and G. Bewick and M. A. Horowitz
rawtitle: Rounding Algorithms for {IEEE} Multipliers
entry:
@InProceedings{Santoro:1989:RAI,
  author =       "M. R. Santoro and G. Bewick and M. A. Horowitz",
  title =        "Rounding Algorithms for {IEEE} Multipliers",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "176--183",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Santoro.pdf",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  keywords =     "ARITH-9",
  summary =      "Several technology independent rounding algorithms for
                 multiplying normalized numbers are presented. The first
                 is a simple rounding algorithm suitable for software
                 simulation or moderate performance hardware
                 multipliers. The next two algorithms are \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Sasaki:1989:AAD
author: Tateaki Sasaki and Mutsuko Sasaki
journal: J. Inform. Process.
volume: 12
number: 4
pages: 394--403
year: 1989
MRclass: 65G05 (65Y20)
MRnumber: 91h:65069
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
acknowledgement: ack-nhfb
rawauthor: Tateaki Sasaki and Mutsuko Sasaki
title:
Analysis of accuracy decreasing in polynomial remainder sequence with floating-point number coefficients

rawtitle:
Analysis of accuracy decreasing in polynomial remainder sequence with floating-point number coefficients

entry:
@Article{Sasaki:1989:AAD,
  author =       "Tateaki Sasaki and Mutsuko Sasaki",
  title =        "Analysis of accuracy decreasing in polynomial
                 remainder sequence with floating-point number
                 coefficients",
  journal =      "J. Inform. Process.",
  volume =       "12",
  number =       "4",
  pages =        "394--403",
  year =         "1989",
  MRclass =      "65G05 (65Y20)",
  MRnumber =     "91h:65069",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schwarz:1989:IIP
author: Jerry Schwarz
title: Implementing infinite precision arithmetic
crossref: Ercegovac:1989:PSC
pages: 10--17
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Schwarz.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Jerry Schwarz
rawtitle: Implementing infinite precision arithmetic
entry:
@InProceedings{Schwarz:1989:IIP,
  author =       "Jerry Schwarz",
  title =        "Implementing infinite precision arithmetic",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "10--17",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Schwarz.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Scott:1989:FRM
author: M. Scott
title: Fast rounding in multiprecision floating-slash arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 7
pages: 1049--1052
month: jul
monthnumber: 7
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.30856
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 16 11:25:03 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:03 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Scott
rawtitle: Fast rounding in multiprecision floating-slash arithmetic
entry:
@Article{Scott:1989:FRM,
  author =       "M. Scott",
  title =        "Fast rounding in multiprecision floating-slash
                 arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "7",
  pages =        "1049--1052",
  month =        jul,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.30856",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 16 11:25:03 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "A computational algorithm is described which quickly
                 rounds large fractions into a fixed-length
                 multiprecision floating-slash representation, using
                 single-precision operations where possible. An easily
                 calculated criterion for terminating the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Shenoy:1989:FBE
author: A. P. Shenoy and R. Kumaresan
title: Fast base extension using a redundant modulus in RNS
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 2
pages: 292--297
month: feb
monthnumber: 2
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.16508
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:38 MDT 2011
bibtimestamp: 2011.07.08 19:00:38 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16508
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. P. Shenoy and R. Kumaresan
rawtitle: Fast base extension using a redundant modulus in {RNS}
entry:
@Article{Shenoy:1989:FBE,
  author =       "A. P. Shenoy and R. Kumaresan",
  title =        "Fast base extension using a redundant modulus in
                 {RNS}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "2",
  pages =        "292--297",
  month =        feb,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.16508",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:38 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16508",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Shimazu:1989:MFP
title: A 50 MHz 24b Floating-Point DSP
crossref: Wuorinen:1989:DTP
pages: 44--45, 285
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-mfc
affiliation: Mitsubishi, Hyogo, Japan
rawtitle: A 50 {MHz} 24b Floating-Point {DSP}
author:
Y. Shimazu and T. Kengaku and T. Fujiyama and E. Teraoka and T. Ohno and T. Tokuda and O. Tomisawa and S. Tsujimichi

abstract:
A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized.

keywords:
1 Micron; 24 Bit; 40 Ns; 50 MHz; 600 MW; Built-in self-test; Circuit design techniques; Clock frequency; Communication applications; Data register; Double-metal CMOS; Floating-point digital signal processor; I/O registers; Instruction set; Linear feedback shift registers; Machine cycle time; On-chip IROM; Power dissipation; Serial input registers; Serial output registers; Speech processing; WSi/sub 2/ technology

thesaurus:
CMOS integrated circuits; Digital arithmetic; Digital signal processing chips; Speech analysis and processing

rawabstract:
A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized.

rawauthor:
Y. Shimazu and T. Kengaku and T. Fujiyama and E. Teraoka and T. Ohno and T. Tokuda and O. Tomisawa and S. Tsujimichi

entry:
@InProceedings{Shimazu:1989:MFP,
  author =       "Y. Shimazu and T. Kengaku and T. Fujiyama and E.
                 Teraoka and T. Ohno and T. Tokuda and O. Tomisawa and
                 S. Tsujimichi",
  title =        "A 50 {MHz} 24b Floating-Point {DSP}",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "44--45, 285",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 24-bit floating-point digital signal processor (DSP)
                 has been developed primarily for speech processing and
                 communication applications. The chip uses 1.0- mu m
                 double-metal CMOS with tungsten silicide technology.
                 The instruction set is upward compatible with an 18-bit
                 DSP. Novel circuit design techniques allowing 40-ns
                 machine cycle time at 50-MHz clock and less than 600-mW
                 power dissipation are described. A built-in self-test
                 is prepared using on-chip IROM and the two 24-bit
                 linear feedback shift registers which are included in
                 I/O registers such as the data register, the serial
                 input registers, and the serial output registers. The
                 DSP design features are summarized.",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  affiliation =  "Mitsubishi, Hyogo, Japan",
  chemicalindex = "WSi2/int Si2/int Si/int W/int WSi2/bin Si2/bin Si/bin
                 W/bin",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); B6130 (Speech analysis and
                 processing techniques); C5130 (Microprocessor chips);
                 C5230 (Digital arithmetic methods); C5260 (Digital
                 signal processing)",
  keywords =     "1 Micron; 24 Bit; 40 Ns; 50 MHz; 600 MW; Built-in
                 self-test; Circuit design techniques; Clock frequency;
                 Communication applications; Data register; Double-metal
                 CMOS; Floating-point digital signal processor; I/O
                 registers; Instruction set; Linear feedback shift
                 registers; Machine cycle time; On-chip IROM; Power
                 dissipation; Serial input registers; Serial output
                 registers; Speech processing; WSi/sub 2/ technology",
  numericalindex = "Frequency 5.0E+07 Hz; Word length 2.4E+01 bit; Time
                 4.0E-08 s; Power 6.0E-01 W; Size 1.0E-06 m",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic; Digital
                 signal processing chips; Speech analysis and
                 processing",
}


bibtype: article
filename: fparith.bib
label: Sinha:1989:FPA
author: B. P. Sinha and P. K. Srimani
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 3
pages: 424--431
month: mar
monthnumber: 3
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.21128
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:38 MDT 2011
bibtimestamp: 2011.07.08 19:00:38 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=21128
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: B. P. Sinha and P. K. Srimani
title:
Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

rawtitle:
Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

entry:
@Article{Sinha:1989:FPA,
  author =       "B. P. Sinha and P. K. Srimani",
  title =        "Fast parallel algorithms for binary multiplication and
                 their implementation on systolic architectures",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "3",
  pages =        "424--431",
  month =        mar,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.21128",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:38 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=21128",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Sit:1989:MFP
author: H. P. Sit and M. R. Nofal and S. Kimn
title: An 80 MFLOPS Floating-point Engine in the Intel i860TM Processor
crossref: IEEE:1989:PII
pages: 374--379
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-mfc
affiliation: Intel Corp., Santa Clara, CA, USA
rawauthor: H. P. Sit and M. R. Nofal and S. Kimn
rawtitle: An 80 {MFLOPS} Floating-point Engine in the {Intel} i860{\TM} Processor
abstract:
The i860 processor is a 64-b microprocessor with 1.02 million transistors. It has a 64-b external data bus and a 32-b external address bus. It is fabricated with Intel's CHMOS IV technology (a 1- mu m double-metal process). The die size is approximately 10 mm*15 mm. First silicon is functional over commercial temperature and voltage ranges with an execution speed of 40 MHz. The floating-point engine consists of a pipelined adder and a pipelined multiplier, incorporates a special hardware to support the dual operation instructions, and operates synchronously with the RISC (reduced-instruction-set computer) core to execute up to three operations per clock. Its high performance lends itself well to a numeric-intensive computation environment, including vector processing.

keywords:
1 Micron; 10 Mm; 15 Mm; 32 Bit; 40 MHz; 64 Bit; 80 MFLOPS; 80 MFLOPS floating-point engine; CHMOS IV technology; CMOS; Commercial temperature; Die size; Double-metal process; Dual operation instructions; Execution speed; Floating-point engine; Intel i860 processor; Numeric-intensive computation environment; Pipelined adder; Pipelined multiplier; Reduced-instruction-set computer; RISC core; Three operations per clock; Vector processing

thesaurus:
CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Reduced instruction set computing

rawabstract:
The i860 processor is a 64-b microprocessor with 1.02 million transistors. It has a 64-b external data bus and a 32-b external address bus. It is fabricated with Intel's CHMOS IV technology (a 1- mu m double-metal process). The die size is approximately 10 mm*15 mm. First silicon is functional over commercial temperature and voltage ranges with an execution speed of 40 MHz. The floating-point engine consists of a pipelined adder and a pipelined multiplier, incorporates a special hardware to support the dual operation instructions, and operates synchronously with the RISC (reduced-instruction-set computer) core to execute up to three operations per clock. Its high performance lends itself well to a numeric-intensive computation environment, including vector processing.

entry:
@InProceedings{Sit:1989:MFP,
  author =       "H. P. Sit and M. R. Nofal and S. Kimn",
  title =        "An 80 {MFLOPS} Floating-point Engine in the {Intel}
                 i860{\TM} Processor",
  crossref =     "IEEE:1989:PII",
  pages =        "374--379",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The i860 processor is a 64-b microprocessor with 1.02
                 million transistors. It has a 64-b external data bus
                 and a 32-b external address bus. It is fabricated with
                 Intel's CHMOS IV technology (a 1- mu m double-metal
                 process). The die size is approximately 10 mm*15 mm.
                 First silicon is functional over commercial temperature
                 and voltage ranges with an execution speed of 40 MHz.
                 The floating-point engine consists of a pipelined adder
                 and a pipelined multiplier, incorporates a special
                 hardware to support the dual operation instructions,
                 and operates synchronously with the RISC
                 (reduced-instruction-set computer) core to execute up
                 to three operations per clock. Its high performance
                 lends itself well to a numeric-intensive computation
                 environment, including vector processing.",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  affiliation =  "Intel Corp., Santa Clara, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips)",
  keywords =     "1 Micron; 10 Mm; 15 Mm; 32 Bit; 40 MHz; 64 Bit; 80
                 MFLOPS; 80 MFLOPS floating-point engine; CHMOS IV
                 technology; CMOS; Commercial temperature; Die size;
                 Double-metal process; Dual operation instructions;
                 Execution speed; Floating-point engine; Intel i860
                 processor; Numeric-intensive computation environment;
                 Pipelined adder; Pipelined multiplier;
                 Reduced-instruction-set computer; RISC core; Three
                 operations per clock; Vector processing",
  numericalindex = "Word length 6.4E+01 bit; Frequency 4.0E+07 Hz; Word
                 length 3.2E+01 bit; Computer speed 8.0E+07 FLOPS; Size
                 1.0E-06 m; Size 1.0E-02 m; Size 1.5E-02 m",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Reduced instruction set
                 computing",
}


bibtype: inproceedings
filename: fparith.bib
label: Skavantzos:1989:DFC
author: A. Skavantzos
booktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
title: Designing fast convolvers for residue number systems
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 497--501
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266586
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Skavantzos
rawbooktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
rawtitle: Designing fast convolvers for residue number systems
entry:
@InProceedings{Skavantzos:1989:DFC,
  author =       "A. Skavantzos",
  booktitle =    "Twenty-Third Asilomar Conference on Signals, Systems
                 and Computers, 1989",
  title =        "Designing fast convolvers for residue number systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "497--501",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266586",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
}


bibtype: article
filename: fparith.bib
label: Smith:1989:CSB
author: S. G. Smith
title: Comments on ``A signed bit-sequential multiplier'' by T. Rhyne and N. R. Strader II
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 9
pages: 1328--1330
month: sep
monthnumber: 9
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.29473
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:41 MDT 2011
bibtimestamp: 2011.07.08 19:00:41 MDT
note: See cite Rhyne:1986:SBS.
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=29473
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. G. Smith
rawnote: See \cite{Rhyne:1986:SBS}.
rawtitle: Comments on {``A signed bit-sequential multiplier''} by {T. Rhyne} and {N. R. Strader II}
entry:
@Article{Smith:1989:CSB,
  author =       "S. G. Smith",
  title =        "Comments on {``A signed bit-sequential multiplier''}
                 by {T. Rhyne} and {N. R. Strader II}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "9",
  pages =        "1328--1330",
  month =        sep,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.29473",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  note =         "See \cite{Rhyne:1986:SBS}.",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=29473",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Spaderna:1989:IFP
author: D. Spaderna and P. Green and K. Tam and T. Datta and M. Kumar
title: An integrated floating point vector processor for DSP and scientific computing
crossref: IEEE:1989:PII
pages: 8--13
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Sharp Microelectron. Technol. Inc., Vancouver, WA, USA
thesaurus: Digital signal processing chips; Parallel architectures
rawauthor: D. Spaderna and P. Green and K. Tam and T. Datta and M. Kumar
rawtitle: An integrated floating point vector processor for {DSP} and scientific computing
abstract:
The architecture of a high-performance floating-point microprocessor intended for computation-intensive applications is presented. Utilizing a massively parallel execution unit, very high bandwidth onchip memory, and extensive parallel address calculation hardware, the processor is expected to achieve peak execution rates of 400 MFLOPS for single-precision floating-point numbers. This type of performance is competitive with that of popular mainframe vector processors.

keywords:
400 MFLOPS; Computation-intensive applications; DSP; Floating-point microprocessor; Integrated floating point vector processor; Mainframe vector processors; Massively parallel execution unit; Onchip memory; Parallel address calculation hardware; Peak execution rates; Scientific computing; Single-precision floating-point numbers

rawabstract:
The architecture of a high-performance floating-point microprocessor intended for computation-intensive applications is presented. Utilizing a massively parallel execution unit, very high bandwidth onchip memory, and extensive parallel address calculation hardware, the processor is expected to achieve peak execution rates of 400 MFLOPS for single-precision floating-point numbers. This type of performance is competitive with that of popular mainframe vector processors.

entry:
@InProceedings{Spaderna:1989:IFP,
  author =       "D. Spaderna and P. Green and K. Tam and T. Datta and
                 M. Kumar",
  title =        "An integrated floating point vector processor for
                 {DSP} and scientific computing",
  crossref =     "IEEE:1989:PII",
  pages =        "8--13",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The architecture of a high-performance floating-point
                 microprocessor intended for computation-intensive
                 applications is presented. Utilizing a massively
                 parallel execution unit, very high bandwidth onchip
                 memory, and extensive parallel address calculation
                 hardware, the processor is expected to achieve peak
                 execution rates of 400 MFLOPS for single-precision
                 floating-point numbers. This type of performance is
                 competitive with that of popular mainframe vector
                 processors.",
  acknowledgement = ack-nhfb,
  affiliation =  "Sharp Microelectron. Technol. Inc., Vancouver, WA,
                 USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C5260 (Digital signal processing)",
  keywords =     "400 MFLOPS; Computation-intensive applications; DSP;
                 Floating-point microprocessor; Integrated floating
                 point vector processor; Mainframe vector processors;
                 Massively parallel execution unit; Onchip memory;
                 Parallel address calculation hardware; Peak execution
                 rates; Scientific computing; Single-precision
                 floating-point numbers",
  numericalindex = "Computer speed 4.0E+08 FLOPS",
  thesaurus =    "Digital signal processing chips; Parallel
                 architectures",
}


bibtype: inproceedings
filename: fparith.bib
label: Stearns:1989:SFD
author: C. C. Stearns
title: Subtractive floating-point division and square root for VLSI DSP
crossref: IEE:1989:EEC
pages: 405--409
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
rawauthor: C. C. Stearns
rawtitle: Subtractive floating-point division and square root for {VLSI DSP}
abstract:
This paper describes recent architectural developments in VLSI design for real-time digital signal processing. In particular, floating point division and floating point square root architectures applicable to both adaptive filtering, standard deviation computations, and general purpose processing are discussed. Emphasis here is on the internal architectures of the arithmetic units not on their applications. The research presented in this paper has been proven feasible and reliable from extensive gate-level simulation and fabrication in silicon.

keywords:
Adaptive filtering; Arithmetic units; CMOS technology; Floating point division; Floating point square root architectures; Gate-level simulation; General purpose processing; Real-time digital signal processing; Semiconductor; Standard deviation computations; VLSI DSP

thesaurus:
Adaptive filters; CMOS integrated circuits; Digital arithmetic; Digital signal processing chips; VLSI

rawabstract:
This paper describes recent architectural developments in VLSI design for real-time digital signal processing. In particular, floating point division and floating point square root architectures applicable to both adaptive filtering, standard deviation computations, and general purpose processing are discussed. Emphasis here is on the internal architectures of the arithmetic units not on their applications. The research presented in this paper has been proven feasible and reliable from extensive gate-level simulation and fabrication in silicon.

entry:
@InProceedings{Stearns:1989:SFD,
  author =       "C. C. Stearns",
  title =        "Subtractive floating-point division and square root
                 for {VLSI DSP}",
  crossref =     "IEE:1989:EEC",
  pages =        "405--409",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper describes recent architectural developments
                 in VLSI design for real-time digital signal processing.
                 In particular, floating point division and floating
                 point square root architectures applicable to both
                 adaptive filtering, standard deviation computations,
                 and general purpose processing are discussed. Emphasis
                 here is on the internal architectures of the arithmetic
                 units not on their applications. The research presented
                 in this paper has been proven feasible and reliable
                 from extensive gate-level simulation and fabrication in
                 silicon.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B1270F
                 (Digital filters); B2570D (CMOS integrated circuits);
                 C5230 (Digital arithmetic methods); C5240 (Digital
                 filters); C5260 (Digital signal processing)",
  keywords =     "Adaptive filtering; Arithmetic units; CMOS technology;
                 Floating point division; Floating point square root
                 architectures; Gate-level simulation; General purpose
                 processing; Real-time digital signal processing;
                 Semiconductor; Standard deviation computations; VLSI
                 DSP",
  thesaurus =    "Adaptive filters; CMOS integrated circuits; Digital
                 arithmetic; Digital signal processing chips; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: Stearns:1989:SFP
author: C. C. Stearns
booktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
title: Subtractive floating-point division and square root for VLSI DSP
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 405--409
year: 1989
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: C. C. Stearns
rawbooktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
rawtitle: Subtractive floating-point division and square root for {VLSI} {DSP}
entry:
@InProceedings{Stearns:1989:SFP,
  author =       "C. C. Stearns",
  booktitle =    "European Conference on Circuit Theory and Design, 5--8
                 Sep 1989",
  title =        "Subtractive floating-point division and square root
                 for {VLSI} {DSP}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "405--409",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper describes recent architectural developments
                 in VLSI design for real-time digital signal processing.
                 In particular, floating point division and floating
                 point square root architectures applicable to both
                 adaptive filtering, standard \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Tang:1989:TCA
author: P. T. P. Tang
title: Testing Computer Arithmetic by Elementary Number Theory
institution: Mathematics and Computer Science Division, Argonne National Laboratory
month: aug
monthnumber: 8
year: 1989
bibdate: Thu Sep 01 11:57:30 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 11:57:30 ???
keywords: floating-point testing
acknowledgement: ack-nj
rawauthor: P. T. P. Tang
rawtitle: Testing Computer Arithmetic by Elementary Number Theory
entry:
@TechReport{Tang:1989:TCA,
  author =       "P. T. P. Tang",
  title =        "Testing Computer Arithmetic by Elementary Number
                 Theory",
  institution =  "Mathematics and Computer Science Division, Argonne
                 National Laboratory",
  pages =        "??",
  month =        aug,
  year =         "1989",
  bibdate =      "Thu Sep 01 11:57:30 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  keywords =     "floating-point testing",
}


bibtype: article
filename: fparith.bib
label: Tang:1989:TDI
author: Ping Tak Peter Tang
title: Table-Driven Implementation of the Exponential Function in IEEE Floating-Point Arithmetic
journal: j-TOMS
volume: 15
number: 2
pages: 144--157
month: jun
monthnumber: 6
year: 1989
CODEN: ACMSCU
DOI: https://doi.org/10.1145/63522.214389
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sun Sep 04 22:47:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.04 22:47:40 ???
URL: http://www.acm.org/pubs/citations/journals/toms/1989-15-2/p144-tang/
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: algorithms
acknowledgement: ack-nj
journalURL: https://dl.acm.org/loi/toms
rawauthor: Ping Tak Peter Tang
rawtitle: Table-Driven Implementation of the Exponential Function in {IEEE} Floating-Point Arithmetic
abstract:
Algorithms and implementation details for the exponential function in both single- and double-precision of IEEE 754 arithmetic are presented here. With a table of moderate size, the implementations need only working-precision arithmetic and are provably accurate to within 0.54 ulp as long as the final result does not underflow. When the final result suffers gradual underflow, the error is still no worse than 0.77 ulp.

subject:
bf G.1.0: Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic. bf G.1.0: Mathematics of Computing, NUMERICAL ANALYSIS, General, Error analysis. bf G.1.0: Mathematics of Computing, NUMERICAL ANALYSIS, General, Numerical algorithms. bf G.4: Mathematics of Computing, MATHEMATICAL SOFTWARE, Algorithm analysis.

rawabstract:
Algorithms and implementation details for the exponential function in both single- and double-precision of IEEE 754 arithmetic are presented here. With a table of moderate size, the implementations need only working-precision arithmetic and are provably accurate to within 0.54 ulp as long as the final result does not underflow. When the final result suffers gradual underflow, the error is still no worse than 0.77 ulp.

entry:
@Article{Tang:1989:TDI,
  author =       "Ping Tak Peter Tang",
  title =        "Table-Driven Implementation of the Exponential
                 Function in {IEEE} Floating-Point Arithmetic",
  journal =      j-TOMS,
  volume =       "15",
  number =       "2",
  pages =        "144--157",
  month =        jun,
  year =         "1989",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/63522.214389",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sun Sep 04 22:47:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/citations/journals/toms/1989-15-2/p144-tang/",
  abstract =     "Algorithms and implementation details for the
                 exponential function in both single- and
                 double-precision of IEEE 754 arithmetic are presented
                 here. With a table of moderate size, the
                 implementations need only working-precision arithmetic
                 and are provably accurate to within 0.54 ulp as long as
                 the final result does not underflow. When the final
                 result suffers gradual underflow, the error is still no
                 worse than 0.77 ulp.",
  acknowledgement = ack-nj,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "algorithms",
  subject =      "{\bf G.1.0}: Mathematics of Computing, NUMERICAL
                 ANALYSIS, General, Computer arithmetic. {\bf G.1.0}:
                 Mathematics of Computing, NUMERICAL ANALYSIS, General,
                 Error analysis. {\bf G.1.0}: Mathematics of Computing,
                 NUMERICAL ANALYSIS, General, Numerical algorithms. {\bf
                 G.4}: Mathematics of Computing, MATHEMATICAL SOFTWARE,
                 Algorithm analysis.",
}


bibtype: book
filename: fparith.bib
label: Thies:1989:PXA
author: Klaus-Dieter Thies
title: PC / XT / AT Numerik Buch toenglish PC / XT / AT Numeric Book endtoenglish
publisher: pub-TEWI
address: pub-TEWI:adr
pages: xiii + 707
year: 1989
ISBN: 3-89362-033-8 OR 3893620338
ISBN13: 978-3-89362-033-3 OR 9783893620333
bibdate: Sat Nov 09 10:09:41 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 10:09:41 ???
acknowledgement: ack-nj
rawauthor: Klaus-Dieter Thies
rawtitle:
{PC\slash {XT}\slash {AT} Numerik Buch} \toenglish {PC\slash XT\slash AT Numeric Book} \endtoenglish

entry:
@Book{Thies:1989:PXA,
  author =       "Klaus-Dieter Thies",
  title =        "{PC\slash {XT}\slash {AT} Numerik Buch} \toenglish
                 {PC\slash XT\slash AT Numeric Book} \endtoenglish",
  publisher =    pub-TEWI,
  address =      pub-TEWI:adr,
  pages =        "xiii + 707",
  year =         "1989",
  ISBN =         "3-89362-033-8",
  ISBN-13 =      "978-3-89362-033-3",
  LCCN =         "????",
  bibdate =      "Sat Nov 09 10:09:41 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Tu:1989:DLD
author: Paul K. Tu and M. D. Ercegovac
title: Design of on-line division unit
crossref: Ercegovac:1989:PSC
pages: 42--49
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Tu.pdf
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, California University, Los Angeles, CA, USA
thesaurus: Digital arithmetic; Large scale integration; Logic arrays
rawauthor: Paul K. Tu and M. D. Ercegovac
rawtitle: Design of on-line division unit
abstract:
A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78%.

keywords:
24 Ns Cycle time; ARITH-9; Gate array implementation; LSI Logic LL9320P chip; Online division unit design; Radix-2 floating-point online division algorithm; Utilization factor

rawabstract:
A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78\%.

entry:
@InProceedings{Tu:1989:DLD,
  author =       "Paul K. Tu and M. D. Ercegovac",
  title =        "Design of on-line division unit",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "42--49",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Tu.pdf",
  abstract =     "A gate array implementation of a radix-2
                 floating-point online division algorithm is presented.
                 The design requires 111 equivalent gates per bit and
                 has a cycle time of 24 ns. For 8-b exponent and 24-b
                 mantissa, the design requires 2497 equivalent gates and
                 can fit on an LSI Logic LL9320P chip with a utilization
                 factor 78\%.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, California University,
                 Los Angeles, CA, USA",
  classification = "B1265B (Logic circuits); B2570 (Semiconductor
                 integrated circuits); C5120 (Logic and switching
                 circuits); C5230 (Digital arithmetic methods)",
  keywords =     "24 Ns Cycle time; ARITH-9; Gate array implementation;
                 LSI Logic LL9320P chip; Online division unit design;
                 Radix-2 floating-point online division algorithm;
                 Utilization factor",
  numericalindex = "Time 2.4E-08 s",
  thesaurus =    "Digital arithmetic; Large scale integration; Logic
                 arrays",
}


bibtype: inproceedings
filename: fparith.bib
label: Turner:1989:SIS
author: Peter R. Turner
title: A software implementation of SLI arithmetic
crossref: Ercegovac:1989:PSC
pages: 18--24
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Turner.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Peter R. Turner
rawtitle: A software implementation of {SLI} arithmetic
entry:
@InProceedings{Turner:1989:SIS,
  author =       "Peter R. Turner",
  title =        "A software implementation of {SLI} arithmetic",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "18--24",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Turner.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Turrini:1989:OGD
author: Silvio Turrini
title: Optimal group distribution in carry-skip adders
crossref: Ercegovac:1989:PSC
pages: 96--103
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Turrini.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Silvio Turrini
rawtitle: Optimal group distribution in carry-skip adders
entry:
@InProceedings{Turrini:1989:OGD,
  author =       "Silvio Turrini",
  title =        "Optimal group distribution in carry-skip adders",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "96--103",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Turrini.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Unguru:1989:BRB
author: Sabetai Unguru
journal: j-ISIS
volume: 80
number: 2
pages: 298--299
month: jun
monthnumber: 6
year: 1989
CODEN: ISISA4
ISSN: 0021-1753 (print), 1545-6994 (electronic) OR 00211753 (print), 15456994 (electronic)
ISSNL: 0021-1753 OR 00211753
bibdate: Tue Jul 30 21:23:50 MDT 2013
bibtimestamp: 2013.07.30 21:23:50 MDT
URL: http://www.jstor.org/stable/234607
fjournal: Isis
acknowledgement: ack-nhfb
journalURL: http://www.jstor.org/journal/isis
rawauthor: Sabetai Unguru
title:
Book Review: booktitle A Mathematical History of Division in Extreme and Mean Ratio by Roger Herz-Fischler

bibsource:
http://www.jstor.org/action/showPublication?journalCode=isis; http://www.jstor.org/stable/i211193; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/isis1980.bib

rawtitle:
Book Review: {{\booktitle{A Mathematical History of Division in Extreme and Mean Ratio}} by Roger Herz-Fischler}

entry:
@Article{Unguru:1989:BRB,
  author =       "Sabetai Unguru",
  title =        "Book Review: {{\booktitle{A Mathematical History of
                 Division in Extreme and Mean Ratio}} by Roger
                 Herz-Fischler}",
  journal =      j-ISIS,
  volume =       "80",
  number =       "2",
  pages =        "298--299",
  month =        jun,
  year =         "1989",
  CODEN =        "ISISA4",
  ISSN =         "0021-1753 (print), 1545-6994 (electronic)",
  ISSN-L =       "0021-1753",
  bibdate =      "Tue Jul 30 21:23:50 MDT 2013",
  bibsource =    "http://www.jstor.org/action/showPublication?journalCode=isis;
                 http://www.jstor.org/stable/i211193;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/isis1980.bib",
  URL =          "http://www.jstor.org/stable/234607",
  acknowledgement = ack-nhfb,
  fjournal =     "Isis",
  journal-URL =  "http://www.jstor.org/journal/isis",
}


bibtype: article
filename: fparith.bib
label: VanVeen:1989:MBC
author: B. D. Van Veen and R. Baraniuk
title: Matrix based computation of floating-point roundoff noise
journal: j-IEEE-TRANS-ACOUST-SPEECH
volume: 37
number: 12
pages: 1995--1998
month: dec
monthnumber: 12
year: 1989
CODEN: IETABA
ISSN: 0096-3518 OR 00963518
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Acoustics, Speech, and Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29
rawauthor: B. D. {Van Veen} and R. Baraniuk
rawtitle: Matrix based computation of floating-point roundoff noise
entry:
@Article{VanVeen:1989:MBC,
  author =       "B. D. {Van Veen} and R. Baraniuk",
  title =        "Matrix based computation of floating-point roundoff
                 noise",
  journal =      j-IEEE-TRANS-ACOUST-SPEECH,
  volume =       "37",
  number =       "12",
  pages =        "1995--1998",
  month =        dec,
  year =         "1989",
  CODEN =        "IETABA",
  ISSN =         "0096-3518",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Acoustics, Speech, and Signal
                 Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29",
  summary =      "A matrix-based procedure is presented for computing
                 the output roundoff power for filters implemented with
                 floating-point arithmetic. The filter's computational
                 structure is represented in terms of a product of
                 matrices, known as a factored state \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Vassiliadis:1989:GPO
author: S. Vassiliadis and E. M. Schwarz and D. J. Hanrahan
title: A General Proof for Overlapped Multiple-Bit Scanning Multiplications
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 2
pages: 172--183
month: feb
monthnumber: 2
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.16494
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:37 MDT 2011
bibtimestamp: 2011.07.08 19:00:37 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16494
fjournal: IEEE Transactions on Computers
acknowledgement: ack-mfc
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Vassiliadis and E. M. Schwarz and D. J. Hanrahan
rawtitle: A General Proof for Overlapped Multiple-Bit Scanning Multiplications
entry:
@Article{Vassiliadis:1989:GPO,
  author =       "S. Vassiliadis and E. M. Schwarz and D. J. Hanrahan",
  title =        "A General Proof for Overlapped Multiple-Bit Scanning
                 Multiplications",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "2",
  pages =        "172--183",
  month =        feb,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.16494",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:37 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16494",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Vassiliadis:1989:SMF
author: S. Vassiliadis and D. S. Lemon and M. Putrino
title: S/370 sign-magnitude floating-point adder
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 4
pages: 1062--1070
month: aug
monthnumber: 8
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: IBM Corp., Endicott, NY, USA
thesaurus: Adders; Bipolar integrated circuits; Carry logic; Integrated logic circuits; NAND circuits
rawauthor: S. Vassiliadis and D. S. Lemon and M. Putrino
rawtitle: {S/370} sign-magnitude floating-point adder
abstract:
A 56-bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal (4LM) bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the floating-point adder and the error-detecting logic requires one chip of 7500 automatically placed and wired NAND gates. The chip die size is 7.39 x 7.39 mm super(2) and it is mounted on a metalized ceramic (MC) substrate. The floating-point sign-magnitude adder chip is used in the IBM 9370 model 60 (9375) Engineering Scientific Accelerator (ESA) card.

keywords:
algorithms; arithmetic circuits; Carry lookahead scheme; Chip die size; design; End-around carry; Engineering scientific accelerator card; Error-detecting logic; floating point arithmetic; Four-level metal bipolar master-slice technology; IBM 9370 Model 60; logic circuits; Metallized ceramic substrate; NAND gates; S/370; Sign-magnitude floating-point adder

rawabstract:
A 56-bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal (4LM) bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the floating-point adder and the error-detecting logic requires one chip of 7500 automatically placed and wired NAND gates. The chip die size is 7.39 x 7.39 mm super(2) and it is mounted on a metalized ceramic (MC) substrate. The floating-point sign-magnitude adder chip is used in the IBM 9370 model 60 (9375) Engineering Scientific Accelerator (ESA) card.

entry:
@Article{Vassiliadis:1989:SMF,
  author =       "S. Vassiliadis and D. S. Lemon and M. Putrino",
  title =        "{S/370} sign-magnitude floating-point adder",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "4",
  pages =        "1062--1070",
  month =        aug,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 56-bit S/370 sign-magnitude adder for floating-point
                 operations implemented in a four-level metal (4LM)
                 bipolar master-slice technology is described. The
                 design of the two-to-one adder is based on a carry
                 lookahead scheme with implicit calculation of the
                 end-around carry. The implementation of the
                 floating-point adder and the error-detecting logic
                 requires one chip of 7500 automatically placed and
                 wired NAND gates. The chip die size is 7.39 x 7.39 mm
                 super(2) and it is mounted on a metalized ceramic (MC)
                 substrate. The floating-point sign-magnitude adder chip
                 is used in the IBM 9370 model 60 (9375) Engineering
                 Scientific Accelerator (ESA) card.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Endicott, NY, USA",
  classification = "B1265B (Logic circuits); B2570B (Bipolar integrated
                 circuits); C5120 (Logic and switching circuits)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "algorithms; arithmetic circuits; Carry lookahead
                 scheme; Chip die size; design; End-around carry;
                 Engineering scientific accelerator card;
                 Error-detecting logic; floating point arithmetic;
                 Four-level metal bipolar master-slice technology; IBM
                 9370 Model 60; logic circuits; Metallized ceramic
                 substrate; NAND gates; S/370; Sign-magnitude
                 floating-point adder",
  summary =      "A 56 bit S/370 sign-magnitude adder for floating-point
                 operations implemented in a four-level metal bipolar
                 master-slice technology is described. The design of the
                 two-to-one adder is based on a carry lookahead scheme
                 with implicit calculation of the \ldots{}",
  thesaurus =    "Adders; Bipolar integrated circuits; Carry logic;
                 Integrated logic circuits; NAND circuits",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1989:FSAa
author: H. Volzke
journal: j-MC
volume: 1
pages: 66--73
year: 1989
ISSN: 0720-4442, 0941-777x , 0943-5409 OR 07204442, 0941777x , 09435409
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 4: Die Konvertierungsroutinen toenglish Floating-point Arithmetic and its IEEE Specification. Part 4: Conversion Routines endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 4: Die Konvertierungsroutinen} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 4: Conversion Routines} \endtoenglish

entry:
@Article{Voelzke:1989:FSAa,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 4: Die
                 Konvertierungsroutinen} \toenglish {Floating-point
                 Arithmetic and its IEEE Specification. Part 4:
                 Conversion Routines} \endtoenglish",
  journal =      j-MC,
  volume =       "1",
  pages =        "66--73",
  year =         "1989",
  ISSN =         "0720-4442, 0941-777x , 0943-5409",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1989:FSAb
author: H. Volzke
journal: j-MC
volume: 2
pages: 65--71
year: 1989
ISSN: 0720-4442, 0941-777x , 0943-5409 OR 07204442, 0941777x , 09435409
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 5: Ein- und Ausgabefunktionen toenglish Floating-point Arithmetic and its IEEE Specification. Part 5: Input and Output Functions endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 5: Ein- und Ausgabefunktionen} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 5: Input and Output Functions} \endtoenglish

entry:
@Article{Voelzke:1989:FSAb,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 5: Ein- und
                 Ausgabefunktionen} \toenglish {Floating-point
                 Arithmetic and its IEEE Specification. Part 5: Input
                 and Output Functions} \endtoenglish",
  journal =      j-MC,
  volume =       "2",
  pages =        "65--71",
  year =         "1989",
  ISSN =         "0720-4442, 0941-777x , 0943-5409",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Vulchanov:1989:SCR
author: N. L. Vulchanov and M. M. Konstantinov
title: Safe calculation of the relative machine precision in floating-point computing environments
journal: j-C-R-ACAD-BULGARE-SCI
volume: 42
number: 2
pages: 45--48
year: 1989
CODEN: DBANAD
ISSN: 0366-8681 OR 03668681
MRclass: 65G99
MRnumber: 991 451
bibdate: Fri Dec 8 08:24:14 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:14 ???
fjournal: Comptes rendus de l'Academie bulgare des sciences
acknowledgement: ack-nhfb
rawauthor: N. L. Vulchanov and M. M. Konstantinov
rawtitle: Safe calculation of the relative machine precision in floating-point computing environments
entry:
@Article{Vulchanov:1989:SCR,
  author =       "N. L. Vulchanov and M. M. Konstantinov",
  title =        "Safe calculation of the relative machine precision in
                 floating-point computing environments",
  journal =      j-C-R-ACAD-BULGARE-SCI,
  volume =       "42",
  number =       "2",
  pages =        "45--48",
  year =         "1989",
  CODEN =        "DBANAD",
  ISSN =         "0366-8681",
  MRclass =      "65G99",
  MRnumber =     "991 451",
  bibdate =      "Fri Dec 8 08:24:14 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Comptes rendus de l'Acad{\'e}mie bulgare des
                 sciences",
}


bibtype: article
filename: fparith.bib
label: Wagner:1989:EDD
author: Neal R. Wagner and Paul Putter
title: Error detecting decimal digits
journal: j-CACM
volume: 32
number: 1
pages: 106--110
month: jan
monthnumber: 1
year: 1989
CODEN: CACMA2
DOI: https://doi.org/10.1145/63238.63246
ISSN: 0001-0782 (print), 1557-7317 (electronic) OR 00010782 (print), 15577317 (electronic)
ISSNL: 0001-0782 OR 00010782
bibdate: Thu May 30 09:41:10 MDT 1996
bibtimestamp: 1996.05.30 09:41:10 MDT
URL: http://www.acm.org/pubs/toc/Abstracts/0001-0782/63246.html
fjournal: Communications of the ACM
keywords: decimal floating-point arithmetic; reliability
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/cacm
rawauthor: Neal R. Wagner and Paul Putter
rawtitle: Error detecting decimal digits
bibsource:
ftp://ftp.ira.uka.de/pub/bibliography/Misc/IMMD_IV.bib; http://www.acm.org/pubs/toc/; https://www.math.utah.edu/pub/tex/bib/cacm1980.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We were recently engaged by a large mail-order house to act as consultants on their use of check digits for detecting errors in account numbers. Since we were not experts in coding theory, we looked in reference books such as Error Correcting Codes [7] and asked colleagues who were familiar with coding theory. Uniformly, the answer was: There is no field of order 10; the theory only works over a field. This article relates our experiences and presents several of the simple decimal-oriented error detection schemes that are available, but not widely known.

subject:
bf B.4.5: Hardware, INPUT/OUTPUT AND DATA COMMUNICATIONS, Reliability, Testing, and Fault-Tolerance, Error-checking. bf E.4: Data, CODING AND INFORMATION THEORY, Nonsecret encoding schemes.

rawabstract:
We were recently engaged by a large mail-order house to act as consultants on their use of check digits for detecting errors in account numbers. Since we were not experts in coding theory, we looked in reference books such as Error Correcting Codes [7] and asked colleagues who were familiar with coding theory. Uniformly, the answer was: There is no field of order 10; the theory only works over a field. This article relates our experiences and presents several of the simple decimal-oriented error detection schemes that are available, but not widely known.

entry:
@Article{Wagner:1989:EDD,
  author =       "Neal R. Wagner and Paul Putter",
  title =        "Error detecting decimal digits",
  journal =      j-CACM,
  volume =       "32",
  number =       "1",
  pages =        "106--110",
  month =        jan,
  year =         "1989",
  CODEN =        "CACMA2",
  DOI =          "https://doi.org/10.1145/63238.63246",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Thu May 30 09:41:10 MDT 1996",
  bibsource =    "ftp://ftp.ira.uka.de/pub/bibliography/Misc/IMMD_IV.bib;
                 http://www.acm.org/pubs/toc/;
                 https://www.math.utah.edu/pub/tex/bib/cacm1980.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/toc/Abstracts/0001-0782/63246.html",
  abstract =     "We were recently engaged by a large mail-order house
                 to act as consultants on their use of check digits for
                 detecting errors in account numbers. Since we were not
                 experts in coding theory, we looked in reference books
                 such as Error Correcting Codes [7] and asked colleagues
                 who were familiar with coding theory. Uniformly, the
                 answer was: There is no field of order 10; the theory
                 only works over a field. This article relates our
                 experiences and presents several of the simple
                 decimal-oriented error detection schemes that are
                 available, but not widely known.",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
  keywords =     "decimal floating-point arithmetic; reliability",
  review =       "ACM CR 9002-0109",
  subject =      "{\bf B.4.5}: Hardware, INPUT/OUTPUT AND DATA
                 COMMUNICATIONS, Reliability, Testing, and
                 Fault-Tolerance, Error-checking. {\bf E.4}: Data,
                 CODING AND INFORMATION THEORY, Nonsecret encoding
                 schemes.",
}


bibtype: article
filename: fparith.bib
label: Wang:1989:ADF
author: C. C. Wang
title: An algorithm to design finite field multipliers using a self-dual normal basis
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 10
pages: 1457--1460
month: oct
monthnumber: 10
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.35840
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:42 MDT 2011
bibtimestamp: 2011.07.08 19:00:42 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=35840
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: C. C. Wang
rawtitle: An algorithm to design finite field multipliers using a self-dual normal basis
entry:
@Article{Wang:1989:ADF,
  author =       "C. C. Wang",
  title =        "An algorithm to design finite field multipliers using
                 a self-dual normal basis",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "10",
  pages =        "1457--1460",
  month =        oct,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.35840",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=35840",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:1989:MBC
title: A 34-MFLOP 32-bit CMOS floating point processor
crossref: IEEE:1989:ISV
pages: 361--364
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Electron. Res and Service Organ., Hsing-Chu, Taiwan
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Pipeline processing
rawtitle: A 34-{MFLOP} 32-bit {CMOS} floating point processor
author:
Song-Tine Wang and Chi-Suan Wang and Morries Wang and Shyh-Rurong Wang and Jhy-Kun Wang and Ching-Lu Hon and Row-Ming Yang and Wei-Hsiung Chuang and Te-Tsoung Tsai and Ming-Yuan Jang and Gwo-Jeng Pun

abstract:
A 34-MFLOP 32-bit floating-point processor in 2- mu m CMOS technology is presented. In order to achieve the high speed of floating-point operation, the authors use such techniques as hierarchical design parallel circuits, and a three-stage pipeline that has been optimized with equal delay in each stage. It is shown that the CIC81232Y (multiplier) and CIC81233Y (arithmetic and logic circuit) are fully compatible with WTL1232 and WTL1233 in function, but the speeds are 1.7 times faster.

keywords:
32 Bit; 32-Bit floating-point processor; 34 MFLOPS; Arithmetic circuit; CIC81232Y; CIC81233Y; CMOS technology; Hierarchical design parallel circuits; Logic circuit; Multiplier; Three-stage pipeline

rawabstract:
A 34-MFLOP 32-bit floating-point processor in 2- mu m CMOS technology is presented. In order to achieve the high speed of floating-point operation, the authors use such techniques as hierarchical design parallel circuits, and a three-stage pipeline that has been optimized with equal delay in each stage. It is shown that the CIC81232Y (multiplier) and CIC81233Y (arithmetic and logic circuit) are fully compatible with WTL1232 and WTL1233 in function, but the speeds are 1.7 times faster.

rawauthor:
Song-Tine Wang and Chi-Suan Wang and Morries Wang and Shyh-Rurong Wang and Jhy-Kun Wang and Ching-Lu Hon and Row-Ming Yang and Wei-Hsiung Chuang and Te-Tsoung Tsai and Ming-Yuan Jang and Gwo-Jeng Pun

entry:
@InProceedings{Wang:1989:MBC,
  author =       "Song-Tine Wang and Chi-Suan Wang and Morries Wang and
                 Shyh-Rurong Wang and Jhy-Kun Wang and Ching-Lu Hon and
                 Row-Ming Yang and Wei-Hsiung Chuang and Te-Tsoung Tsai
                 and Ming-Yuan Jang and Gwo-Jeng Pun",
  title =        "A 34-{MFLOP} 32-bit {CMOS} floating point processor",
  crossref =     "IEEE:1989:ISV",
  pages =        "361--364",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 34-MFLOP 32-bit floating-point processor in 2- mu m
                 CMOS technology is presented. In order to achieve the
                 high speed of floating-point operation, the authors use
                 such techniques as hierarchical design parallel
                 circuits, and a three-stage pipeline that has been
                 optimized with equal delay in each stage. It is shown
                 that the CIC81232Y (multiplier) and CIC81233Y
                 (arithmetic and logic circuit) are fully compatible
                 with WTL1232 and WTL1233 in function, but the speeds
                 are 1.7 times faster.",
  acknowledgement = ack-nhfb,
  affiliation =  "Electron. Res and Service Organ., Hsing-Chu, Taiwan",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods)",
  keywords =     "32 Bit; 32-Bit floating-point processor; 34 MFLOPS;
                 Arithmetic circuit; CIC81232Y; CIC81233Y; CMOS
                 technology; Hierarchical design parallel circuits;
                 Logic circuit; Multiplier; Three-stage pipeline",
  numericalindex = "Word length 3.2E+01 bit; Computer speed 3.4E+07
                 FLOPS",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Pipeline processing",
}


bibtype: mastersthesis
filename: fparith.bib
label: Ward:1989:BFP
author: Kenneth L. Ward
title: A block floating point distributed arithmetic finite impulse response filter
type: Thesis (M.S.)
school: University of Florida
address: Gainesville, FL, USA
pages: 361--364
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Digital filters (Mathematics); Filters (Mathematics); Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Kenneth L. Ward
rawtitle: A block floating point distributed arithmetic finite impulse response filter
entry:
@MastersThesis{Ward:1989:BFP,
  author =       "Kenneth L. Ward",
  title =        "A block floating point distributed arithmetic finite
                 impulse response filter",
  type =         "Thesis ({M.S.})",
  school =       "University of Florida",
  address =      "Gainesville, FL, USA",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital filters (Mathematics); Filters (Mathematics);
                 Floating-point arithmetic.",
}


bibtype: article
filename: fparith.bib
label: Wichmann:1989:SPI
author: B. A. Wichmann
journal: j-SIGPLAN
volume: 24
number: 6
pages: 20--22
month: jun
monthnumber: 6
year: 1989
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:15:40 MST 2003
bibsource: Compendex database; http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:15:40 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliationaddress: Teddington, Engl
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
journalabr: SIGPLAN Not
rawauthor: B. A. Wichmann
title:
Scientific processing in ISO-Pascal: a proposal to get the benefits of mixed precision floating-point

abstract:
Although Pascal is a very popular language for teaching and for use on microprocessors, it has not been very successful for scientific calculations. Apart from the pre-eminence of FORTRAN in this application area, several technical defects in Pascal have inhibited its use. One defect has been the problem in Pascal as defined by Jensen and Wirth of the inability to handle arrays of varying size as parameters to procedures. The level 1 option in ISO-Pascal addressed this defect by means of conformant arrays, albeit in a somewhat inelegant fashion. Array handling in ISO-Pascal can now be regarded as adequate since level 1 validated compilers are available for the majority of widely available machines. This note addresses another defect of Pascal, that no facility is provided to handle floating point types of more than one precision.

keywords:
algorithms; Computer Programming Languages; design; Floating Point Computation; iso-pascal; languages; pascal; Scientific Computing; standardization; Standards

subject:
D.2.1 Software, SOFTWARE ENGINEERING, Requirements/Specifications D.3.2 Software, PROGRAMMING LANGUAGES, Language Classifications, Pascal E.1 Data, DATA STRUCTURES, Arrays

rawabstract:
Although Pascal is a very popular language for teaching and for use on microprocessors, it has not been very successful for scientific calculations. Apart from the pre-eminence of FORTRAN in this application area, several technical defects in Pascal have inhibited its use. One defect has been the problem in Pascal as defined by Jensen and Wirth of the inability to handle arrays of varying size as parameters to procedures. The level 1 option in ISO-Pascal addressed this defect by means of conformant arrays, albeit in a somewhat inelegant fashion. Array handling in ISO-Pascal can now be regarded as adequate since level 1 validated compilers are available for the majority of widely available machines. This note addresses another defect of Pascal, that no facility is provided to handle floating point types of more than one precision.

rawtitle:
Scientific processing in {ISO-Pascal}: a proposal to get the benefits of mixed precision floating-point

entry:
@Article{Wichmann:1989:SPI,
  author =       "B. A. Wichmann",
  title =        "Scientific processing in {ISO-Pascal}: a proposal to
                 get the benefits of mixed precision floating-point",
  journal =      j-SIGPLAN,
  volume =       "24",
  number =       "6",
  pages =        "20--22",
  month =        jun,
  year =         "1989",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:15:40 MST 2003",
  bibsource =    "Compendex database; http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Although Pascal is a very popular language for
                 teaching and for use on microprocessors, it has not
                 been very successful for scientific calculations. Apart
                 from the pre-eminence of FORTRAN in this application
                 area, several technical defects in Pascal have
                 inhibited its use. One defect has been the problem in
                 Pascal as defined by Jensen and Wirth of the inability
                 to handle arrays of varying size as parameters to
                 procedures. The level 1 option in ISO-Pascal addressed
                 this defect by means of conformant arrays, albeit in a
                 somewhat inelegant fashion. Array handling in
                 ISO-Pascal can now be regarded as adequate since level
                 1 validated compilers are available for the majority of
                 widely available machines. This note addresses another
                 defect of Pascal, that no facility is provided to
                 handle floating point types of more than one
                 precision.",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Teddington, Engl",
  classification = "723; 902",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  journalabr =   "SIGPLAN Not",
  keywords =     "algorithms; Computer Programming Languages; design;
                 Floating Point Computation; iso-pascal; languages;
                 pascal; Scientific Computing; standardization;
                 Standards",
  subject =      "D.2.1 Software, SOFTWARE ENGINEERING,
                 Requirements/Specifications \\ D.3.2 Software,
                 PROGRAMMING LANGUAGES, Language Classifications, Pascal
                 \\ E.1 Data, DATA STRUCTURES, Arrays",
}


bibtype: article
filename: fparith.bib
label: Wichmann:1989:TFS
author: B. A. Wichmann
title: Towards a formal specification of floating point
journal: j-COMP-J
volume: 32
number: 5
pages: 432--436
month: oct
monthnumber: 10
year: 1989
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
MRclass: 65G99 (65Y10)
MRnumber: 91b:65055
bibdate: Wed Dec 13 18:44:32 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.13 18:44:32 ???
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Department of Trade and Ind., NPL, Teddington, UK
corpsource: Department of Trade and Ind., NPL, Teddington, UK
journalURL: http://comjnl.oxfordjournals.org/
thesaurus: Digital arithmetic; Formal specification
treatment: P Practical
rawauthor: B. A. Wichmann
rawtitle: Towards a formal specification of floating point
abstract:
Although the concept of floating point is well understood, a formal mathematical treatment appears to be new. The paper presents a formal definition of floating point using the Vienna Development Method (VDM). The relationship between this definition and the informal definition in the Ada Standard and the work of W. S. Brown (1981) is discussed.

keywords:
digital arithmetic; Floating point; floating point; Formal specification; formal specification; Method; Vienna Development; Vienna Development Method

rawabstract:
Although the concept of floating point is well understood, a formal mathematical treatment appears to be new. The paper presents a formal definition of floating point using the Vienna Development Method (VDM). The relationship between this definition and the informal definition in the Ada Standard and the work of W. S. Brown (1981) is discussed.

entry:
@Article{Wichmann:1989:TFS,
  author =       "B. A. Wichmann",
  title =        "Towards a formal specification of floating point",
  journal =      j-COMP-J,
  volume =       "32",
  number =       "5",
  pages =        "432--436",
  month =        oct,
  year =         "1989",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  MRclass =      "65G99 (65Y10)",
  MRnumber =     "91b:65055",
  bibdate =      "Wed Dec 13 18:44:32 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Although the concept of floating point is well
                 understood, a formal mathematical treatment appears to
                 be new. The paper presents a formal definition of
                 floating point using the Vienna Development Method
                 (VDM). The relationship between this definition and the
                 informal definition in the Ada Standard and the work of
                 W. S. Brown (1981) is discussed.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Trade and Ind., NPL, Teddington, UK",
  classification = "C5230 (Digital arithmetic methods); C6110B (Software
                 engineering techniques)",
  corpsource =   "Department of Trade and Ind., NPL, Teddington, UK",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "digital arithmetic; Floating point; floating point;
                 Formal specification; formal specification; Method;
                 Vienna Development; Vienna Development Method",
  pubcountry =   "UK",
  thesaurus =    "Digital arithmetic; Formal specification",
  treatment =    "P Practical",
}


bibtype: mastersthesis
filename: fparith.bib
label: Wittman:1989:SCU
author: Susan Jean Wittman
title: Servo compensation using a floating point digital signal processor
type: Thesis (M.S.)
school: Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics
address: Cambridge, MA, USA
pages: 60
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
note: Supervised by James K. Roberge
acknowledgement: ack-nhfb
rawauthor: Susan Jean Wittman
rawnote: Supervised by James K. Roberge
rawtitle: Servo compensation using a floating point digital signal processor
entry:
@MastersThesis{Wittman:1989:SCU,
  author =       "Susan Jean Wittman",
  title =        "Servo compensation using a floating point digital
                 signal processor",
  type =         "Thesis ({M.S.})",
  school =       "Massachusetts Institute of Technology, Dept. of
                 Aeronautics and Astronautics",
  address =      "Cambridge, MA, USA",
  pages =        "60",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Supervised by James K. Roberge",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Zeng:1989:RNP
author: B. Zeng and Y. Neuvo
booktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
title: Roundoff noise properties of lattice filters employing floating-point arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 233--237
year: 1989
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: B. Zeng and Y. Neuvo
rawbooktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
rawtitle: Roundoff noise properties of lattice filters employing floating-point arithmetic
entry:
@InProceedings{Zeng:1989:RNP,
  author =       "B. Zeng and Y. Neuvo",
  booktitle =    "European Conference on Circuit Theory and Design, 5--8
                 Sep 1989",
  title =        "Roundoff noise properties of lattice filters employing
                 floating-point arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "233--237",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The roundoff noise properties of general lattice
                 filters are studied for floating-point implementations
                 using the concept of dummy multipliers. The main
                 efforts are devoted to the Gray-Markel recursive
                 structures. It is shown that the roundoff noise
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Zorpette:1989:PGD
author: Glenn Zorpette
title: Parkinson's gun director
journal: j-IEEE-SPECTRUM
volume: 26
number: 4
pages: 43--43
month: apr
monthnumber: 4
year: 1989
CODEN: IEESAM
DOI: https://doi.org/10.1109/6.24154
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Mon Jan 20 06:41:24 2020
bibtimestamp: 2020.01.20 06:41:24 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: Glenn Zorpette
rawtitle: {Parkinson}'s gun director
keywords:
antiaircraft guns; Arithmetic; Automatic control; Cities and towns; controllers; Crystallization; electromechanical system; gun director; Guns; Laboratories; M-9; magnetic clutches; operational amplifiers; Operational amplifiers; position control; potentiometer; Psychology; Springs; Telephony; weapons

entry:
@Article{Zorpette:1989:PGD,
  author =       "Glenn Zorpette",
  title =        "{Parkinson}'s gun director",
  journal =      j-IEEE-SPECTRUM,
  volume =       "26",
  number =       "4",
  pages =        "43--43",
  month =        apr,
  year =         "1989",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/6.24154",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Mon Jan 20 06:41:24 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum1980.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "antiaircraft guns; Arithmetic; Automatic control;
                 Cities and towns; controllers; Crystallization;
                 electromechanical system; gun director; Guns;
                 Laboratories; M-9; magnetic clutches; operational
                 amplifiers; Operational amplifiers; position control;
                 potentiometer; Psychology; Springs; Telephony;
                 weapons",
}


bibtype: article
filename: fparith.bib
label: Alsup:1990:MFA
author: M. Alsup
title: Motorola's 88000 Family Architecture
journal: j-IEEE-MICRO
volume: 10
number: 3
pages: 48--66
month: may
monthnumber: 5
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.56325
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Wed Sep 7 22:32:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:42 ???
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: M. Alsup
rawtitle: {Motorola}'s 88000 Family Architecture
entry:
@Article{Alsup:1990:MFA,
  author =       "M. Alsup",
  title =        "{Motorola}'s 88000 Family Architecture",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "3",
  pages =        "48--66",
  month =        may # "\slash " # jun,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.56325",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Wed Sep 7 22:32:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1990:MUF
author: Anonymous
title: Motorola unveils 96002 floating point processor
journal: Integrated circuits international
pages: 3--??
month: jul
monthnumber: 7
year: 1990
ISSN: 0263-6522 OR 02636522
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {Motorola} unveils 96002 floating point processor
entry:
@Article{Anonymous:1990:MUF,
  author =       "Anonymous",
  title =        "{Motorola} unveils 96002 floating point processor",
  journal =      "Integrated circuits international",
  pages =        "3--??",
  month =        jul,
  year =         "1990",
  ISSN =         "0263-6522",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: mastersthesis
filename: fparith.bib
label: Ansari:1990:MBF
author: Ahmad Ansari
title: A $ 3 times 3 $ multipurpose bus-connected floating-point array processor
type: Thesis (M.S.)
school: University of Florida
address: Gainesville, FL, USA
pages: vi + 127
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Ahmad Ansari
rawtitle: A $ 3 \times 3 $ multipurpose bus-connected floating-point array processor
entry:
@MastersThesis{Ansari:1990:MBF,
  author =       "Ahmad Ansari",
  title =        "A $ 3 \times 3 $ multipurpose bus-connected
                 floating-point array processor",
  type =         "Thesis ({M.S.})",
  school =       "University of Florida",
  address =      "Gainesville, FL, USA",
  pages =        "vi + 127",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Arnold:1990:RLA
author: M. G. Arnold and T. A. Bailey and J. R. Cowles and J. J. Cupal
title: Redundant logarithmic arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 8
pages: 1077--1086
month: aug
monthnumber: 8
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57046
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:03 MDT 2011
bibtimestamp: 2011.07.07 14:20:03 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57046
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Wyoming University, Laramie, WY, USA
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
thesaurus: Digital arithmetic; Number theory; Redundancy; Table lookup
rawauthor: M. G. Arnold and T. A. Bailey and J. R. Cowles and J. J. Cupal
rawtitle: Redundant logarithmic arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

abstract:
A number system that offers advantages in some situations over conventional floating point and sign/logarithmic number systems is described. Redundant logarithmic arithmetic, like conventional logarithmic arithmetic, relies on table lookups to make the arithmetic unit simpler than an equivalent floating point unit. The cost of 32 bit subtraction in a redundant logarithmic number system is lower than previously published logarithmic subtraction methods. The total memory requirement for a 29-bit redundant logarithmic unit is 16 K words compared to 22 K words by the best previously published conventional sign logarithm unit, assuming similar addition techniques are employed. A redundant logarithmic number system can be implemented with online arithmetic, which would be impractical for a conventional sign logarithm number system. The disadvantages of redundant arithmetic are typical of redundant number systems. First, the redundancy doubles the storage requirements for data values. Second, the representation can become ill-conditioned, especially as a result of iterated multiplications. Third, division and square root operations are more difficult to implement in redundant logarithmic arithmetic.

keywords:
29-Bit redundant logarithmic unit; 32 Bit subtraction; Arithmetic unit; Data values; Division; Ill-conditioned; Iterated multiplications; Memory requirement; Online arithmetic; Redundant logarithmic arithmetic; Redundant logarithmic number system; Square root; Storage requirements; Table lookups

rawabstract:
A number system that offers advantages in some situations over conventional floating point and sign/logarithmic number systems is described. Redundant logarithmic arithmetic, like conventional logarithmic arithmetic, relies on table lookups to make the arithmetic unit simpler than an equivalent floating point unit. The cost of 32 bit subtraction in a redundant logarithmic number system is lower than previously published logarithmic subtraction methods. The total memory requirement for a 29-bit redundant logarithmic unit is 16 K words compared to 22 K words by the best previously published conventional sign logarithm unit, assuming similar addition techniques are employed. A redundant logarithmic number system can be implemented with online arithmetic, which would be impractical for a conventional sign logarithm number system. The disadvantages of redundant arithmetic are typical of redundant number systems. First, the redundancy doubles the storage requirements for data values. Second, the representation can become ill-conditioned, especially as a result of iterated multiplications. Third, division and square root operations are more difficult to implement in redundant logarithmic arithmetic.

entry:
@Article{Arnold:1990:RLA,
  author =       "M. G. Arnold and T. A. Bailey and J. R. Cowles and J.
                 J. Cupal",
  title =        "Redundant logarithmic arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "8",
  pages =        "1077--1086",
  month =        aug,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57046",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:03 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57046",
  abstract =     "A number system that offers advantages in some
                 situations over conventional floating point and
                 sign/logarithmic number systems is described. Redundant
                 logarithmic arithmetic, like conventional logarithmic
                 arithmetic, relies on table lookups to make the
                 arithmetic unit simpler than an equivalent floating
                 point unit. The cost of 32 bit subtraction in a
                 redundant logarithmic number system is lower than
                 previously published logarithmic subtraction methods.
                 The total memory requirement for a 29-bit redundant
                 logarithmic unit is 16 K words compared to 22 K words
                 by the best previously published conventional sign
                 logarithm unit, assuming similar addition techniques
                 are employed. A redundant logarithmic number system can
                 be implemented with online arithmetic, which would be
                 impractical for a conventional sign logarithm number
                 system. The disadvantages of redundant arithmetic are
                 typical of redundant number systems. First, the
                 redundancy doubles the storage requirements for data
                 values. Second, the representation can become
                 ill-conditioned, especially as a result of iterated
                 multiplications. Third, division and square root
                 operations are more difficult to implement in redundant
                 logarithmic arithmetic.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Wyoming University,
                 Laramie, WY, USA",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C1160 (Combinatorial mathematics); C1210B
                 (Reliability theory); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "29-Bit redundant logarithmic unit; 32 Bit subtraction;
                 Arithmetic unit; Data values; Division;
                 Ill-conditioned; Iterated multiplications; Memory
                 requirement; Online arithmetic; Redundant logarithmic
                 arithmetic; Redundant logarithmic number system; Square
                 root; Storage requirements; Table lookups",
  thesaurus =    "Digital arithmetic; Number theory; Redundancy; Table
                 lookup",
}


bibtype: article
filename: fparith.bib
label: Aspray:1990:BBS
author: William Aspray
title: Back to Basics: The Stored Program Concept
journal: j-IEEE-SPECTRUM
volume: 27
number: 9
pages: 51--51
month: sep
monthnumber: 9
year: 1990
CODEN: IEESAM
DOI: https://doi.org/10.1109/6.58457
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Wed Jan 15 12:40:28 2020
bibtimestamp: 2020.01.15 12:40:28 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: William Aspray
rawtitle: Back to Basics: The Stored Program Concept
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/v/von-neumann-john.bib; https://www.math.utah.edu/pub/tex/bib/annhistcomput.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeespectrum1990.bib

abstract:
The history and early development of the stored program concept are briefly described. This refers to the ability of a calculating machine to store its instructions in its internal memory and process them in its arithmetic unit, so that in the course of a computation they may be not just executed but also modified at electronic speeds. John von Neumann, a faculty member of the Institute for Advanced Study in Princeton, NJ, participated in the discussions in which the idea was elaborated, wrote the first report of the concept, placed it in a theoretical context, and built his own computer, which was the early model for a number of others, including the important commercially manufactured IBM 701. J. Presper Eckert and John Mauchly perhaps first conceived of the stored program concept and developed most of the plans for implementing it in the Edvac, and later incorporated it in the Univac and other computers produced by their company. Several British computer scientists, notably Maurice Wilkes, were the first to implement the idea in machines initially designed to embody this feature.

keywords:
arithmetic unit; calculating machine; Computer aided instruction; Computer aided manufacturing; Computer architecture; Context modeling; Digital arithmetic; file organisation; history; History; internal memory; Laboratories; Military computing; Prototypes; storage allocation; stored program concept; Virtual manufacturing

rawabstract:
The history and early development of the stored program concept are briefly described. This refers to the ability of a calculating machine to store its instructions in its internal memory and process them in its arithmetic unit, so that in the course of a computation they may be not just executed but also modified at electronic speeds. John von Neumann, a faculty member of the Institute for Advanced Study in Princeton, NJ, participated in the discussions in which the idea was elaborated, wrote the first report of the concept, placed it in a theoretical context, and built his own computer, which was the early model for a number of others, including the important commercially manufactured IBM 701. J. Presper Eckert and John Mauchly perhaps first conceived of the stored program concept and developed most of the plans for implementing it in the Edvac, and later incorporated it in the Univac and other computers produced by their company. Several British computer scientists, notably Maurice Wilkes, were the first to implement the idea in machines initially designed to embody this feature.

entry:
@Article{Aspray:1990:BBS,
  author =       "William Aspray",
  title =        "Back to Basics: The Stored Program Concept",
  journal =      j-IEEE-SPECTRUM,
  volume =       "27",
  number =       "9",
  pages =        "51--51",
  month =        sep,
  year =         "1990",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/6.58457",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Wed Jan 15 12:40:28 2020",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/v/von-neumann-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/annhistcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum1990.bib",
  abstract =     "The history and early development of the stored
                 program concept are briefly described. This refers to
                 the ability of a calculating machine to store its
                 instructions in its internal memory and process them in
                 its arithmetic unit, so that in the course of a
                 computation they may be not just executed but also
                 modified at electronic speeds. John von Neumann, a
                 faculty member of the Institute for Advanced Study in
                 Princeton, NJ, participated in the discussions in which
                 the idea was elaborated, wrote the first report of the
                 concept, placed it in a theoretical context, and built
                 his own computer, which was the early model for a
                 number of others, including the important commercially
                 manufactured IBM 701. J. Presper Eckert and John
                 Mauchly perhaps first conceived of the stored program
                 concept and developed most of the plans for
                 implementing it in the Edvac, and later incorporated it
                 in the Univac and other computers produced by their
                 company. Several British computer scientists, notably
                 Maurice Wilkes, were the first to implement the idea in
                 machines initially designed to embody this feature.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "arithmetic unit; calculating machine; Computer aided
                 instruction; Computer aided manufacturing; Computer
                 architecture; Context modeling; Digital arithmetic;
                 file organisation; history; History; internal memory;
                 Laboratories; Military computing; Prototypes; storage
                 allocation; stored program concept; Virtual
                 manufacturing",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajwa:1990:FFP
author: A. Bajwa and R. Steck
title: A fast floating point unit in the i960 general-purpose embedded processor family
crossref: Wescon:1990:WCR
pages: 218--222
year: 1990
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Intel Corp., Hillsboro, OR, USA
thesaurus: Computer architecture; Digital arithmetic; Microprocessor chips; Reduced instruction set computing
rawauthor: A. Bajwa and R. Steck
rawtitle: A fast floating point unit in the i960 general-purpose embedded processor family
abstract:
Fast, cheap floating point arithmetic is required in many embedded processor applications. This paper describes a next-generation floating point unit designed as an integrated functional unit on Intel's i960 family of 32-bit embedded RISC processors. High performance is achieved by utilizing two separate, concurrent floating point execution units with wide datapaths, both internally and to general-purpose registers. Hardware system cost is reduced by integrating the FPU on the main processor while software development cost is minimized by using the i960 Numerics Architecture supported by standard i960 family development tools.

keywords:
32 Bit; 32-Bit embedded RISC processors; Concurrent floating point execution units; Embedded processor applications; Fast floating point unit; Floating point arithmetic; FPU; General-purpose embedded processor family; General-purpose registers; I960; I960 family; I960 Numerics Architecture; Integrated functional unit; Intel; Wide datapaths

rawabstract:
Fast, cheap floating point arithmetic is required in many embedded processor applications. This paper describes a next-generation floating point unit designed as an integrated functional unit on Intel's i960 family of 32-bit embedded RISC processors. High performance is achieved by utilizing two separate, concurrent floating point execution units with wide datapaths, both internally and to general-purpose registers. Hardware system cost is reduced by integrating the FPU on the main processor while software development cost is minimized by using the i960 Numerics Architecture supported by standard i960 family development tools.

entry:
@InProceedings{Bajwa:1990:FFP,
  author =       "A. Bajwa and R. Steck",
  title =        "A fast floating point unit in the i960 general-purpose
                 embedded processor family",
  crossref =     "Wescon:1990:WCR",
  pages =        "218--222",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Fast, cheap floating point arithmetic is required in
                 many embedded processor applications. This paper
                 describes a next-generation floating point unit
                 designed as an integrated functional unit on Intel's
                 i960 family of 32-bit embedded RISC processors. High
                 performance is achieved by utilizing two separate,
                 concurrent floating point execution units with wide
                 datapaths, both internally and to general-purpose
                 registers. Hardware system cost is reduced by
                 integrating the FPU on the main processor while
                 software development cost is minimized by using the
                 i960 Numerics Architecture supported by standard i960
                 family development tools.",
  acknowledgement = ack-nhfb,
  affiliation =  "Intel Corp., Hillsboro, OR, USA",
  availability = "Western Periodicals Co., 13000 Rayner Street, North
                 Hollywood, CA 91605, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C5230 (Digital arithmetic methods)",
  keywords =     "32 Bit; 32-Bit embedded RISC processors; Concurrent
                 floating point execution units; Embedded processor
                 applications; Fast floating point unit; Floating point
                 arithmetic; FPU; General-purpose embedded processor
                 family; General-purpose registers; I960; I960 family;
                 I960 Numerics Architecture; Integrated functional unit;
                 Intel; Wide datapaths",
  numericalindex = "Word length 3.2E+01 bit",
  thesaurus =    "Computer architecture; Digital arithmetic;
                 Microprocessor chips; Reduced instruction set
                 computing",
}


bibtype: techreport
filename: fparith.bib
label: Barlow:1990:EAU
author: Jesse Louis Barlow and Richard J. Zaccone
title: Error analysis in unnormalized floating point arithmetic
type: Technical report
number: CS-90-23
institution: Pennsylvania State University, Department of Computer Science
address: University Park, PA, USA
pages: 9
month: apr
monthnumber: 4
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Computer arithmetic.; Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Jesse Louis Barlow and Richard J. Zaccone
rawtitle: Error analysis in unnormalized floating point arithmetic
note:
Supported by the Air Force Office of Scientific Research. Supported by the National Science Foundation. Supported by the Office of Naval Research.

abstract:
The need to construct architectures in VLSI has focused attention on unnormalized floating point arithmetic. Certain unnormalized arithmetics allow one to `pipe on digits,' thus producing significant speed up in computation and making the input problems of special purpose devices such as systolic arrays easier to solve. We consider the error analysis implications of using unnormalized arithmetic in numerical algorithms. We also give specifications for its implementation. Our discussion centers on the example of Gaussian elimination. We show that the use of unnormalized arithmetic requires changes in the analysis of this algorithm. We will show that only for certain classes of matrices that include diagonally dominant matrices (either row or column), Gaussian elimination is as stable in unnormalized arithmetic as in normalized arithmetic. However, if the diagonal elements of the upper triangular matrix are post normalized, then Gaussian elimination is as stable in unnormalized arithmetic as in normalized arithmetic for all matrices.

rawabstract:
The need to construct architectures in VLSI has focused attention on unnormalized floating point arithmetic. Certain unnormalized arithmetics allow one to `pipe on digits,' thus producing significant speed up in computation and making the input problems of special purpose devices such as systolic arrays easier to solve. We consider the error analysis implications of using unnormalized arithmetic in numerical algorithms. We also give specifications for its implementation. Our discussion centers on the example of Gaussian elimination. We show that the use of unnormalized arithmetic requires changes in the analysis of this algorithm. We will show that only for certain classes of matrices that include diagonally dominant matrices (either row or column), Gaussian elimination is as stable in unnormalized arithmetic as in normalized arithmetic. However, if the diagonal elements of the upper triangular matrix are post normalized, then Gaussian elimination is as stable in unnormalized arithmetic as in normalized arithmetic for all matrices.

rawnote:
Supported by the Air Force Office of Scientific Research. Supported by the National Science Foundation. Supported by the Office of Naval Research.

entry:
@TechReport{Barlow:1990:EAU,
  author =       "Jesse Louis Barlow and Richard J. Zaccone",
  title =        "Error analysis in unnormalized floating point
                 arithmetic",
  type =         "Technical report",
  number =       "CS-90-23",
  institution =  "Pennsylvania State University, Department of Computer
                 Science",
  address =      "University Park, PA, USA",
  pages =        "9",
  month =        apr,
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Supported by the Air Force Office of Scientific
                 Research. Supported by the National Science Foundation.
                 Supported by the Office of Naval Research.",
  abstract =     "The need to construct architectures in VLSI has
                 focused attention on unnormalized floating point
                 arithmetic. Certain unnormalized arithmetics allow one
                 to `pipe on digits,' thus producing significant speed
                 up in computation and making the input problems of
                 special purpose devices such as systolic arrays easier
                 to solve. We consider the error analysis implications
                 of using unnormalized arithmetic in numerical
                 algorithms. We also give specifications for its
                 implementation. Our discussion centers on the example
                 of Gaussian elimination. We show that the use of
                 unnormalized arithmetic requires changes in the
                 analysis of this algorithm. We will show that only for
                 certain classes of matrices that include diagonally
                 dominant matrices (either row or column), Gaussian
                 elimination is as stable in unnormalized arithmetic as
                 in normalized arithmetic. However, if the diagonal
                 elements of the upper triangular matrix are post
                 normalized, then Gaussian elimination is as stable in
                 unnormalized arithmetic as in normalized arithmetic for
                 all matrices.",
  acknowledgement = ack-nhfb,
  keywords =     "Computer arithmetic.; Floating-point arithmetic.",
}


bibtype: mastersthesis
filename: fparith.bib
label: Bhargava:1990:DFP
author: Ish Kumar Bhargava
title: Design of a floating point data acquisition system and a development system for the NC 4016
type: Electrical Engineering Thesis (M.S.)
school: University of Missouri--Rolla
address: Rolla, MO, USA
pages: ix + 107
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Ish Kumar Bhargava
rawtitle: Design of a floating point data acquisition system and a development system for the {NC} 4016
entry:
@MastersThesis{Bhargava:1990:DFP,
  author =       "Ish Kumar Bhargava",
  title =        "Design of a floating point data acquisition system and
                 a development system for the {NC} 4016",
  type =         "Electrical Engineering Thesis ({M.S.})",
  school =       "University of Missouri--Rolla",
  address =      "Rolla, MO, USA",
  pages =        "ix + 107",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Birman:1990:DWS
title: Developing the WTL3170 / 3171 Sparc Floating-Point Coprocessors
journal: j-IEEE-MICRO
volume: 10
number: 1
pages: 55--64
month: jan
monthnumber: 1
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.46769
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawtitle: Developing the {WTL3170\slash 3171 Sparc} Floating-Point Coprocessors
author:
Mark Birman and Allen Samuels and George Chu and Chuk Ting and Larry Hu and John McLeod and John Barnes

abstract:
Contending with dual floating-point interfaces at both 25 and 40 MHz posed an extraordinary challenge in coprocessor development.

rawabstract:
Contending with dual floating-point interfaces at both 25 and 40 MHz posed an extraordinary challenge in coprocessor development.

rawauthor:
Mark Birman and Allen Samuels and George Chu and Chuk Ting and Larry Hu and John McLeod and John Barnes

entry:
@Article{Birman:1990:DWS,
  author =       "Mark Birman and Allen Samuels and George Chu and Chuk
                 Ting and Larry Hu and John McLeod and John Barnes",
  title =        "Developing the {WTL3170\slash 3171 Sparc}
                 Floating-Point Coprocessors",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "1",
  pages =        "55--64",
  month =        jan # "\slash " # feb,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.46769",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Contending with dual floating-point interfaces at both
                 25 and 40 MHz posed an extraordinary challenge in
                 coprocessor development.",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  summary =      "The development of the first two members in a family
                 of scalable-processor-architecture (Sparc)-compatible
                 parts is described. With varying frequency and latency
                 performance, the chips work with the first two integer
                 unit (IU) implementations from \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Blevins:1990:BHI
author: D. W. Blevins and E. W. Davis and R. A. Heaton and J. H. Feif
title: BLITZEN: a Highly Integrated Massively Parallel Machine
journal: j-J-PAR-DIST-COMP
volume: 8
number: 2
pages: 150--160
month: feb
monthnumber: 2
year: 1990
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 17:13:17 MDT 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 17:13:17 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
corpsource: Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
journalURL: http://www.sciencedirect.com/science/journal/07437315
treatment: P Practical
rawauthor: D. W. Blevins and E. W. Davis and R. A. Heaton and J. H. Feif
rawtitle: {BLITZEN}: a Highly Integrated Massively Parallel Machine
keywords:
1.25 micron; 20 MHz; architecture; BLITZEN; CMOS design rules; CMOS integrated circuits; computer architecture; global; highly integrated massively parallel machine; IEEE standard 32-bit floating point; local control features; memory address; microprocessor chips; multiplication; parallel processing; static RAM; VLSI

entry:
@Article{Blevins:1990:BHI,
  author =       "D. W. Blevins and E. W. Davis and R. A. Heaton and J.
                 H. Feif",
  title =        "{BLITZEN}: a Highly Integrated Massively Parallel
                 Machine",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "8",
  number =       "2",
  pages =        "150--160",
  month =        feb,
  year =         "1990",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 17:13:17 MDT 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5440
                 (Multiprocessor systems and techniques)",
  corpsource =   "Microelectron. Center of North Carolina, Research
                 Triangle Park, NC, USA",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  keywords =     "1.25 micron; 20 MHz; architecture; BLITZEN; CMOS
                 design rules; CMOS integrated circuits; computer
                 architecture; global; highly integrated massively
                 parallel machine; IEEE standard 32-bit floating point;
                 local control features; memory address; microprocessor
                 chips; multiplication; parallel processing; static RAM;
                 VLSI",
  treatment =    "P Practical",
}


bibtype: inbook
filename: fparith.bib
label: Branham:1990:PFP
author: Richard L. Branham
booktitle: Scientific Data Analysis: An Introduction to Overdetermined Systems
title: Properties of Floating-Point Numbers
publisher: pub-SV
address: pub-SV:adr
pages: 1--19
year: 1990
DOI: https://doi.org/10.1007/978-1-4612-3362-6_1
ISBN: 1-4612-3362-3 (e-book), 1-4612-7981-X OR 1461233623 (ebook), 146127981X
ISBN13: 978-1-4612-3362-6 (e-book), 978-1-4612-7981-5 OR 9781461233626 (ebook), 9781461279815
LCCN: QA76.9.D35
bibdate: Sat Dec 31 11:59:38 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.12.31 11:59:38 ???
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
bookpages: x + 237 + 36
rawauthor: Richard L. Branham
rawbooktitle: Scientific Data Analysis: An Introduction to Overdetermined Systems
rawtitle: Properties of Floating-Point Numbers
remark:
This introductory chapter discusses floating-point arithmetic in VAX binary, IBM System / 360 hexadecimal, and Sharp pocket calculator decimal formats, but has no mention of IEEE 754 arithmetic. It discusses the failure in floating-point arithmetic of the associative, cancellation, and distributive laws of exact arithmetic. In the context of accurate floating-point summation, it describes Kahan's compensated summation algorithm, Linz' binary-subdivision summation algorithm, and Wolfe's cascaded accumulator algorithm, all implemented in Fortran code given in the chapter figures. It also treats the error in summation in rounded and truncated arithmetic, and mentions the importance of guard digits.

TOC:
Properties of Floating-Point Numbers Matrices, Norms, and Condition Numbers Sparse Matrices Introduction to Overdetermined Systems Linear Least Squares The L1 Method Nonlinear Methods The Singular Value Decomposition Index

rawTOC:
Properties of Floating-Point Numbers \\ Matrices, Norms, and Condition Numbers \\ Sparse Matrices \\ Introduction to Overdetermined Systems \\ Linear Least Squares \\ The L1 Method \\ Nonlinear Methods \\ The Singular Value Decomposition \\ Index

entry:
@InBook{Branham:1990:PFP,
  author =       "Richard L. Branham",
  booktitle =    "Scientific Data Analysis: An Introduction to
                 Overdetermined Systems",
  title =        "Properties of Floating-Point Numbers",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  bookpages =    "x + 237 + 36",
  pages =        "1--19",
  year =         "1990",
  DOI =          "https://doi.org/10.1007/978-1-4612-3362-6_1",
  ISBN =         "1-4612-3362-3 (e-book), 1-4612-7981-X",
  ISBN-13 =      "978-1-4612-3362-6 (e-book), 978-1-4612-7981-5",
  LCCN =         "QA76.9.D35",
  bibdate =      "Sat Dec 31 11:59:38 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
  remark =       "This introductory chapter discusses floating-point
                 arithmetic in VAX binary, IBM System\slash 360
                 hexadecimal, and Sharp pocket calculator decimal
                 formats, but has no mention of IEEE 754 arithmetic. It
                 discusses the failure in floating-point arithmetic of
                 the associative, cancellation, and distributive laws of
                 exact arithmetic. In the context of accurate
                 floating-point summation, it describes Kahan's
                 compensated summation algorithm, Linz'
                 binary-subdivision summation algorithm, and Wolfe's
                 cascaded accumulator algorithm, all implemented in
                 Fortran code given in the chapter figures. It also
                 treats the error in summation in rounded and truncated
                 arithmetic, and mentions the importance of guard
                 digits.",
  tableofcontents = "Properties of Floating-Point Numbers \\
                 Matrices, Norms, and Condition Numbers \\
                 Sparse Matrices \\
                 Introduction to Overdetermined Systems \\
                 Linear Least Squares \\
                 The L1 Method \\
                 Nonlinear Methods \\
                 The Singular Value Decomposition \\
                 Index",
}


bibtype: inproceedings
filename: fparith.bib
label: Buck:1990:PAN
author: P. D. Buck and S. L. Day and D. Gonzalez
title: Problems with Ada numeric routines
crossref: Anonymous:1990:PAN
pages: 195--204
year: 1990
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Nat. University, San Diego, CA, USA
thesaurus: Ada; Data structures; Digital arithmetic; Software portability; Symbol manipulation
rawauthor: P. D. Buck and S. L. Day and D. Gonzalez
rawtitle: Problems with {Ada} numeric routines
abstract:
Computer programmers believe that their systems will always perform as expected. Standardization of computer languages has been a major advance towards this goal. The Ada language was intended to further advance this goal by rigorously defining the language. In addition the language was intended to improve the portability of programs. The authors' experience shows that the definition of the Ada language does not ensure mathematical algorithms will function consistently across multiple hardware environments. The method used by the language designers to specify the floating point data types appears to be the cause of the problem.

keywords:
Ada; Floating point data types; Mathematical algorithms; Multiple hardware environments; Numeric routines; Portability

rawabstract:
Computer programmers believe that their systems will always perform as expected. Standardization of computer languages has been a major advance towards this goal. The Ada language was intended to further advance this goal by rigorously defining the language. In addition the language was intended to improve the portability of programs. The authors' experience shows that the definition of the Ada language does not ensure mathematical algorithms will function consistently across multiple hardware environments. The method used by the language designers to specify the floating point data types appears to be the cause of the problem.

entry:
@InProceedings{Buck:1990:PAN,
  author =       "P. D. Buck and S. L. Day and D. Gonzalez",
  title =        "Problems with {Ada} numeric routines",
  crossref =     "Anonymous:1990:PAN",
  pages =        "195--204",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Computer programmers believe that their systems will
                 always perform as expected. Standardization of computer
                 languages has been a major advance towards this goal.
                 The Ada language was intended to further advance this
                 goal by rigorously defining the language. In addition
                 the language was intended to improve the portability of
                 programs. The authors' experience shows that the
                 definition of the Ada language does not ensure
                 mathematical algorithms will function consistently
                 across multiple hardware environments. The method used
                 by the language designers to specify the floating point
                 data types appears to be the cause of the problem.",
  acknowledgement = ack-nhfb,
  affiliation =  "Nat. University, San Diego, CA, USA",
  classification = "C6120 (File organisation); C6130 (Data handling
                 techniques); C6140D (High level languages)",
  keywords =     "Ada; Floating point data types; Mathematical
                 algorithms; Multiple hardware environments; Numeric
                 routines; Portability",
  thesaurus =    "Ada; Data structures; Digital arithmetic; Software
                 portability; Symbol manipulation",
}


bibtype: article
filename: fparith.bib
label: Bursky:1990:FMC
author: D. Bursky
title: Floating-point math chip delivers 200 mflops peak
journal: j-ELECTRONIC-DESIGN
volume: 38
number: 4
pages: 51--52, 54, 55
month: feb
monthnumber: 2
year: 1990
CODEN: ELODAW
ISSN: 0013-4872 (print), 1944-9550 (electronic) OR 00134872 (print), 19449550 (electronic)
ISSNL: 0013-4872 OR 00134872
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: Electronic Design
acknowledgement: ack-nhfb
rawauthor: D. Bursky
rawtitle: Floating-point math chip delivers 200 mflops peak
abstract:
By exploiting its latest process improvements and a three-layer metal interconnection capability, Bipolar Integrated Technology has managed to boost floating-point throughput three- to five-fold over its previous-generation circuits. The new B3130, a single-chip double-precision floating-point processor with 64-bit data buses, can deliver up to 200 MFLOPS of peak throughput. With more than 55000 equivalent gates and multiple 64-bit data buses (plus eight parity bits on each bus), the chip is the highest-complexity ECL chip to be sold commercially. By employing a high degree of integration, the single chip packs a 64-bit ALU, a 54-bit parallel multiplier (for the mantissa), and a 64-bit divide/square root unit. The chip's architecture is optimized for vector processing, but it can also perform scalar calculations. In addition, the wide data buses and pipelining support eliminate the loading and unloading bottlenecks that frequently degrade chip performance.

keywords:
200 MFLOPS; 64 Bit; ALU; B3130; Bipolar Integrated Technology; Bipolar microprocessor; Divide/square root unit; Double-precision; ECL chip; Floating-point processor; Multiple data buses; Parallel multiplier; Pipelining support; Scalar calculations; Three-layer metal interconnection; Vector processing

thesaurus:
Bipolar integrated circuits; Digital arithmetic; Emitter-coupled logic; Microprocessor chips; Parallel architectures; Parallel machines; Pipeline processing; VLSI

rawabstract:
By exploiting its latest process improvements and a three-layer metal interconnection capability, Bipolar Integrated Technology has managed to boost floating-point throughput three- to five-fold over its previous-generation circuits. The new B3130, a single-chip double-precision floating-point processor with 64-bit data buses, can deliver up to 200 MFLOPS of peak throughput. With more than 55000 equivalent gates and multiple 64-bit data buses (plus eight parity bits on each bus), the chip is the highest-complexity ECL chip to be sold commercially. By employing a high degree of integration, the single chip packs a 64-bit ALU, a 54-bit parallel multiplier (for the mantissa), and a 64-bit divide/square root unit. The chip's architecture is optimized for vector processing, but it can also perform scalar calculations. In addition, the wide data buses and pipelining support eliminate the loading and unloading bottlenecks that frequently degrade chip performance.

entry:
@Article{Bursky:1990:FMC,
  author =       "D. Bursky",
  title =        "Floating-point math chip delivers 200 mflops peak",
  journal =      j-ELECTRONIC-DESIGN,
  volume =       "38",
  number =       "4",
  pages =        "51--52, 54, 55",
  month =        feb,
  year =         "1990",
  CODEN =        "ELODAW",
  ISSN =         "0013-4872 (print), 1944-9550 (electronic)",
  ISSN-L =       "0013-4872",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "By exploiting its latest process improvements and a
                 three-layer metal interconnection capability, Bipolar
                 Integrated Technology has managed to boost
                 floating-point throughput three- to five-fold over its
                 previous-generation circuits. The new B3130, a
                 single-chip double-precision floating-point processor
                 with 64-bit data buses, can deliver up to 200 MFLOPS of
                 peak throughput. With more than 55000 equivalent gates
                 and multiple 64-bit data buses (plus eight parity bits
                 on each bus), the chip is the highest-complexity ECL
                 chip to be sold commercially. By employing a high
                 degree of integration, the single chip packs a 64-bit
                 ALU, a 54-bit parallel multiplier (for the mantissa),
                 and a 64-bit divide/square root unit. The chip's
                 architecture is optimized for vector processing, but it
                 can also perform scalar calculations. In addition, the
                 wide data buses and pipelining support eliminate the
                 loading and unloading bottlenecks that frequently
                 degrade chip performance.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B2570B
                 (Bipolar integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  fjournal =     "Electronic Design",
  keywords =     "200 MFLOPS; 64 Bit; ALU; B3130; Bipolar Integrated
                 Technology; Bipolar microprocessor; Divide/square root
                 unit; Double-precision; ECL chip; Floating-point
                 processor; Multiple data buses; Parallel multiplier;
                 Pipelining support; Scalar calculations; Three-layer
                 metal interconnection; Vector processing",
  numericalindex = "Computer speed 2.0E+08 FLOPS; Word length 6.4E+01
                 bit",
  thesaurus =    "Bipolar integrated circuits; Digital arithmetic;
                 Emitter-coupled logic; Microprocessor chips; Parallel
                 architectures; Parallel machines; Pipeline processing;
                 VLSI",
}


bibtype: article
filename: fparith.bib
label: Carter:1990:RSD
author: T. M. Carter and J. E. Robertson
title: Radix-$ 16 $ signed-digit division
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 12
pages: 1424--1433
month: dec
monthnumber: 12
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.61063
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:05 MDT 2011
bibtimestamp: 2011.07.07 14:20:05 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=61063
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. M. Carter and J. E. Robertson
rawtitle: Radix-$ 16 $ signed-digit division
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

entry:
@Article{Carter:1990:RSD,
  author =       "T. M. Carter and J. E. Robertson",
  title =        "Radix-$ 16 $ signed-digit division",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "12",
  pages =        "1424--1433",
  month =        dec,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.61063",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:05 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=61063",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Carter:1990:STA
author: T. M. Carter and J. E. Robertson
title: The set theory of arithmetic decomposition
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 8
pages: 993--1005
month: aug
monthnumber: 8
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57037
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:03 MDT 2011
bibtimestamp: 2011.07.07 14:20:03 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57037
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. M. Carter and J. E. Robertson
rawtitle: The set theory of arithmetic decomposition
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

entry:
@Article{Carter:1990:STA,
  author =       "T. M. Carter and J. E. Robertson",
  title =        "The set theory of arithmetic decomposition",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "8",
  pages =        "993--1005",
  month =        aug,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57037",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:03 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57037",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:1990:DIH
author: J. T. Chen and W. K. Jenkins and I. A. Hein and W. D. O'Brien, Jr.
booktitle: IEEE International Symposium on Circuits and Systems, 1--3 May 1990
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2893--2896
year: 1990
DOI: https://doi.org/10.1109/ISCAS.1990.112615
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: J. T. Chen and W. K. Jenkins and I. A. Hein and W. D. {O'Brien, Jr.}
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 1--3 May 1990
title:
Design and implementation of a high speed residue number system correlator for ultrasonic time domain blood flow measurement

rawtitle:
Design and implementation of a high speed residue number system correlator for ultrasonic time domain blood flow measurement

entry:
@InProceedings{Chen:1990:DIH,
  author =       "J. T. Chen and W. K. Jenkins and I. A. Hein and W. D.
                 {O'Brien, Jr.}",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 1--3 May 1990",
  title =        "Design and implementation of a high speed residue
                 number system correlator for ultrasonic time domain
                 blood flow measurement",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2893--2896",
  year =         "1990",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1990.112615",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The design and operation of a high-speed residue
                 number system (RNS) digital correlator is presented for
                 implementing the correlation function in a real-time
                 ultrasonic blood flow measurement system. This
                 architecture allows for both high-speed \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chren:1990:NRN
author: W. A. Chren, Jr.
title: A new residue number system division algorithm
journal: j-COMPUT-MATH-APPL
volume: 19
number: 7
pages: 13--29
year: 1990
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 19:01:19 MST 2017
bibtimestamp: 2017.03.01 19:01:19 MST
URL: http://www.sciencedirect.com/science/article/pii/089812219090190U
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: W. A. {Chren, Jr.}
rawtitle: A new residue number system division algorithm
bibsource:
https://www.math.utah.edu/pub/tex/bib/computmathappl1990.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Chren:1990:NRN,
  author =       "W. A. {Chren, Jr.}",
  title =        "A new residue number system division algorithm",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "19",
  number =       "7",
  pages =        "13--29",
  month =        "????",
  year =         "1990",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 19:01:19 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl1990.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/089812219090190U",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Ciminiera:1990:HRS
author: L. Ciminiera and P. Montuschi
title: Higher radix square rooting
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 10
pages: 1220--1231
month: oct
monthnumber: 10
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.59853
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:04 MDT 2011
bibtimestamp: 2011.07.07 14:20:04 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=59853
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: L. Ciminiera and P. Montuschi
rawtitle: Higher radix square rooting
entry:
@Article{Ciminiera:1990:HRS,
  author =       "L. Ciminiera and P. Montuschi",
  title =        "Higher radix square rooting",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "10",
  pages =        "1220--1231",
  month =        oct,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.59853",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:04 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=59853",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "A general discussion on nonrestoring square root
                 algorithms is presented, showing bounds and constraints
                 delimiting the space of feasible algorithms, for all
                 the choices of radix, digit set and representation of
                 the partial remainder. Two classes of \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Clinger:1990:HRF
author: William D. Clinger
title: How to Read Floating Point Numbers Accurately
journal: j-SIGPLAN
volume: 25
number: 6
pages: 92--101
month: jun
monthnumber: 6
year: 1990
CODEN: SINODQ
DOI: https://doi.org/10.1145/93548.93557
ISBN: 0-89791-364-7 OR 0897913647
ISBN13: 978-0-89791-364-5 OR 9780897913645
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:15:53 MST 2003
bibtimestamp: 2003.12.14 09:15:53 MST
URL: http://www.acm.org:80/pubs/citations/proceedings/pldi/93542/p92-clinger/
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Oregon University, Eugene, OR, USA
annote: Published as part of the Proceedings of PLDI'90.
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
journalabr: SIGPLAN Not
thesaurus: Digital arithmetic; Mathematics computing; Number theory; Standards
rawauthor: William D. Clinger
rawtitle: How to Read Floating Point Numbers Accurately
bibsource:
Compendex database; ftp://garbo.uwasa.fi/pc/doc-soft/fpbiblio.txt; http://portal.acm.org/; http://www.acm.org/pubs/contents/proceedings/pldi/93542/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigplan1990.bib

note:
See also output algorithms in cite Knuth:1990:SPW,Steele:1990:HPF,Burger:1996:PFP,Abbott:1999:ASS,Steele:2004:RHP.

abstract:
Consider the problem of converting decimal scientific notation for a number into the best binary floating point approximation to that number, for some fixed precision. This problem cannot be solved using arithmetic of any fixed precision. Hence the IEEE Standard for Binary Floating-Point Arithmetic does not require the result of such a conversion to be the best approximation. This paper presents an efficient algorithm that always finds the best approximation. The algorithm uses a few extra bits of precision to compute an IEEE-conforming approximation while testing an intermediate result to determine whether the approximation could be other than the best. If the approximation might not be the best, then the best approximation is determined by a few simple operations on multiple-precision integers, where the precision is determined by the input. When using 64 bits of precision to compute IEEE double precision results, the algorithm avoids higher-precision arithmetic over 99% of the time.

keywords:
algorithms; Best binary floating point approximation; Computer Programming Languages; Computers, Digital --- Computational Methods; Decimal scientific notation; Design; Efficient algorithm; experimentation; Fixed precision; Floating point numbers; Floating Point Numbers; Higher-precision arithmetic; IEEE double precision results; IEEE Standard; IEEE-conforming approximation; Intermediate result; Multiple-precision integers

subject:
bf F.2.1 Theory of Computation, ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms and Problems. bf G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic. bf G.1.2 Mathematics of Computing, NUMERICAL ANALYSIS, Approximation.

rawabstract:
Consider the problem of converting decimal scientific notation for a number into the best binary floating point approximation to that number, for some fixed precision. This problem cannot be solved using arithmetic of any fixed precision. Hence the IEEE Standard for Binary Floating-Point Arithmetic does not require the result of such a conversion to be the best approximation. This paper presents an efficient algorithm that always finds the best approximation. The algorithm uses a few extra bits of precision to compute an IEEE-conforming approximation while testing an intermediate result to determine whether the approximation could be other than the best. If the approximation might not be the best, then the best approximation is determined by a few simple operations on multiple-precision integers, where the precision is determined by the input. When using 64 bits of precision to compute IEEE double precision results, the algorithm avoids higher-precision arithmetic over 99\% of the time.

rawnote:
See also output algorithms in \cite{Knuth:1990:SPW,Steele:1990:HPF,Burger:1996:PFP,Abbott:1999:ASS,Steele:2004:RHP}.

entry:
@Article{Clinger:1990:HRF,
  author =       "William D. Clinger",
  title =        "How to Read Floating Point Numbers Accurately",
  journal =      j-SIGPLAN,
  volume =       "25",
  number =       "6",
  pages =        "92--101",
  month =        jun,
  year =         "1990",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/93548.93557",
  ISBN =         "0-89791-364-7",
  ISBN-13 =      "978-0-89791-364-5",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:15:53 MST 2003",
  bibsource =    "Compendex database;
                 ftp://garbo.uwasa.fi/pc/doc-soft/fpbiblio.txt;
                 http://portal.acm.org/;
                 http://www.acm.org/pubs/contents/proceedings/pldi/93542/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan1990.bib",
  note =         "See also output algorithms in
                 \cite{Knuth:1990:SPW,Steele:1990:HPF,Burger:1996:PFP,Abbott:1999:ASS,Steele:2004:RHP}.",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/pldi/93542/p92-clinger/",
  abstract =     "Consider the problem of converting decimal scientific
                 notation for a number into the best binary floating
                 point approximation to that number, for some fixed
                 precision. This problem cannot be solved using
                 arithmetic of any fixed precision. Hence the IEEE
                 Standard for Binary Floating-Point Arithmetic does not
                 require the result of such a conversion to be the best
                 approximation. This paper presents an efficient
                 algorithm that always finds the best approximation. The
                 algorithm uses a few extra bits of precision to compute
                 an IEEE-conforming approximation while testing an
                 intermediate result to determine whether the
                 approximation could be other than the best. If the
                 approximation might not be the best, then the best
                 approximation is determined by a few simple operations
                 on multiple-precision integers, where the precision is
                 determined by the input. When using 64 bits of
                 precision to compute IEEE double precision results, the
                 algorithm avoids higher-precision arithmetic over 99\%
                 of the time.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Oregon University, Eugene, OR, USA",
  annote =       "Published as part of the Proceedings of PLDI'90.",
  classification = "722; 723; C1160 (Combinatorial mathematics); C5230
                 (Digital arithmetic methods); C7310 (Mathematics)",
  confdate =     "20-22 June 1990",
  conference =   "Proceedings of the ACM SIGPLAN '90 Conference on
                 Programming Language Design and Implementation",
  conferenceyear = "1990",
  conflocation = "White Plains, NY, USA",
  confsponsor =  "ACM",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  journalabr =   "SIGPLAN Not",
  keywords =     "algorithms; Best binary floating point approximation;
                 Computer Programming Languages; Computers, Digital ---
                 Computational Methods; Decimal scientific notation;
                 Design; Efficient algorithm; experimentation; Fixed
                 precision; Floating point numbers; Floating Point
                 Numbers; Higher-precision arithmetic; IEEE double
                 precision results; IEEE Standard; IEEE-conforming
                 approximation; Intermediate result; Multiple-precision
                 integers",
  meetingaddress = "White Plains, NY, USA",
  meetingdate =  "Jun 20--22 1990",
  meetingdate2 = "06/20--22/90",
  sponsor =      "Assoc for Computing Machinery, Special Interest Group
                 on Programming Languages",
  subject =      "{\bf F.2.1} Theory of Computation, ANALYSIS OF
                 ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms
                 and Problems. {\bf G.1.0} Mathematics of Computing,
                 NUMERICAL ANALYSIS, General, Computer arithmetic. {\bf
                 G.1.2} Mathematics of Computing, NUMERICAL ANALYSIS,
                 Approximation.",
  thesaurus =    "Digital arithmetic; Mathematics computing; Number
                 theory; Standards",
}


bibtype: article
filename: fparith.bib
label: Codenotti:1990:ATT
author: B. Codenotti and G. Lotti and F. Romani
title: Area-time trade-offs for matrix-vector multiplication
journal: j-J-PAR-DIST-COMP
volume: 8
number: 1
pages: 52--59
month: jan
monthnumber: 1
year: 1990
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliation: Inst di Elaborazione dell'Informazione-CNR
affiliationaddress: Pisa, Italy
corpsource: Istituto di Elaborazione dell'Inf., CNR, Pisa, Italy
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: T Theoretical or Mathematical
rawauthor: B. Codenotti and G. Lotti and F. Romani
rawtitle: Area-time trade-offs for matrix-vector multiplication
keywords:
algebra; area-time complexity; Area-Time Trade-Offs; arithmetic; computation; computational complexity; Computer Systems, Digital; Computers, Digital--Computational Methods; I/O conventions; information flow; integrated logic circuits; Mathematical Techniques--Matrix Algebra; matrix; Matrix-Vector Multiplication; matrix-vector multiplication; operations; Parallel Processing; sparse matrix; VLSI

entry:
@Article{Codenotti:1990:ATT,
  author =       "B. Codenotti and G. Lotti and F. Romani",
  title =        "Area-time trade-offs for matrix-vector
                 multiplication",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "8",
  number =       "1",
  pages =        "52--59",
  month =        jan,
  year =         "1990",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Inst di Elaborazione dell'Informazione-CNR",
  affiliationaddress = "Pisa, Italy",
  classification = "722; 723; 921; B0290H (Linear algebra); B1265B
                 (Logic circuits); C4140 (Linear algebra); C4240
                 (Programming and algorithm theory)",
  corpsource =   "Istituto di Elaborazione dell'Inf., CNR, Pisa, Italy",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "algebra; area-time complexity; Area-Time Trade-Offs;
                 arithmetic; computation; computational complexity;
                 Computer Systems, Digital; Computers,
                 Digital--Computational Methods; I/O conventions;
                 information flow; integrated logic circuits;
                 Mathematical Techniques--Matrix Algebra; matrix;
                 Matrix-Vector Multiplication; matrix-vector
                 multiplication; operations; Parallel Processing; sparse
                 matrix; VLSI",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: article
filename: fparith.bib
label: Cosnard:1990:STF
author: Michel Cosnard and Jean Duprat and Yves Robert
title: Systolic triangularization over finite fields
journal: j-J-PAR-DIST-COMP
volume: 9
number: 3
pages: 252--260
month: jul
monthnumber: 7
year: 1990
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliation: Ecole Normale Superieure de Lyon Lab LIP-IMAG
affiliationaddress: Lyon, Fr
corpsource: IMAG, Ecole Normale Superieure de Lyon, France
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: P Practical; T Theoretical or Mathematical
rawauthor: Michel Cosnard and Jean Duprat and Yves Robert
rawtitle: Systolic triangularization over finite fields
keywords:
architecture; arithmetic number; computer algebra; Computer Programming--Algorithms; Computer Systems, Digital--Parallel Processing; Computers, Digital; digital arithmetic; finite fields; Gaussian Elimination; Gaussian elimination; large dense linear systems; linear algebra; Mathematical Techniques--Linear Algebra; Modular Multiplication Algorithm; parallel architectures; partial; pivoting; Special Purpose Application; systolic; Systolic Arrays; Systolic Triangularization; systolic triangularization; theory

entry:
@Article{Cosnard:1990:STF,
  author =       "Michel Cosnard and Jean Duprat and Yves Robert",
  title =        "Systolic triangularization over finite fields",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "9",
  number =       "3",
  pages =        "252--260",
  month =        jul,
  year =         "1990",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Ecole Normale Superieure de Lyon Lab LIP-IMAG",
  affiliationaddress = "Lyon, Fr",
  classification = "722; 723; 921; C4140 (Linear algebra); C5220
                 (Computer architecture); C5230 (Digital arithmetic
                 methods)",
  corpsource =   "IMAG, Ecole Normale Superieure de Lyon, France",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "architecture; arithmetic number; computer algebra;
                 Computer Programming--Algorithms; Computer Systems,
                 Digital--Parallel Processing; Computers, Digital;
                 digital arithmetic; finite fields; Gaussian
                 Elimination; Gaussian elimination; large dense linear
                 systems; linear algebra; Mathematical
                 Techniques--Linear Algebra; Modular Multiplication
                 Algorithm; parallel architectures; partial; pivoting;
                 Special Purpose Application; systolic; Systolic Arrays;
                 Systolic Triangularization; systolic triangularization;
                 theory",
  treatment =    "P Practical; T Theoretical or Mathematical",
}


bibtype: manual
filename: fparith.bib
label: Cyrix:1990:FCU
title: FasMath CX-83S87 user's manual
publisher: Cyrix Corp.
address: Richardson, TX, USA
pages: 115 + 5 + 3
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
remark: Running title: FasMath 83S87 user manual.
acknowledgement: ack-nhfb
rawtitle: {FasMath} {CX-83S87} user's manual
keywords:
Cyrix CX-83X87 (Microprocessor); Floating-point arithmetic.; Integrated circuits --- Very large scale integration.; Metal oxide semiconductors, Complementary.

entry:
@Manual{Cyrix:1990:FCU,
  title =        "{FasMath} {CX-83S87} user's manual",
  publisher =    "Cyrix Corp.",
  address =      "Richardson, TX, USA",
  pages =        "115 + 5 + 3",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Cyrix CX-83X87 (Microprocessor); Floating-point
                 arithmetic.; Integrated circuits --- Very large scale
                 integration.; Metal oxide semiconductors,
                 Complementary.",
  remark =       "Running title: FasMath 83S87 user manual.",
}


bibtype: article
filename: fparith.bib
label: Darley:1990:TFC
title: The TMS390C602A Floating-Point Coprocessor for Sparc Systems
journal: j-IEEE-MICRO
volume: 10
number: 3
pages: 36--47
month: may
monthnumber: 5
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.56324
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Feb 24 15:01:45 MST 1996
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: IEEE Micro
language: English
acknowledgement: ack-nhfb
affiliation: Texas Instrum. Inc., Dallas, TX, USA
journalURL: http://www.computer.org/csdl/mags/mi/index.html
thesaurus: Digital arithmetic; Microprocessor chips
rawtitle: The {TMS390C602A} Floating-Point Coprocessor for {Sparc} Systems
author:
Merrick Darley and Bill Kronlage and David Bural and Bob Churchill and David Pulling and Paul Wang and Rick Iwamoto and Larry Yang

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/microchip.bib

abstract:
A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented. (4 Refs.)

keywords:
Addition; Compare; Convert; Division; Linpack benchmark; Multiplication; Sparc systems; Square root; Subtraction; TMS390C601 integer unit; TMS390C602A floating-point coprocessor; TMS390C602A floating-point unit; Two-chip configuration

rawabstract:
A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented. (4 Refs.)

rawauthor:
Merrick Darley and Bill Kronlage and David Bural and Bob Churchill and David Pulling and Paul Wang and Rick Iwamoto and Larry Yang

entry:
@Article{Darley:1990:TFC,
  author =       "Merrick Darley and Bill Kronlage and David Bural and
                 Bob Churchill and David Pulling and Paul Wang and Rick
                 Iwamoto and Larry Yang",
  title =        "The {TMS390C602A} Floating-Point Coprocessor for
                 {Sparc} Systems",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "3",
  pages =        "36--47",
  month =        may # "\slash " # jun,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.56324",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "A recent Sparc (scalable processor architecture)
                 processor consists of a two-chip configuration,
                 containing the TMS390C601 integer unit (IU) and the
                 TMS390C602A floating-point unit (FPU). The second
                 device, an innovative coprocessor that lets the
                 processor execute single- or double-precision
                 floating-point instructions concurrently with IU
                 operations is described. Dedicated floating-point
                 hardware in the FPU increases the performance of the
                 system. Running at clock periods as small as 20 ns, the
                 chip should deliver 5.5 million double-precision
                 floating-point operations per second under the Linpack
                 benchmark (50-MHz clock rate). The FPU provides single-
                 and double-precision arithmetic functions: addition,
                 subtraction, multiplication, division, square root,
                 compare, and convert. To minimize its math unit's
                 latency, the FPU uses a highly parallel architecture
                 requiring separate math units to optimize additions and
                 multiplications. Traps stop the execution of a program
                 to jump to software routine for handling data-dependent
                 errors or to execute instructions not implemented in
                 the hardware. Benchmark results are presented. (4
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Texas Instrum. Inc., Dallas, TX, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Addition; Compare; Convert; Division; Linpack
                 benchmark; Multiplication; Sparc systems; Square root;
                 Subtraction; TMS390C601 integer unit; TMS390C602A
                 floating-point coprocessor; TMS390C602A floating-point
                 unit; Two-chip configuration",
  language =     "English",
  pubcountry =   "USA",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
}


bibtype: article
filename: fparith.bib
label: Darley:1990:TFP
title: The TMS390C602A Floating-Point Coprocessor for Sparc Systems
journal: j-IEEE-MICRO
volume: 10
number: 3
pages: 36--47
month: may
monthnumber: 5
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.56324
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-mfc
affiliation: Texas Instrum. Inc., Dallas, TX, USA
journalURL: http://www.computer.org/csdl/mags/mi/index.html
thesaurus: Digital arithmetic; Microprocessor chips
rawtitle: The {TMS390C602A} Floating-Point Coprocessor for {Sparc} Systems
author:
Merrick Darley and Bill Kronlage and David Bural and Bob Churchill and David Pulling and Paul Wang and Rick Iwamoto and Larry Yang

abstract:
A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented. (4 Refs.)

keywords:
Addition; Compare; Convert; Division; Linpack benchmark; Multiplication; Sparc systems; Square root; Subtraction; TMS390C601 integer unit; TMS390C602A floating-point coprocessor; TMS390C602A floating-point unit; Two-chip configuration

entry:
@Article{Darley:1990:TFP,
  author =       "Merrick Darley and Bill Kronlage and David Bural and
                 Bob Churchill and David Pulling and Paul Wang and Rick
                 Iwamoto and Larry Yang",
  title =        "The {TMS390C602A} Floating-Point Coprocessor for
                 {Sparc} Systems",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "3",
  pages =        "36--47",
  month =        may # "\slash " # jun,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.56324",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A recent Sparc (scalable processor architecture)
                 processor consists of a two-chip configuration,
                 containing the TMS390C601 integer unit (IU) and the
                 TMS390C602A floating-point unit (FPU). The second
                 device, an innovative coprocessor that lets the
                 processor execute single- or double-precision
                 floating-point instructions concurrently with IU
                 operations is described. Dedicated floating-point
                 hardware in the FPU increases the performance of the
                 system. Running at clock periods as small as 20 ns, the
                 chip should deliver 5.5 million double-precision
                 floating-point operations per second under the Linpack
                 benchmark (50-MHz clock rate). The FPU provides single-
                 and double-precision arithmetic functions: addition,
                 subtraction, multiplication, division, square root,
                 compare, and convert. To minimize its math unit's
                 latency, the FPU uses a highly parallel architecture
                 requiring separate math units to optimize additions and
                 multiplications. Traps stop the execution of a program
                 to jump to software routine for handling data-dependent
                 errors or to execute instructions not implemented in
                 the hardware. Benchmark results are presented. (4
                 Refs.)",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  affiliation =  "Texas Instrum. Inc., Dallas, TX, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Addition; Compare; Convert; Division; Linpack
                 benchmark; Multiplication; Sparc systems; Square root;
                 Subtraction; TMS390C601 integer unit; TMS390C602A
                 floating-point coprocessor; TMS390C602A floating-point
                 unit; Two-chip configuration",
  summary =      "A recent Sparc (scalable processor architecture)
                 processor consists of a two-chip configuration,
                 containing the TMS390C601 integer unit (IU) and the
                 TMS390C602A floating-point unit (FPU). The second
                 device, an innovative coprocessor that lets the
                 \ldots{}",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
}


bibtype: book
filename: fparith.bib
label: Dewar:1990:MPV
author: Robert B. K. Dewar and Matthew Smosna
title: Microprocessors: a programmer's view
publisher: pub-MCGRAW-HILL
address: pub-MCGRAW-HILL:adr
pages: xvii + 462
year: 1990
ISBN: 0-07-016638-2, 0-07-016639-0 (soft) OR 0070166382, 0070166390 (soft)
ISBN13: 978-0-07-016638-7, 978-0-07-016639-4 (soft) OR 9780070166387, 9780070166394 (soft)
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Microprocessors --- Programming.
acknowledgement: ack-nhfb
rawauthor: Robert B. K. Dewar and Matthew Smosna
rawtitle: Microprocessors: a programmer's view
remark:
Microprocessors --- Introduction to the 80386 --- Addressing and memory on the 80386 --- Tasking, virtual memory, and exceptions to the 80386 --- Microprocessors and floating-point arithmetic --- 68030 user programming model --- 68030 supervisor state --- Introduction to RISC architectures --- MIPS processors --- SPARC architecture --- Intel i860 --- IBM RISC chips --- INMOS transputer - - Future of microprocessor design.

entry:
@Book{Dewar:1990:MPV,
  author =       "Robert B. K. Dewar and Matthew Smosna",
  title =        "Microprocessors: a programmer's view",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "xvii + 462",
  year =         "1990",
  ISBN =         "0-07-016638-2, 0-07-016639-0 (soft)",
  ISBN-13 =      "978-0-07-016638-7, 978-0-07-016639-4 (soft)",
  LCCN =         "????",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Microprocessors --- Programming.",
  remark =       "Microprocessors --- Introduction to the 80386 ---
                 Addressing and memory on the 80386 --- Tasking, virtual
                 memory, and exceptions to the 80386 --- Microprocessors
                 and floating-point arithmetic --- 68030 user
                 programming model --- 68030 supervisor state ---
                 Introduction to RISC architectures --- MIPS processors
                 --- SPARC architecture --- Intel i860 --- IBM RISC
                 chips --- INMOS transputer - - Future of microprocessor
                 design.",
}


bibtype: inproceedings
filename: fparith.bib
label: Dixon:1990:HPB
author: G. Dixon
title: A high performance block floating point DSP chip-set
crossref: IEE:1990:ICV
pages: 9/1--7
year: 1990
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Plessey Res. Caswell, Towcester, UK
rawauthor: G. Dixon
rawtitle: A high performance block floating point {DSP} chip-set
abstract:
This paper describes the design and development of two ASICs which form the processing kernel of a high performance sonar signal processor; namely a 24-bit Block Floating Point Arithmetic Unit (BFPAU), and a Table Memory And Address Modifier (TMAAM). The system is based upon a 24-bit block floating point data format which is a compromise between fixed and floating point data; possessing the advantage of reducing the data storage requirement compared to true floating point while allowing arithmetic to be performed in the faster fixed-point format whilst retaining the extended dynamic range provided by floating point. The BFPAU and TMAAM perform the arithmetic processing; the BFPAU is the central arithmetic processor aimed at sonar signal processing in general and beamforming in particular, while the TMAAM provides a range of essential support functions such as look-up tables for trigonometric functions, address generation, exponent control and normalisation and program sequencing. Two blocks of dual-port RAM provide storage for system I/O data transfers, together with two blocks of RAM providing working data storage for the BFPAU. A block of video RAM is used to store address and control sequences for the processing element.

keywords:
Address generation; Arithmetic processing; ASICs; Beamforming; Block floating point DSP chip-set; Data format; Data storage requirement; Dual-port RAM; Dynamic range; Exponent control; Fixed-point format; Look-up tables; Normalisation; Program sequencing; Sonar signal processor; System I/O data transfers; Video RAM; Working data storage

thesaurus:
Application specific integrated circuits; Digital signal processing chips; Random-access storage; Sonar

rawabstract:
This paper describes the design and development of two ASICs which form the processing kernel of a high performance sonar signal processor; namely a 24-bit Block Floating Point Arithmetic Unit (BFPAU), and a Table Memory And Address Modifier (TMAAM). The system is based upon a 24-bit block floating point data format which is a compromise between fixed and floating point data; possessing the advantage of reducing the data storage requirement compared to true floating point while allowing arithmetic to be performed in the faster fixed-point format whilst retaining the extended dynamic range provided by floating point. The BFPAU and TMAAM perform the arithmetic processing; the BFPAU is the central arithmetic processor aimed at sonar signal processing in general and beamforming in particular, while the TMAAM provides a range of essential support functions such as look-up tables for trigonometric functions, address generation, exponent control and normalisation and program sequencing. Two blocks of dual-port RAM provide storage for system I/O data transfers, together with two blocks of RAM providing working data storage for the BFPAU. A block of video RAM is used to store address and control sequences for the processing element.

entry:
@InProceedings{Dixon:1990:HPB,
  author =       "G. Dixon",
  title =        "A high performance block floating point {DSP}
                 chip-set",
  crossref =     "IEE:1990:ICV",
  pages =        "9/1--7",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper describes the design and development of two
                 ASICs which form the processing kernel of a high
                 performance sonar signal processor; namely a 24-bit
                 Block Floating Point Arithmetic Unit (BFPAU), and a
                 Table Memory And Address Modifier (TMAAM). The system
                 is based upon a 24-bit block floating point data format
                 which is a compromise between fixed and floating point
                 data; possessing the advantage of reducing the data
                 storage requirement compared to true floating point
                 while allowing arithmetic to be performed in the faster
                 fixed-point format whilst retaining the extended
                 dynamic range provided by floating point. The BFPAU and
                 TMAAM perform the arithmetic processing; the BFPAU is
                 the central arithmetic processor aimed at sonar signal
                 processing in general and beamforming in particular,
                 while the TMAAM provides a range of essential support
                 functions such as look-up tables for trigonometric
                 functions, address generation, exponent control and
                 normalisation and program sequencing. Two blocks of
                 dual-port RAM provide storage for system I/O data
                 transfers, together with two blocks of RAM providing
                 working data storage for the BFPAU. A block of video
                 RAM is used to store address and control sequences for
                 the processing element.",
  acknowledgement = ack-nhfb,
  affiliation =  "Plessey Res. Caswell, Towcester, UK",
  classification = "B1265F (Microprocessors and microcomputers); B6320E
                 (Sonar and acoustic radar)",
  keywords =     "Address generation; Arithmetic processing; ASICs;
                 Beamforming; Block floating point DSP chip-set; Data
                 format; Data storage requirement; Dual-port RAM;
                 Dynamic range; Exponent control; Fixed-point format;
                 Look-up tables; Normalisation; Program sequencing;
                 Sonar signal processor; System I/O data transfers;
                 Video RAM; Working data storage",
  thesaurus =    "Application specific integrated circuits; Digital
                 signal processing chips; Random-access storage; Sonar",
}


bibtype: article
filename: fparith.bib
label: Dotzel:1990:DMG
author: Gunter Dotzel
journal: j-SIGPLAN
volume: 25
number: 12
pages: 85--88
month: dec
monthnumber: 12
year: 1990
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:00 MST 2003
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:16:00 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: ModulaWare GmbH, Erlangen, West Germany
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
thesaurus: Modula; Modula listings; Program compilers; Program testing
rawauthor: G{\"u}nter Dotzel
title:
Does Modula-2 generate racehorses? Comparison of compiler generated code quality for floating point arithmetic

abstract:
A simple example serves to demonstrate the code quality generated by two different Modula-2 compilers. The two compilers are called the Zurich/Hamburger and the Erlanger. The author lists the Modula-2 source program, shows an excerpt of the machine code listing generated by the Erlanger and presents that of the Zurich/Hamburger. The differences in code quality concerning instruction count, code size and execution speed are discussed and summarized. The author also presents the main program module used for the benchmarks and a short description of the development history of Modula-2 and Modula/R.

keywords:
Benchmarks; Code size; Compiler generated code quality; Development history; Erlanger; Execution speed; Floating point arithmetic; Instruction count; Machine code listing; Main program module; Modula-2 compilers; Modula-2 source program; Modula/R; Zurich/Hamburger

rawabstract:
A simple example serves to demonstrate the code quality generated by two different Modula-2 compilers. The two compilers are called the Zurich/Hamburger and the Erlanger. The author lists the Modula-2 source program, shows an excerpt of the machine code listing generated by the Erlanger and presents that of the Zurich/Hamburger. The differences in code quality concerning instruction count, code size and execution speed are discussed and summarized. The author also presents the main program module used for the benchmarks and a short description of the development history of Modula-2 and Modula/R.

rawtitle:
Does {Modula-2} generate racehorses? Comparison of compiler generated code quality for floating point arithmetic

entry:
@Article{Dotzel:1990:DMG,
  author =       "G{\"u}nter Dotzel",
  title =        "Does {Modula-2} generate racehorses? Comparison of
                 compiler generated code quality for floating point
                 arithmetic",
  journal =      j-SIGPLAN,
  volume =       "25",
  number =       "12",
  pages =        "85--88",
  month =        dec,
  year =         "1990",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:00 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A simple example serves to demonstrate the code
                 quality generated by two different Modula-2 compilers.
                 The two compilers are called the Zurich/Hamburger and
                 the Erlanger. The author lists the Modula-2 source
                 program, shows an excerpt of the machine code listing
                 generated by the Erlanger and presents that of the
                 Zurich/Hamburger. The differences in code quality
                 concerning instruction count, code size and execution
                 speed are discussed and summarized. The author also
                 presents the main program module used for the
                 benchmarks and a short description of the development
                 history of Modula-2 and Modula/R.",
  acknowledgement = ack-nhfb,
  affiliation =  "ModulaWare GmbH, Erlangen, West Germany",
  classification = "C6140D (High level languages); C6150C (Compilers,
                 interpreters and other processors); C6150G (Diagnostic,
                 testing, debugging and evaluating systems)",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "Benchmarks; Code size; Compiler generated code
                 quality; Development history; Erlanger; Execution
                 speed; Floating point arithmetic; Instruction count;
                 Machine code listing; Main program module; Modula-2
                 compilers; Modula-2 source program; Modula/R;
                 Zurich/Hamburger",
  thesaurus =    "Modula; Modula listings; Program compilers; Program
                 testing",
}


bibtype: article
filename: fparith.bib
label: Dunham:1990:FFE
author: C. B. Dunham
title: Feasibility of `Perfect' Function Evaluation
journal: j-SIGNUM
volume: 25
number: 4
pages: 25--26
month: oct
monthnumber: 10
year: 1990
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Thu Sep 1 10:15:30 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:30 ???
fjournal: ACM SIGNUM Newsletter
acknowledgement: ack-nj
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J690
rawauthor: C. B. Dunham
rawtitle: Feasibility of `Perfect' Function Evaluation
entry:
@Article{Dunham:1990:FFE,
  author =       "C. B. Dunham",
  title =        "Feasibility of `Perfect' Function Evaluation",
  journal =      j-SIGNUM,
  volume =       "25",
  number =       "4",
  pages =        "25--26",
  month =        oct,
  year =         "1990",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Thu Sep 1 10:15:30 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J690",
}


bibtype: article
filename: fparith.bib
label: Edenfield:1990:PPD
title: The 68040 Processor. Part 1, Design and Implementation
journal: j-IEEE-MICRO
volume: 10
number: 1
pages: 66--78
month: jan
monthnumber: 1
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.46770
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Wed Sep 7 22:32:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:42 ???
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawtitle: The 68040 Processor. {Part} 1, Design and Implementation
author:
R. W. Edenfield and M. G. Gallup and W. B. Ledbetter, Jr. and R. C. McGarity and E. E. Quintana and R. A. Reininger

rawauthor:
R. W. Edenfield and M. G. Gallup and W. B. {Ledbetter, Jr.} and R. C. McGarity and E. E. Quintana and R. A. Reininger

entry:
@Article{Edenfield:1990:PPD,
  author =       "R. W. Edenfield and M. G. Gallup and W. B. {Ledbetter,
                 Jr.} and R. C. McGarity and E. E. Quintana and R. A.
                 Reininger",
  title =        "The 68040 Processor. {Part} 1, Design and
                 Implementation",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "1",
  pages =        "66--78",
  month =        jan # "\slash " # feb,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.46770",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Wed Sep 7 22:32:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}


bibtype: article
filename: fparith.bib
label: Ercegovac:1990:FMC
author: M. D. Ercegovac and T. Lang
title: Fast multiplication without carry-propagate addition
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 11
pages: 1385--1390
month: nov
monthnumber: 11
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.61047
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:05 MDT 2011
bibtimestamp: 2011.07.07 14:20:05 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=61047
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. D. Ercegovac and T. Lang
rawtitle: Fast multiplication without carry-propagate addition
entry:
@Article{Ercegovac:1990:FMC,
  author =       "M. D. Ercegovac and T. Lang",
  title =        "Fast multiplication without carry-propagate addition",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "11",
  pages =        "1385--1390",
  month =        nov,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.61047",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:05 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=61047",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Ercegovac:1990:RSR
author: M. D. Ercegovac and T. Lang
title: Radix-$4$ square root without initial PLA
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 8
pages: 1016--1024
month: aug
monthnumber: 8
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57040
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:03 MDT 2011
bibtimestamp: 2011.07.07 14:20:03 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57040
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. D. Ercegovac and T. Lang
rawtitle: Radix-$4$ square root without initial {PLA}
entry:
@Article{Ercegovac:1990:RSR,
  author =       "M. D. Ercegovac and T. Lang",
  title =        "Radix-$4$ square root without initial {PLA}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "8",
  pages =        "1016--1024",
  month =        aug,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57040",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:03 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57040",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Ercegovac:1990:SRD
author: M. D. Ercegovac and T. Lang
title: Simple radix-$4$ division with operands scaling
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 9
pages: 1204--1208
month: sep
monthnumber: 9
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57060
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:04 MDT 2011
bibtimestamp: 2011.07.07 14:20:04 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57060
fjournal: IEEE Transactions on Computers
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. D. Ercegovac and T. Lang
rawtitle: Simple radix-$4$ division with operands scaling
entry:
@Article{Ercegovac:1990:SRD,
  author =       "M. D. Ercegovac and T. Lang",
  title =        "Simple radix-$4$ division with operands scaling",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "9",
  pages =        "1204--1208",
  month =        sep,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57060",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:04 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57060",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Fussichen:1990:GAM
author: Kenneth Fussichen
title: Getting Ada into the mainstream in the 1990's
crossref: ACM:1990:PDB
pages: 428--428
year: 1990
DOI: https://doi.org/10.1145/255471.255572
bibdate: Thu Aug 07 18:17:35 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 18:17:35 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Kenneth Fussichen
rawtitle: Getting {Ada} into the mainstream in the 1990's
abstract:
Ada offers a great deal to the MIS community. There are a number of language features that provide attractive tools to the programmer. Ada's support for Object Orientation is far superior to that currently afforded by IBM mainframe languages such as COBOL and PL/1. This translates into more maintainable code, which is the key to MIS Ada acceptance.par Unfortunately, Ada introduces problems that do not currently exist in MIS. Decimal arithmetic and string manipulation adequate to support reporting are inherently non-existent. I/O support is inadequate as are DBMS bindings. Conversions are forced on non-ASCII hosts. The compiler has the option of reordering fields within records, rendering non-Ada utilities useless. There is an inexcusable lack of understanding of the targeted market.

rawabstract:
Ada offers a great deal to the MIS community. There are a number of language features that provide attractive tools to the programmer. Ada's support for Object Orientation is far superior to that currently afforded by IBM mainframe languages such as COBOL and PL/1. This translates into more maintainable code, which is the key to MIS Ada acceptance.\par Unfortunately, Ada introduces problems that do not currently exist in MIS. Decimal arithmetic and string manipulation adequate to support reporting are inherently non-existent. I/O support is inadequate as are DBMS bindings. Conversions are forced on non-ASCII hosts. The compiler has the option of reordering fields within records, rendering non-Ada utilities useless. There is an inexcusable lack of understanding of the targeted market.

entry:
@InProceedings{Fussichen:1990:GAM,
  author =       "Kenneth Fussichen",
  title =        "Getting {Ada} into the mainstream in the 1990's",
  crossref =     "ACM:1990:PDB",
  pages =        "428--428",
  year =         "1990",
  DOI =          "https://doi.org/10.1145/255471.255572",
  bibdate =      "Thu Aug 07 18:17:35 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Ada offers a great deal to the MIS community. There
                 are a number of language features that provide
                 attractive tools to the programmer. Ada's support for
                 Object Orientation is far superior to that currently
                 afforded by IBM mainframe languages such as COBOL and
                 PL/1. This translates into more maintainable code,
                 which is the key to MIS Ada
                 acceptance.\par

                 Unfortunately, Ada introduces problems that do not
                 currently exist in MIS. Decimal arithmetic and string
                 manipulation adequate to support reporting are
                 inherently non-existent. I/O support is inadequate as
                 are DBMS bindings. Conversions are forced on non-ASCII
                 hosts. The compiler has the option of reordering fields
                 within records, rendering non-Ada utilities useless.
                 There is an inexcusable lack of understanding of the
                 targeted market.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Gallant:1990:MCI
author: John Gallant and Bill Travis
title: Math coprocessor ICs: Floating-point chips boost muP performance
journal: j-EDN
volume: 35
number: 12
pages: 63--??
month: jun
monthnumber: 6
year: 1990
CODEN: EDNSBH
ISSN: 0012-7515, 0364-6637 OR 00127515, 03646637
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: EDN
acknowledgement: ack-nhfb
rawauthor: John Gallant and Bill Travis
rawtitle: Math coprocessor {ICs}: Floating-point chips boost {muP} performance
abstract:
Floating-point arithmetic exacts huge penalties in CPU computation time. Dedicated coprocessor ICs execute this onerous task automatically and efficiently.

rawabstract:
Floating-point arithmetic exacts huge penalties in CPU computation time. Dedicated coprocessor ICs execute this onerous task automatically and efficiently.

entry:
@Article{Gallant:1990:MCI,
  author =       "John Gallant and Bill Travis",
  title =        "Math coprocessor {ICs}: Floating-point chips boost
                 {muP} performance",
  journal =      j-EDN,
  volume =       "35",
  number =       "12",
  pages =        "63--??",
  month =        jun,
  year =         "1990",
  CODEN =        "EDNSBH",
  ISSN =         "0012-7515, 0364-6637",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating-point arithmetic exacts huge penalties in CPU
                 computation time. Dedicated coprocessor ICs execute
                 this onerous task automatically and efficiently.",
  acknowledgement = ack-nhfb,
  fjournal =     "EDN",
}


bibtype: techreport
filename: fparith.bib
label: Gay:1990:CRB
author: David M. Gay
title: Correctly Rounded Binary-Decimal and Decimal-Binary Conversions
type: Numerical Analysis Manuscript
number: 90-10
institution: AT&T Bell Laboratories
pages: 16
month: nov
monthnumber: 11
year: 1990
bibdate: Sat Apr 28 18:42:55 2001
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.04.28 18:42:55 ???
keywords: correct rounding; decimal floating-point arithmetic
acknowledgement: ack-nj
rawauthor: David M. Gay
rawtitle: Correctly Rounded Binary-Decimal and Decimal-Binary Conversions
URL:
http://cm.bell-labs.com/cm/cs/doc/90/4-10.ps.gz; http://www.ampl.com/ampl/REFS/rounding.ps.gz; http://www.netlib.org/fp/dtoa.c; http://www.netlib.org/fp/g_fmt.c; http://www.netlib.org/fp/gdtoa.tgz; http://www.netlib.org/fp/rnd_prod.s

entry:
@TechReport{Gay:1990:CRB,
  author =       "David M. Gay",
  title =        "Correctly Rounded Binary-Decimal and Decimal-Binary
                 Conversions",
  type =         "Numerical Analysis Manuscript",
  number =       "90-10",
  institution =  "AT\&T Bell Laboratories",
  pages =        "16",
  month =        nov # " 30",
  year =         "1990",
  bibdate =      "Sat Apr 28 18:42:55 2001",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://cm.bell-labs.com/cm/cs/doc/90/4-10.ps.gz;
                 http://www.ampl.com/ampl/REFS/rounding.ps.gz;
                 http://www.netlib.org/fp/dtoa.c;
                 http://www.netlib.org/fp/g_fmt.c;
                 http://www.netlib.org/fp/gdtoa.tgz;
                 http://www.netlib.org/fp/rnd_prod.s",
  acknowledgement = ack-nj,
  keywords =     "correct rounding; decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Gibson:1990:CII
author: D. H. Gibson
title: Considerations for including IEEE floating point in large systems
crossref: SHARE:1990:PSE
pages: 47--62
year: 1990
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
keywords: Application portability; Floating-point arithmetic; IEEE Std 754 floating point; SHARE
acknowledgement: ack-nhfb
affiliation: IBM Corp., Poughkeepsie, NY, USA
thesaurus: Digital arithmetic; Standards
rawauthor: D. H. Gibson
rawtitle: Considerations for including {IEEE} floating point in large systems
abstract:
International standards such as ANSI/IEEE Std 754-1985 floating-point arithmetic provide the potential for application portability. The paper, beginning with a 1984 SHARE requirements statement, sets forth certain considerations for including IEEE Std 754 floating point in large systems. A tutorial is presented on IEEE Std 754 floating-point arithmetic. The considerations for integrating IEEE into a large system along with an existing floating point representation are discussed in three categories: architectural; implementation; usage. Related topics are identified and discussed. The paper concludes with a summary of the considerations. (11 Refs.)

rawabstract:
International standards such as ANSI/IEEE Std 754-1985 floating-point arithmetic provide the potential for application portability. The paper, beginning with a 1984 SHARE requirements statement, sets forth certain considerations for including IEEE Std 754 floating point in large systems. A tutorial is presented on IEEE Std 754 floating-point arithmetic. The considerations for integrating IEEE into a large system along with an existing floating point representation are discussed in three categories: architectural; implementation; usage. Related topics are identified and discussed. The paper concludes with a summary of the considerations. (11 Refs.)

entry:
@InProceedings{Gibson:1990:CII,
  author =       "D. H. Gibson",
  title =        "Considerations for including {IEEE} floating point in
                 large systems",
  crossref =     "SHARE:1990:PSE",
  pages =        "47--62",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "International standards such as ANSI/IEEE Std 754-1985
                 floating-point arithmetic provide the potential for
                 application portability. The paper, beginning with a
                 1984 SHARE requirements statement, sets forth certain
                 considerations for including IEEE Std 754 floating
                 point in large systems. A tutorial is presented on IEEE
                 Std 754 floating-point arithmetic. The considerations
                 for integrating IEEE into a large system along with an
                 existing floating point representation are discussed in
                 three categories: architectural; implementation; usage.
                 Related topics are identified and discussed. The paper
                 concludes with a summary of the considerations. (11
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Poughkeepsie, NY, USA",
  classification = "C5230 (Digital arithmetic methods)",
  keywords =     "Application portability; Floating-point arithmetic;
                 IEEE Std 754 floating point; SHARE",
  thesaurus =    "Digital arithmetic; Standards",
}


bibtype: article
filename: fparith.bib
label: Glass:1990:MC
author: L. B. Glass
title: Math coprocessors
journal: j-BYTE
volume: 15
number: 1
pages: 337--348
month: jan
monthnumber: 1
year: 1990
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 12 17:47:21 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.12 17:47:21 MDT
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
thesaurus: Digital arithmetic; Microprocessor chips; Satellite computers
rawauthor: L. B. Glass
rawtitle: Math coprocessors
keywords:
Cyrix 83D87; Floating-point maths; IEEE 754 floating-point standard; Integrated Information Technology; Intel 80287; Intel 80387; Intel 8087; Maths coprocessors; Motorola 68881; Motorola 68882; NP-3C87; Weitek Abacus 3167

entry:
@Article{Glass:1990:MC,
  author =       "L. B. Glass",
  title =        "Math coprocessors",
  journal =      j-BYTE,
  volume =       "15",
  number =       "1",
  pages =        "337--348",
  month =        jan,
  year =         "1990",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 12 17:47:21 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B1265B (Logic circuits); B1265F (Microprocessors and
                 microcomputers); C5130 (Microprocessor chips); C5230
                 (Digital arithmetic methods)",
  fjournal =     "BYTE Magazine",
  keywords =     "Cyrix 83D87; Floating-point maths; IEEE 754
                 floating-point standard; Integrated Information
                 Technology; Intel 80287; Intel 80387; Intel 8087; Maths
                 coprocessors; Motorola 68881; Motorola 68882; NP-3C87;
                 Weitek Abacus 3167",
  thesaurus =    "Digital arithmetic; Microprocessor chips; Satellite
                 computers",
}


bibtype: incollection
filename: fparith.bib
label: Goldberg:1990:CA
author: D. Goldberg
title: Computer Arithmetic
crossref: Hennessy:1990:CAQ
chapter: A
pages: A-1--A-66
year: 1990
bibdate: Fri Dec 08 13:04:21 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 13:04:21 ???
acknowledgement: ack-nj
rawauthor: D. Goldberg
rawtitle: Computer Arithmetic
entry:
@InCollection{Goldberg:1990:CA,
  author =       "D. Goldberg",
  title =        "Computer Arithmetic",
  crossref =     "Hennessy:1990:CAQ",
  chapter =      "A",
  pages =        "A-1--A-66",
  year =         "1990",
  bibdate =      "Fri Dec 08 13:04:21 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Goodman:1990:SMR
author: R. H. Goodman
title: Some Models of Relative Error in Products
journal: j-APPL-NUM-MATH
volume: 6
number: 3
pages: 209--220
month: mar
monthnumber: 3
year: 1990
CODEN: ANMAEL
ISSN: 0168-9274 (print), 1873-5460 (electronic) OR 01689274 (print), 18735460 (electronic)
ISSNL: 0168-9274 OR 01689274
bibdate: Thu Sep 1 10:14:16 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:14:16 ???
fjournal: Applied Numerical Mathematics: Transactions of IMACS
acknowledgement: ack-nj
journalURL: http://www.sciencedirect.com/science/journal/01689274
rawauthor: R. H. Goodman
rawtitle: Some Models of Relative Error in Products
entry:
@Article{Goodman:1990:SMR,
  author =       "R. H. Goodman",
  title =        "Some Models of Relative Error in Products",
  journal =      j-APPL-NUM-MATH,
  volume =       "6",
  number =       "3",
  pages =        "209--220",
  month =        mar,
  year =         "1990",
  CODEN =        "ANMAEL",
  ISSN =         "0168-9274 (print), 1873-5460 (electronic)",
  ISSN-L =       "0168-9274",
  bibdate =      "Thu Sep 1 10:14:16 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Applied Numerical Mathematics: Transactions of IMACS",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01689274",
}


bibtype: mastersthesis
filename: fparith.bib
label: Goodreau:1990:DIF
author: Michael S. Goodreau
title: The design and implementation of a floating-point format conversion integrated circuit
type: Thesis (M.S.E.E.)
school: University of Washington
address: Seattle, WA, USA
pages: ix + 113
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Michael S. Goodreau
rawtitle: The design and implementation of a floating-point format conversion integrated circuit
keywords:
Electronic digital computers --- Programming.; Floating-point arithmetic.; Integrated circuits --- Design and construction.

entry:
@MastersThesis{Goodreau:1990:DIF,
  author =       "Michael S. Goodreau",
  title =        "The design and implementation of a floating-point
                 format conversion integrated circuit",
  type =         "Thesis ({M.S.E.E.})",
  school =       "University of Washington",
  address =      "Seattle, WA, USA",
  pages =        "ix + 113",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Electronic digital computers --- Programming.;
                 Floating-point arithmetic.; Integrated circuits ---
                 Design and construction.",
}


bibtype: incollection
filename: fparith.bib
label: Gries:1990:BDO
author: David Gries
title: Binary to Decimal, One More Time
crossref: Feijen:1990:BOB
chapter: 16
pages: 141--148
year: 1990
DOI: https://doi.org/10.1007/978-1-4612-4476-9_17
bibdate: Sat Sep 03 09:41:32 1994
bibtimestamp: 1994.09.03 09:41:32 ???
URL: https://link.springer.com/chapter/10.1007/978-1-4612-4476-9_17
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: David Gries
rawtitle: Binary to Decimal, One More Time
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/texbook3.bib

note:
This paper presents an alternate proof of Knuth's algorithm cite Knuth:1990:SPW for conversion between decimal and fixed-point binary numbers.

rawnote:
This paper presents an alternate proof of Knuth's algorithm \cite{Knuth:1990:SPW} for conversion between decimal and fixed-point binary numbers.

entry:
@InCollection{Gries:1990:BDO,
  author =       "David Gries",
  title =        "Binary to Decimal, One More Time",
  crossref =     "Feijen:1990:BOB",
  chapter =      "16",
  pages =        "141--148",
  year =         "1990",
  DOI =          "https://doi.org/10.1007/978-1-4612-4476-9_17",
  bibdate =      "Sat Sep 03 09:41:32 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/texbook3.bib",
  note =         "This paper presents an alternate proof of Knuth's
                 algorithm \cite{Knuth:1990:SPW} for conversion between
                 decimal and fixed-point binary numbers.",
  URL =          "https://link.springer.com/chapter/10.1007/978-1-4612-4476-9_17",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Gu:1990:TIT
author: Li Zhen Gu and Xing Yuan Chen
journal: Journal of Tsinghua University
volume: 30
number: 3
pages: 31--38
year: 1990
MRclass: 65D20 (65-04)
MRnumber: 92a:65070
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
acknowledgement: ack-nhfb
ajournal: J. Tsinghua Univ.
rawauthor: Li Zhen Gu and Xing Yuan Chen
title:
Table-driven implementation of the trigonometric functions using IEEE floating point operations. (Chinese)

rawtitle:
Table-driven implementation of the trigonometric functions using {IEEE} floating point operations. ({Chinese})

entry:
@Article{Gu:1990:TIT,
  author =       "Li Zhen Gu and Xing Yuan Chen",
  title =        "Table-driven implementation of the trigonometric
                 functions using {IEEE} floating point operations.
                 ({Chinese})",
  journal =      "Journal of Tsinghua University",
  volume =       "30",
  number =       "3",
  pages =        "31--38",
  year =         "1990",
  MRclass =      "65D20 (65-04)",
  MRnumber =     "92a:65070",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Tsinghua Univ.",
}


bibtype: book
filename: fparith.bib
label: Hamacher:1990:CO
author: V. Carl Hamacher and Zvonko G. Vranesic and Safwat G. Zaky
title: Computer organization
publisher: pub-MCGRAW-HILL
address: pub-MCGRAW-HILL:adr
edition: Third
pages: xx + 617
year: 1990
ISBN: 0-07-025685-3 OR 0070256853
ISBN13: 978-0-07-025685-9 OR 9780070256859
LCCN: QA76.9.A73 H351 1990
bibdate: Sat May 18 14:24:11 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.18 14:24:11 ???
series: McGraw-Hill series in computer organization and architecture
acknowledgement: ack-nhfb
rawauthor: V. Carl Hamacher and Zvonko G. Vranesic and Safwat G. Zaky
rawtitle: Computer organization
entry:
@Book{Hamacher:1990:CO,
  author =       "V. Carl Hamacher and Zvonko G. Vranesic and Safwat G.
                 Zaky",
  title =        "Computer organization",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  edition =      "Third",
  pages =        "xx + 617",
  year =         "1990",
  ISBN =         "0-07-025685-3",
  ISBN-13 =      "978-0-07-025685-9",
  LCCN =         "QA76.9.A73 H351 1990",
  bibdate =      "Sat May 18 14:24:11 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "McGraw-Hill series in computer organization and
                 architecture",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hashemian:1990:SRA
author: R. Hashemian
title: Square Rooting Algorithms for Integer and Floating-Point Numbers
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 8
pages: 1025--1029
month: aug
monthnumber: 8
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57041
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:03 MDT 2011
bibtimestamp: 2011.07.07 14:20:03 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57041
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng., Northern Illinois University, Dekalb, IL, USA
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
thesaurus: Digital arithmetic; Iterative methods; Number theory
rawauthor: R. Hashemian
rawtitle: Square Rooting Algorithms for Integer and Floating-Point Numbers
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

abstract:
An algorithm for evaluating the square root of integers and real numbers is developed. The procedure consists of two parts: one to obtain a close estimate of the square root and the other to modify the initial value, iteratively, until a precise root is evaluated. The major effort in this development has been concentrated on two objectives: high speed and no division operation other than division by 2. The first objective is achieved through a simple two-step procedure for getting the first estimate, and then modifying it by employing a fast converging iteration technique. The second objective is also fulfilled through applying bit-shift operation rather than division operation. The algorithm is simulated for both integer and real numbers, and the results are compared to two methods being widely used. The results (tabulated) show considerable improvement in speed compared to these other two methods.

keywords:
Bit-shift operation; Close estimate; Division by 2; Fast converging iteration; Floating-point numbers; Initial value modification; Integer numbers; Precise root; Real numbers; Square rooting algorithms

rawabstract:
An algorithm for evaluating the square root of integers and real numbers is developed. The procedure consists of two parts: one to obtain a close estimate of the square root and the other to modify the initial value, iteratively, until a precise root is evaluated. The major effort in this development has been concentrated on two objectives: high speed and no division operation other than division by 2. The first objective is achieved through a simple two-step procedure for getting the first estimate, and then modifying it by employing a fast converging iteration technique. The second objective is also fulfilled through applying bit-shift operation rather than division operation. The algorithm is simulated for both integer and real numbers, and the results are compared to two methods being widely used. The results (tabulated) show considerable improvement in speed compared to these other two methods.

entry:
@Article{Hashemian:1990:SRA,
  author =       "R. Hashemian",
  title =        "Square Rooting Algorithms for Integer and
                 Floating-Point Numbers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "8",
  pages =        "1025--1029",
  month =        aug,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57041",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:03 MDT 2011",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57041",
  abstract =     "An algorithm for evaluating the square root of
                 integers and real numbers is developed. The procedure
                 consists of two parts: one to obtain a close estimate
                 of the square root and the other to modify the initial
                 value, iteratively, until a precise root is evaluated.
                 The major effort in this development has been
                 concentrated on two objectives: high speed and no
                 division operation other than division by 2. The first
                 objective is achieved through a simple two-step
                 procedure for getting the first estimate, and then
                 modifying it by employing a fast converging iteration
                 technique. The second objective is also fulfilled
                 through applying bit-shift operation rather than
                 division operation. The algorithm is simulated for both
                 integer and real numbers, and the results are compared
                 to two methods being widely used. The results
                 (tabulated) show considerable improvement in speed
                 compared to these other two methods.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Department of Electr. Eng., Northern Illinois
                 University, Dekalb, IL, USA",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C1160 (Combinatorial mathematics); C4130
                 (Interpolation and function approximation); C5230
                 (Digital arithmetic methods)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Bit-shift operation; Close estimate; Division by 2;
                 Fast converging iteration; Floating-point numbers;
                 Initial value modification; Integer numbers; Precise
                 root; Real numbers; Square rooting algorithms",
  summary =      "An algorithm for evaluating the square root of
                 integers and real numbers is developed. The procedure
                 consists of two parts: one to obtain a close estimate
                 of the square root and the other to modify the initial
                 value, iteratively, until a precise \ldots{}",
  thesaurus =    "Digital arithmetic; Iterative methods; Number theory",
}


bibtype: article
filename: fparith.bib
label: Hokenek:1990:LZA
author: E. Hokenek and R. K. Montoye
title: Leading-zero anticipator (LZA) in the IBM RISC System / 6000 floating-point execution unit
journal: j-IBM-JRD
volume: 34
number: 1
pages: 71--77
month: jan
monthnumber: 1
year: 1990
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
thesaurus: Digital arithmetic; IBM computers; Reduced instruction set computing
rawauthor: E. Hokenek and R. K. Montoye
rawtitle: Leading-zero anticipator ({LZA}) in the {IBM RISC System\slash 6000} floating-point execution unit
abstract:
Presents a novel technique used in the multiply-add-fused (MAF) unit of the IBM RISC System/6000 (RS/6000) processor for normalizing the floating-point results. Unlike the conventional procedures applied thus far, the so-called leading-zero anticipator (LZA) of the RS/6000 carries out processing of the leading zeros and ones in parallel with floating-point addition. Therefore, the new circuitry reduces the total latency of the MAF unit by enabling the normalization and addition to take place in a single cycle.

keywords:
Circuitry; Floating-point addition; IBM RISC System/6000 floating-point execution unit; Latency; Leading-zero anticipator; Multiply-add-fused; Normalization; Parallel

rawabstract:
Presents a novel technique used in the multiply-add-fused (MAF) unit of the IBM RISC System/6000 (RS/6000) processor for normalizing the floating-point results. Unlike the conventional procedures applied thus far, the so-called leading-zero anticipator (LZA) of the RS/6000 carries out processing of the leading zeros and ones in parallel with floating-point addition. Therefore, the new circuitry reduces the total latency of the MAF unit by enabling the normalization and addition to take place in a single cycle.

entry:
@Article{Hokenek:1990:LZA,
  author =       "E. Hokenek and R. K. Montoye",
  title =        "Leading-zero anticipator ({LZA}) in the {IBM RISC
                 System\slash 6000} floating-point execution unit",
  journal =      j-IBM-JRD,
  volume =       "34",
  number =       "1",
  pages =        "71--77",
  month =        jan,
  year =         "1990",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents a novel technique used in the
                 multiply-add-fused (MAF) unit of the IBM RISC
                 System/6000 (RS/6000) processor for normalizing the
                 floating-point results. Unlike the conventional
                 procedures applied thus far, the so-called leading-zero
                 anticipator (LZA) of the RS/6000 carries out processing
                 of the leading zeros and ones in parallel with
                 floating-point addition. Therefore, the new circuitry
                 reduces the total latency of the MAF unit by enabling
                 the normalization and addition to take place in a
                 single cycle.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Res. Div., Thomas J. Watson Res. Center, Yorktown
                 Heights, NY, USA",
  classification = "B1265B (Logic circuits); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "Circuitry; Floating-point addition; IBM RISC
                 System/6000 floating-point execution unit; Latency;
                 Leading-zero anticipator; Multiply-add-fused;
                 Normalization; Parallel",
  thesaurus =    "Digital arithmetic; IBM computers; Reduced instruction
                 set computing",
}


bibtype: article
filename: fparith.bib
label: Hokenek:1990:SGR
author: E. Hokenek and R. K. Montoye and P. W. Cook
title: Second-Generation RISC Floating Point with Multiply-Add Fused
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 25
number: 5
pages: 1207--1213
month: oct
monthnumber: 10
year: 1990
CODEN: IJSCBC
DOI: https://doi.org/10.1109/4.62143
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
rawauthor: E. Hokenek and R. K. Montoye and P. W. Cook
rawtitle: Second-Generation {RISC} Floating Point with Multiply-Add Fused
abstract:
A 440000-transistor second-generation RISC (reduced instruction set computer) floating-point chip is described. The pipeline latency is only two cycles, and a double-precision result is produced every cycle. System throughput and accuracy are increased by using a floating-point multiply-add-fused unit, which carries out a double-precision accumulate as a two-cycle pipelined execution with only one rounding error. While the cycle time (40 ns) is competitive with other CMOS RISC systems, the floating-point performance stretches to the range of bipolar RISC systems (7.4-13 MFLOPS LINPACK). Leading zero anticipation makes the two-cycle pipeline possible by nearly eliminating the additional postnormalization time, and it allows for reduced overall system latency. Partial decode shifters allow complete time sharing for the multiply and data alignment. Improved design techniques for logarithmic addition and higher order counters for multiplication complete this second-generation RISC floating-point unit design.

keywords:
40 Ns; 7.4 To 13 MFLOPS; Double-precision accumulate; Double-precision result; Floating-point chip; Higher order counters; Logarithmic addition; Multiplication; Multiply-add-fused unit; Partial decode shifters; Pipeline latency; Reduced instruction set computer; RISC; Two-cycle pipelined execution

thesaurus:
CMOS integrated circuits; Microprocessor chips; Pipeline processing; Reduced instruction set computing

rawabstract:
A 440000-transistor second-generation RISC (reduced instruction set computer) floating-point chip is described. The pipeline latency is only two cycles, and a double-precision result is produced every cycle. System throughput and accuracy are increased by using a floating-point multiply-add-fused unit, which carries out a double-precision accumulate as a two-cycle pipelined execution with only one rounding error. While the cycle time (40 ns) is competitive with other CMOS RISC systems, the floating-point performance stretches to the range of bipolar RISC systems (7.4-13 MFLOPS LINPACK). Leading zero anticipation makes the two-cycle pipeline possible by nearly eliminating the additional postnormalization time, and it allows for reduced overall system latency. Partial decode shifters allow complete time sharing for the multiply and data alignment. Improved design techniques for logarithmic addition and higher order counters for multiplication complete this second-generation RISC floating-point unit design.

entry:
@Article{Hokenek:1990:SGR,
  author =       "E. Hokenek and R. K. Montoye and P. W. Cook",
  title =        "Second-Generation {RISC} Floating Point with
                 Multiply-Add Fused",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "25",
  number =       "5",
  pages =        "1207--1213",
  month =        oct,
  year =         "1990",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/4.62143",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 440000-transistor second-generation RISC (reduced
                 instruction set computer) floating-point chip is
                 described. The pipeline latency is only two cycles, and
                 a double-precision result is produced every cycle.
                 System throughput and accuracy are increased by using a
                 floating-point multiply-add-fused unit, which carries
                 out a double-precision accumulate as a two-cycle
                 pipelined execution with only one rounding error. While
                 the cycle time (40 ns) is competitive with other CMOS
                 RISC systems, the floating-point performance stretches
                 to the range of bipolar RISC systems (7.4-13 MFLOPS
                 LINPACK). Leading zero anticipation makes the two-cycle
                 pipeline possible by nearly eliminating the additional
                 postnormalization time, and it allows for reduced
                 overall system latency. Partial decode shifters allow
                 complete time sharing for the multiply and data
                 alignment. Improved design techniques for logarithmic
                 addition and higher order counters for multiplication
                 complete this second-generation RISC floating-point
                 unit design.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "IBM Thomas J. Watson Res. Center, Yorktown Heights,
                 NY, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "40 Ns; 7.4 To 13 MFLOPS; Double-precision accumulate;
                 Double-precision result; Floating-point chip; Higher
                 order counters; Logarithmic addition; Multiplication;
                 Multiply-add-fused unit; Partial decode shifters;
                 Pipeline latency; Reduced instruction set computer;
                 RISC; Two-cycle pipelined execution",
  numericalindex = "Time 4.0E-08 s; Computer speed 7.4E+06 to 1.3E+07
                 FLOPS",
  summary =      "A 440000-transistor second-generation RISC (reduced
                 instruction set computer) floating-point chip is
                 described. The pipeline latency is only two cycles, and
                 a double-precision result is produced every cycle.
                 System throughput and accuracy are increased \ldots{}",
  thesaurus =    "CMOS integrated circuits; Microprocessor chips;
                 Pipeline processing; Reduced instruction set
                 computing",
}


bibtype: article
filename: fparith.bib
label: Hong:1990:DTP
author: S. J. Hong
title: The design of a testable parallel multiplier
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 3
pages: 411--416
month: mar
monthnumber: 3
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.48874
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:00 MDT 2011
bibtimestamp: 2011.07.07 14:20:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=48874
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. J. Hong
rawtitle: The design of a testable parallel multiplier
entry:
@Article{Hong:1990:DTP,
  author =       "S. J. Hong",
  title =        "The design of a testable parallel multiplier",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "3",
  pages =        "411--416",
  month =        mar,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.48874",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=48874",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Horiguchi:1990:FNR
author: Hiroshi Horiguchi
title: Floating-Point Numbers and Real Numbers
journal: j-ADV-SOFT-SCI-TECH
volume: 1
pages: 157--??
year: 1990
ISSN: 1044-7997 OR 10447997
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Advances in software science and technology
acknowledgement: ack-nhfb
rawauthor: Hiroshi Horiguchi
rawtitle: Floating-Point Numbers and Real Numbers
entry:
@Article{Horiguchi:1990:FNR,
  author =       "Hiroshi Horiguchi",
  title =        "Floating-Point Numbers and Real Numbers",
  journal =      j-ADV-SOFT-SCI-TECH,
  volume =       "1",
  number =       "??",
  pages =        "157--??",
  year =         "1990",
  ISSN =         "1044-7997",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Advances in software science and technology",
}


bibtype: techreport
filename: fparith.bib
label: IBM:1990:AXI
author: IBM Corporation
title: ACRITH-XSC: IBM High Accuracy Arithmetic --- Extended Scientific Computation
type: Technical Report
number: GC33-6461-01, SC33-6462-00, SC33-6463-00, SC33-6464-00, SC33-6466-00.
institution: pub-IBM
address: pub-IBM:adr
pages: 157--??
year: 1990
bibdate: Thu Jan 21 17:27:09 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.01.21 17:27:09 ???
TOC: 1. General Information 2. Reference 3. Sample Programs 4. How To Use 5. Syntax Diagrams
acknowledgement: ack-nhfb
rawauthor: {IBM Corporation}
rawtitle: {ACRITH-XSC}: {IBM} High Accuracy Arithmetic --- Extended Scientific Computation
rawTOC: 1. General Information \\ 2. Reference \\ 3. Sample Programs \\ 4. How To Use \\ 5. Syntax Diagrams
entry:
@TechReport{IBM:1990:AXI,
  author =       "{IBM Corporation}",
  title =        "{ACRITH-XSC}: {IBM} High Accuracy Arithmetic ---
                 Extended Scientific Computation",
  type =         "Technical Report",
  number =       "GC33-6461-01, SC33-6462-00, SC33-6463-00,
                 SC33-6464-00, SC33-6466-00.",
  institution =  pub-IBM,
  address =      pub-IBM:adr,
  year =         "1990",
  bibdate =      "Thu Jan 21 17:27:09 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  tableofcontents = "1. General Information \\
                 2. Reference \\
                 3. Sample Programs \\
                 4. How To Use \\
                 5. Syntax Diagrams",
}


bibtype: book
filename: fparith.bib
label: IBM:1990:IRS
editor: Mamata Misra
title: IBM RISC System / 6000 Technology, publication SA23-2619-00
publisher: pub-IBM
address: pub-IBM:adr
pages: 157--??
year: 1990
bibdate: Wed Sep 14 23:02:26 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.14 23:02:26 ???
acknowledgement: ack-nhfb
raweditor: Mamata Misra
rawtitle: {IBM RISC System\slash 6000 Technology, publication SA23-2619-00}
entry:
@Book{IBM:1990:IRS,
  editor =       "Mamata Misra",
  title =        "{IBM RISC System\slash 6000 Technology, publication
                 SA23-2619-00}",
  publisher =    pub-IBM,
  address =      pub-IBM:adr,
  year =         "1990",
  bibdate =      "Wed Sep 14 23:02:26 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Jarvis:1990:ICA
author: P. Jarvis
title: Implementing Cordic Algorithms
journal: j-DDJ
volume: 15
number: 10
pages: 152--158
month: oct
monthnumber: 10
year: 1990
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Thu Sep 1 10:15:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:40 ???
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nj
rawauthor: P. Jarvis
rawtitle: Implementing {Cordic} Algorithms
entry:
@Article{Jarvis:1990:ICA,
  author =       "P. Jarvis",
  title =        "Implementing {Cordic} Algorithms",
  journal =      j-DDJ,
  volume =       "15",
  number =       "10",
  pages =        "152--158",
  month =        oct,
  year =         "1990",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Thu Sep 1 10:15:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Dr. Dobb's Journal of Software Tools",
}


bibtype: inproceedings
filename: fparith.bib
label: Kahan:1990:HCA
author: W. Kahan
title: How Cray's arithmetic hurts scientific computation (and what might be done about it)
crossref: CUG:1990:PSC
pages: 42
day: 14
month: jun
monthnumber: 6
year: 1990
bibdate: Tue Jan 03 18:17:16 2006
bibtimestamp: 2006.01.03 18:17:16 ???
note: Manuscript prepared for the Cray User Group meeting in Toronto, Canada, April 10, 1990.
acknowledgement: ack-nhfb
rawauthor: W. Kahan
rawnote: Manuscript prepared for the Cray User Group meeting in Toronto, Canada, April 10, 1990.
rawtitle: How {Cray}'s arithmetic hurts scientific computation (and what might be done about it)
bibsource:
https://www.math.utah.edu/pub/bibnet/subjects/acc-stab-num-alg-2ed.bib; https://www.math.utah.edu/pub/bibnet/subjects/acc-stab-num-alg.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://754r.ucbtest.org/issues/cray-hurts-uk.pdf; http://754r.ucbtest.org/issues/cray-hurts-ut.pdf; http://754r.ucbtest.org/issues/cray-hurts.pdf

entry:
@InProceedings{Kahan:1990:HCA,
  author =       "W. Kahan",
  title =        "How {Cray}'s arithmetic hurts scientific computation
                 (and what might be done about it)",
  crossref =     "CUG:1990:PSC",
  pages =        "42",
  day =          "14",
  month =        jun,
  year =         "1990",
  bibdate =      "Tue Jan 03 18:17:16 2006",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/subjects/acc-stab-num-alg-2ed.bib;
                 https://www.math.utah.edu/pub/bibnet/subjects/acc-stab-num-alg.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Manuscript prepared for the Cray User Group meeting in
                 Toronto, Canada, April 10, 1990.",
  URL =          "http://754r.ucbtest.org/issues/cray-hurts-uk.pdf;
                 http://754r.ucbtest.org/issues/cray-hurts-ut.pdf;
                 http://754r.ucbtest.org/issues/cray-hurts.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Kahan:1990:PCA
author: William Kahan
title: Paradoxes in concepts of accuracy
publisher: Carnegie Mellon University
address: Pittsburgh, PA, USA
pages: 42
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
note: 1 videocassette (60 min.)
series: Distinguished lecture series
keywords: Computer arithmetic.; Floating-point arithmetic --- Data processing.
acknowledgement: ack-nhfb
rawauthor: William Kahan
rawnote: 1 videocassette (60 min.)
rawtitle: Paradoxes in concepts of accuracy
remark:
Lecture given February 15, 1990. VHS format. Lecturer, William Kahan. Paradoxes expose errors in conventional wisdom about floating-point arithmetic.

entry:
@Misc{Kahan:1990:PCA,
  author =       "William Kahan",
  title =        "Paradoxes in concepts of accuracy",
  publisher =    "Carnegie Mellon University",
  address =      "Pittsburgh, PA, USA",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "1 videocassette (60 min.)",
  series =       "Distinguished lecture series",
  acknowledgement = ack-nhfb,
  keywords =     "Computer arithmetic.; Floating-point arithmetic ---
                 Data processing.",
  remark =       "Lecture given February 15, 1990. VHS format. Lecturer,
                 William Kahan. Paradoxes expose errors in conventional
                 wisdom about floating-point arithmetic.",
}


bibtype: article
filename: fparith.bib
label: Kalbasi:1990:CYT
author: K. Kalbasi
title: Can you trust your computer?
journal: j-IEEE-POT
volume: 9
number: 2
pages: 15--18
month: apr
monthnumber: 4
year: 1990
CODEN: IEPTDF
ISSN: 0278-6648 (print), 1558-1772 (electronic) OR 02786648 (print), 15581772 (electronic)
ISSNL: 0278-6648 OR 02786648
bibdate: Wed Sep 14 19:14:21 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.14 19:14:21 ???
fjournal: IEEE Potentials
acknowledgement: ack-nj
rawauthor: K. Kalbasi
rawtitle: Can you trust your computer?
entry:
@Article{Kalbasi:1990:CYT,
  author =       "K. Kalbasi",
  title =        "Can you trust your computer?",
  journal =      j-IEEE-POT,
  volume =       "9",
  number =       "2",
  pages =        "15--18",
  month =        apr,
  year =         "1990",
  CODEN =        "IEPTDF",
  ISSN =         "0278-6648 (print), 1558-1772 (electronic)",
  ISSN-L =       "0278-6648",
  bibdate =      "Wed Sep 14 19:14:21 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "IEEE Potentials",
}


bibtype: article
filename: fparith.bib
label: Katsuno:1990:BFP
author: A. Katsuno and H. Takahashi and H. Kubosawa and T. Sato and A. Suga and G. Goto
title: A 64-bit Floating-Point Processing Unit with a Horizontal Instruction Code for Parallel Operations
crossref: IEEE:1990:PII
pages: 347--350
year: 1990
bibdate: Wed Sep 7 22:32:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:42 ???
acknowledgement: ack-nj
rawauthor: A. Katsuno and H. Takahashi and H. Kubosawa and T. Sato and A. Suga and G. Goto
rawtitle: A 64-bit Floating-Point Processing Unit with a Horizontal Instruction Code for Parallel Operations
entry:
@Article{Katsuno:1990:BFP,
  author =       "A. Katsuno and H. Takahashi and H. Kubosawa and T.
                 Sato and A. Suga and G. Goto",
  title =        "A 64-bit Floating-Point Processing Unit with a
                 Horizontal Instruction Code for Parallel Operations",
  crossref =     "IEEE:1990:PII",
  pages =        "347--350",
  year =         "1990",
  bibdate =      "Wed Sep 7 22:32:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Khan:1990:FPA
author: A. Khan
title: Floating point architecture and implementation
crossref: Wescon:1990:WCR
pages: 205--213
year: 1990
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
thesaurus: Computer architecture; Digital arithmetic
rawauthor: A. Khan
rawtitle: Floating point architecture and implementation
abstract:
Analyzes various requirements of efficient floating point architecture and implementation. The basic elements of architecture such as latency, repeat rate and issue rate are defined. Handling various exceptions in a precise manner is described. Finally, a description of one example (MIPS R3010) is provided. (0 Refs.)

keywords:
Elements of architecture; Floating point architecture; Issue rate; Latency; MIPS R3010; Repeat rate; Requirements

rawabstract:
Analyzes various requirements of efficient floating point architecture and implementation. The basic elements of architecture such as latency, repeat rate and issue rate are defined. Handling various exceptions in a precise manner is described. Finally, a description of one example (MIPS R3010) is provided. (0 Refs.)

entry:
@InProceedings{Khan:1990:FPA,
  author =       "A. Khan",
  title =        "Floating point architecture and implementation",
  crossref =     "Wescon:1990:WCR",
  pages =        "205--213",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Analyzes various requirements of efficient floating
                 point architecture and implementation. The basic
                 elements of architecture such as latency, repeat rate
                 and issue rate are defined. Handling various exceptions
                 in a precise manner is described. Finally, a
                 description of one example (MIPS R3010) is provided. (0
                 Refs.)",
  acknowledgement = ack-nhfb,
  availability = "Western Periodicals Co., 13000 Rayner Street, North
                 Hollywood, CA 91605, USA",
  classification = "C5130 (Microprocessor chips); C5220 (Computer
                 architecture); C5230 (Digital arithmetic methods)",
  keywords =     "Elements of architecture; Floating point architecture;
                 Issue rate; Latency; MIPS R3010; Repeat rate;
                 Requirements",
  thesaurus =    "Computer architecture; Digital arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Kiernan:1990:FAE
author: J. M. Kiernan and T. B. Blachowiak
title: Fast, Accurate Elementary Functions For the Cray Y-MP Computer
crossref: CUG:1990:PSC
pages: 243--252
year: 1990
bibdate: Thu Sep 1 10:15:30 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:30 ???
acknowledgement: ack-nj
rawauthor: J. M. Kiernan and T. B. Blachowiak
rawtitle: Fast, Accurate Elementary Functions For the {Cray Y-MP} Computer
entry:
@InProceedings{Kiernan:1990:FAE,
  author =       "J. M. Kiernan and T. B. Blachowiak",
  title =        "Fast, Accurate Elementary Functions For the {Cray
                 Y-MP} Computer",
  crossref =     "CUG:1990:PSC",
  pages =        "243--252",
  year =         "1990",
  bibdate =      "Thu Sep 1 10:15:30 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: incollection
filename: fparith.bib
label: Knuth:1990:SPW
author: Donald E. Knuth
title: A Simple Program Whose Proof Isn't
crossref: Feijen:1990:BOB
chapter: 27
pages: 233--242
year: 1990
bibdate: Mon Feb 03 07:07:55 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.02.03 07:07:55 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Donald E. Knuth
rawtitle: A Simple Program Whose Proof Isn't
note:
Reprinted in cite [Chapter 11]Knuth:2010:SPD. This paper discusses the algorithm used in TeX for converting between decimal and scaled fixed-point binary values, and for guaranteeing a minimum number of digits in the decimal representation. See also cite Clinger:1990:HRF,Clinger:2004:RHR for decimal to binary conversion, cite Steele:1990:HPF,Steele:2004:RHP for binary to decimal conversion, and cite Gries:1990:BDO for an alternate proof of Knuth's algorithm.

rawnote:
Reprinted in \cite[Chapter 11]{Knuth:2010:SPD}. This paper discusses the algorithm used in {\TeX} for converting between decimal and scaled fixed-point binary values, and for guaranteeing a minimum number of digits in the decimal representation. See also \cite{Clinger:1990:HRF,Clinger:2004:RHR} for decimal to binary conversion, \cite{Steele:1990:HPF,Steele:2004:RHP} for binary to decimal conversion, and \cite{Gries:1990:BDO} for an alternate proof of Knuth's algorithm.

entry:
@InCollection{Knuth:1990:SPW,
  author =       "Donald E. Knuth",
  title =        "A Simple Program Whose Proof Isn't",
  crossref =     "Feijen:1990:BOB",
  chapter =      "27",
  pages =        "233--242",
  year =         "1990",
  bibdate =      "Mon Feb 03 07:07:55 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Reprinted in \cite[Chapter 11]{Knuth:2010:SPD}. This
                 paper discusses the algorithm used in {\TeX} for
                 converting between decimal and scaled fixed-point
                 binary values, and for guaranteeing a minimum number of
                 digits in the decimal representation. See also
                 \cite{Clinger:1990:HRF,Clinger:2004:RHR} for decimal to
                 binary conversion,
                 \cite{Steele:1990:HPF,Steele:2004:RHP} for binary to
                 decimal conversion, and \cite{Gries:1990:BDO} for an
                 alternate proof of Knuth's algorithm.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Koren:1990:EEF
author: I. Koren and O. Zinaty
title: Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations
journal: j-IEEE-TRANS-COMPUT
volume: C-39
number: 8
pages: 1030--1037
month: aug
monthnumber: 8
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57042
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Sep 1 10:15:30 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:30 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nj
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: I. Koren and O. Zinaty
rawtitle: Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations
entry:
@Article{Koren:1990:EEF,
  author =       "I. Koren and O. Zinaty",
  title =        "Evaluating Elementary Functions in a Numerical
                 Coprocessor Based on Rational Approximations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "C-39",
  number =       "8",
  pages =        "1030--1037",
  month =        aug,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57042",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Sep 1 10:15:30 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Kornerup:1990:ARB
author: Peter Kornerup and David W. Matula
title: An algorithm for redundant binary bit-pipelined rational arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 8
pages: 1106--1115
month: aug
monthnumber: 8
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57048
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:04 MDT 2011
bibtimestamp: 2011.07.07 14:20:04 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57048
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Peter Kornerup and David W. Matula
rawtitle: An algorithm for redundant binary bit-pipelined rational arithmetic
abstract:
The authors introduce a redundant binary representation of the rationals and an associated algorithm for computing the sum, difference, product, quotient, and other useful functions of two rational operands, using this representation. The algorithm extends R.W. Gosper's (1972) partial quotient arithmetic algorithm and allows the design of an online arithmetic unit with computations granularized at the signed bit level. Each input or output port can be independently set to receive/produce operands/result in either binary radix or the binary rational representation. The authors investigate by simulation the interconnection of several such units for the parallel computation of more complicated expressions in a tree-pipelined manner, with particular regard to measuring individual and compounded online delays

rawabstract:
The authors introduce a redundant binary representation of the rationals and an associated algorithm for computing the sum, difference, product, quotient, and other useful functions of two rational operands, using this representation. The algorithm extends R.W. Gosper's (1972) partial quotient arithmetic algorithm and allows the design of an online arithmetic unit with computations granularized at the signed bit level. Each input or output port can be independently set to receive/produce operands/result in either binary radix or the binary rational representation. The authors investigate by simulation the interconnection of several such units for the parallel computation of more complicated expressions in a tree-pipelined manner, with particular regard to measuring individual and compounded online delays

entry:
@Article{Kornerup:1990:ARB,
  author =       "Peter Kornerup and David W. Matula",
  title =        "An algorithm for redundant binary bit-pipelined
                 rational arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "8",
  pages =        "1106--1115",
  month =        aug,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57048",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:04 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57048",
  abstract =     "The authors introduce a redundant binary
                 representation of the rationals and an associated
                 algorithm for computing the sum, difference, product,
                 quotient, and other useful functions of two rational
                 operands, using this representation. The algorithm
                 extends R.W. Gosper's (1972) partial quotient
                 arithmetic algorithm and allows the design of an online
                 arithmetic unit with computations granularized at the
                 signed bit level. Each input or output port can be
                 independently set to receive/produce operands/result in
                 either binary radix or the binary rational
                 representation. The authors investigate by simulation
                 the interconnection of several such units for the
                 parallel computation of more complicated expressions in
                 a tree-pipelined manner, with particular regard to
                 measuring individual and compounded online delays",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Laakso:1990:RFP
author: T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo
booktitle: IEEE International Conference on Systems Engineering, 1990
title: Reduction of floating-point roundoff noise in recursive digital filters with error feedback
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 244--247
year: 1990
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo
rawbooktitle: {IEEE} International Conference on Systems Engineering, 1990
rawtitle: Reduction of floating-point roundoff noise in recursive digital filters with error feedback
entry:
@InProceedings{Laakso:1990:RFP,
  author =       "T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo",
  booktitle =    "{IEEE} International Conference on Systems
                 Engineering, 1990",
  title =        "Reduction of floating-point roundoff noise in
                 recursive digital filters with error feedback",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "244--247",
  year =         "1990",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The reduction of roundoff noise in floating-point
                 recursive digital filters by means of error feedback is
                 discussed. Optimal (minimum-noise) error feedback is
                 formulated, and it is shown to be different from the
                 optimal solution in the fixed-point \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Lee:1990:OPC
author: Vernon A. Lee, Jr. and Hans-J. Boehm
title: Optimizing programs over the constructive reals
journal: j-SIGPLAN
volume: 25
number: 6
pages: 102--111
month: jun
monthnumber: 6
year: 1990
CODEN: SINODQ
DOI: https://doi.org/10.1145/93542.93558
ISBN: 0-89791-364-7 OR 0897913647
ISBN13: 978-0-89791-364-5 OR 9780897913645
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:15:53 MST 2003
bibtimestamp: 2003.12.14 09:15:53 MST
URL: http://www.acm.org:80/pubs/citations/proceedings/pldi/93542/p102-lee/
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Rice University
affiliationaddress: Houston, TX, USA
annote: Published as part of the Proceedings of PLDI'90.
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
journalabr: SIGPLAN Not
thesaurus: Data structures; Mathematics computing; Programming
rawauthor: Vernon A. {Lee, Jr.} and Hans-J. Boehm
rawtitle: Optimizing programs over the constructive reals
bibsource:
Compendex database; http://portal.acm.org/; http://www.acm.org/pubs/contents/proceedings/pldi/93542/index.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
The constructive reals provide programmers with a useful mechanism for prototyping numerical programs, and for experimenting with numerical algorithms. Unfortunately, the performance of current implementations is inadequate for some potential applications. In particular, these implementations tend to be space inefficient, in that they essentially require a complete computation history to be maintained. Some numerical analysts propose that the programmer instead be provided with variable precision interval arithmetic, and then be required to write code to restart a computation when the intervals become too inaccurate. Though this model is no doubt appropriate at times, it is not an adequate replacement for exact arithmetic. The correct transformation from a program operating on the constructive reals to a reasonable program using iterated interval arithmetic can be nontrivial and error prone. Here we present a technique based on program slicing to both automate this process and reduce the amount of reexecution. Thus the programmer is still free to use the simpler abstraction of exact real arithmetic, but we can provide a more efficient interval arithmetic based implementation. Some preliminary empirical results are presented.

keywords:
algorithms; Computer Operating Systems; Computer Programming Languages --- Design; Constructive reals; Efficient interval arithmetic based implementation; Empirical results; Exact real arithmetic; Numerical algorithms; Numerical analysts; Numerical programs; Optimizing Compilers; performance; Performance; Program Compilers; Program slicing; Reexecution; Variable precision interval arithmetic

subject:
bf D.3.4 Software, PROGRAMMING LANGUAGES, Processors, Optimization. bf F.2.1 Theory of Computation, ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms and Problems. bf G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic. bf F.2.2 Theory of Computation, ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY, Nonnumerical Algorithms and Problems, Computations on discrete structures.

rawabstract:
The constructive reals provide programmers with a useful mechanism for prototyping numerical programs, and for experimenting with numerical algorithms. Unfortunately, the performance of current implementations is inadequate for some potential applications. In particular, these implementations tend to be space inefficient, in that they essentially require a complete computation history to be maintained. Some numerical analysts propose that the programmer instead be provided with variable precision interval arithmetic, and then be required to write code to restart a computation when the intervals become too inaccurate. Though this model is no doubt appropriate at times, it is not an adequate replacement for exact arithmetic. The correct transformation from a program operating on the constructive reals to a reasonable program using iterated interval arithmetic can be nontrivial and error prone. Here we present a technique based on program slicing to both automate this process and reduce the amount of reexecution. Thus the programmer is still free to use the simpler abstraction of exact real arithmetic, but we can provide a more efficient interval arithmetic based implementation. Some preliminary empirical results are presented.

entry:
@Article{Lee:1990:OPC,
  author =       "Vernon A. {Lee, Jr.} and Hans-J. Boehm",
  title =        "Optimizing programs over the constructive reals",
  journal =      j-SIGPLAN,
  volume =       "25",
  number =       "6",
  pages =        "102--111",
  month =        jun,
  year =         "1990",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/93542.93558",
  ISBN =         "0-89791-364-7",
  ISBN-13 =      "978-0-89791-364-5",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:15:53 MST 2003",
  bibsource =    "Compendex database; http://portal.acm.org/;
                 http://www.acm.org/pubs/contents/proceedings/pldi/93542/index.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/pldi/93542/p102-lee/",
  abstract =     "The constructive reals provide programmers with a
                 useful mechanism for prototyping numerical programs,
                 and for experimenting with numerical algorithms.
                 Unfortunately, the performance of current
                 implementations is inadequate for some potential
                 applications. In particular, these implementations tend
                 to be space inefficient, in that they essentially
                 require a complete computation history to be
                 maintained. Some numerical analysts propose that the
                 programmer instead be provided with variable precision
                 interval arithmetic, and then be required to write code
                 to restart a computation when the intervals become too
                 inaccurate. Though this model is no doubt appropriate
                 at times, it is not an adequate replacement for exact
                 arithmetic. The correct transformation from a program
                 operating on the constructive reals to a reasonable
                 program using iterated interval arithmetic can be
                 nontrivial and error prone. Here we present a technique
                 based on program slicing to both automate this process
                 and reduce the amount of reexecution. Thus the
                 programmer is still free to use the simpler abstraction
                 of exact real arithmetic, but we can provide a more
                 efficient interval arithmetic based implementation.
                 Some preliminary empirical results are presented.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Rice University",
  affiliationaddress = "Houston, TX, USA",
  annote =       "Published as part of the Proceedings of PLDI'90.",
  classification = "722; 723; C6110 (Systems analysis and programming);
                 C6120 (File organisation); C7310 (Mathematics)",
  confdate =     "20-22 June 1990",
  conference =   "Proceedings of the ACM SIGPLAN '90 Conference on
                 Programming Language Design and Implementation",
  conferenceyear = "1990",
  conflocation = "White Plains, NY, USA",
  confsponsor =  "ACM",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  journalabr =   "SIGPLAN Not",
  keywords =     "algorithms; Computer Operating Systems; Computer
                 Programming Languages --- Design; Constructive reals;
                 Efficient interval arithmetic based implementation;
                 Empirical results; Exact real arithmetic; Numerical
                 algorithms; Numerical analysts; Numerical programs;
                 Optimizing Compilers; performance; Performance; Program
                 Compilers; Program slicing; Reexecution; Variable
                 precision interval arithmetic",
  meetingaddress = "White Plains, NY, USA",
  meetingdate =  "Jun 20--22 1990",
  meetingdate2 = "06/20--22/90",
  sponsor =      "Assoc for Computing Machinery, Special Interest Group
                 on Programming Languages",
  subject =      "{\bf D.3.4} Software, PROGRAMMING LANGUAGES,
                 Processors, Optimization. {\bf F.2.1} Theory of
                 Computation, ANALYSIS OF ALGORITHMS AND PROBLEM
                 COMPLEXITY, Numerical Algorithms and Problems. {\bf
                 G.1.0} Mathematics of Computing, NUMERICAL ANALYSIS,
                 General, Computer arithmetic. {\bf F.2.2} Theory of
                 Computation, ANALYSIS OF ALGORITHMS AND PROBLEM
                 COMPLEXITY, Nonnumerical Algorithms and Problems,
                 Computations on discrete structures.",
  thesaurus =    "Data structures; Mathematics computing; Programming",
}


bibtype: article
filename: fparith.bib
label: Ling:1990:AIM
author: H. Ling
title: An approach to implementing multiplication with small tables
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 5
pages: 717--718
month: may
monthnumber: 5
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.53588
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:02 MDT 2011
bibtimestamp: 2011.07.07 14:20:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=53588
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Ling
rawtitle: An approach to implementing multiplication with small tables
entry:
@Article{Ling:1990:AIM,
  author =       "H. Ling",
  title =        "An approach to implementing multiplication with small
                 tables",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "5",
  pages =        "717--718",
  month =        may,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.53588",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=53588",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Lozier:1990:CPL
author: D. W. Lozier and F. W. J. Olver
title: Closure and Precision in Level-Index Arithmetic
journal: j-SIAM-J-NUMER-ANAL
volume: 27
number: 5
pages: 1295--1304
month: oct
monthnumber: 10
year: 1990
CODEN: SJNAAM
ISSN: 0036-1429 (print), 1095-7170 (electronic) OR 00361429 (print), 10957170 (electronic)
ISSNL: 0036-1429 OR 00361429
MRclass: 65-04 (65G05)
MRnumber: 91f:65002
bibdate: Fri Oct 16 06:57:22 MDT 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; JSTOR database
bibtimestamp: 1998.10.16 06:57:22 MDT
fjournal: SIAM Journal on Numerical Analysis
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sinum
rawauthor: D. W. Lozier and F. W. J. Olver
rawtitle: Closure and Precision in Level-Index Arithmetic
entry:
@Article{Lozier:1990:CPL,
  author =       "D. W. Lozier and F. W. J. Olver",
  title =        "Closure and Precision in Level-Index Arithmetic",
  journal =      j-SIAM-J-NUMER-ANAL,
  volume =       "27",
  number =       "5",
  pages =        "1295--1304",
  month =        oct,
  year =         "1990",
  CODEN =        "SJNAAM",
  ISSN =         "0036-1429 (print), 1095-7170 (electronic)",
  ISSN-L =       "0036-1429",
  MRclass =      "65-04 (65G05)",
  MRnumber =     "91f:65002",
  bibdate =      "Fri Oct 16 06:57:22 MDT 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 JSTOR database",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Numerical Analysis",
  journal-URL =  "http://epubs.siam.org/sinum",
}


bibtype: article
filename: fparith.bib
label: MacDonald:1990:IFP
author: Tom MacDonald
title: IEEE Floating-Point Arithmetic and C
journal: j-JCLT
volume: 2
number: 2
pages: 102--112
month: sep
monthnumber: 9
year: 1990
ISSN: 1042-5721 OR 10425721
bibdate: Thu Nov 8 14:50:33 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 14:50:33 ???
fjournal: The Journal of C Language Translation
acknowledgement: ack-nj
rawauthor: Tom MacDonald
rawtitle: {IEEE} Floating-Point Arithmetic and {C}
entry:
@Article{MacDonald:1990:IFP,
  author =       "Tom MacDonald",
  title =        "{IEEE} Floating-Point Arithmetic and {C}",
  journal =      j-JCLT,
  volume =       "2",
  number =       "2",
  pages =        "102--112",
  month =        sep,
  year =         "1990",
  ISSN =         "1042-5721",
  bibdate =      "Thu Nov 8 14:50:33 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "The Journal of {C} Language Translation",
}


bibtype: article
filename: fparith.bib
label: Mandelbaum:1990:SMD
author: D. M. Mandelbaum
title: A systematic method for division with high average bit skipping
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 1
pages: 127--130
month: jan
monthnumber: 1
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.46287
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:19:59 MDT 2011
bibtimestamp: 2011.07.07 14:19:59 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=46287
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. M. Mandelbaum
rawtitle: A systematic method for division with high average bit skipping
entry:
@Article{Mandelbaum:1990:SMD,
  author =       "D. M. Mandelbaum",
  title =        "A systematic method for division with high average bit
                 skipping",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "1",
  pages =        "127--130",
  month =        jan,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.46287",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:19:59 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=46287",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: phdthesis
filename: fparith.bib
label: MangaEbongue:1990:PBV
author: Charles Manga Ebongue
type: These Doctoral
school: Sciences Appliquees, Universite Paris 6
address: Paris, France
pages: 127--130
year: 1990
bibdate: Thu May 09 10:03:41 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 10:03:41 ???
note: Sous la direction de Alain Greiner.
language: French
acknowledgement: ack-nhfb
rawauthor: Charles {Manga Ebongue}
rawnote: Sous la direction de Alain Greiner.
title:
Processeur 32 Bits en Virgule Flottante: Techniques de Validation Fonctionnelle, Electrique et Test a la Conception. (French) [32-bit Floating-Point Processor: Techniques of Functional and Electrical Validation and Test in the Design]

abstract:
Cette these developpe deux aspects de la conception des circuits integres: (1) le premier aspect correspond a la methodologie d'implantation du processeur de calcul en virgule flottante developpe au laboratoire MASI par l'equipe de Cao & VLSI de l'Universite Pierre et Marie Curie, (2) le deuxieme aspect presente les travaux concernant une methodologie de test a la conception conduisant aussi bien a la validation fonctionnelle et electrique au cours de la conception qu'a la testabilite apres fabrication. Le premier aspect a des implications a differents niveaux: (1) au niveau assemblage par l'introduction d'une methodologie de conception specifique au circuit, (2) au niveau electrique pour le choix et la conception d'une bibliotheque de cellules standards qui tient compte des caracteristiques dynamiques des signaux sur chaque nud du circuit. Le deuxieme aspect a pour resultat l'introduction d'une technique originale de recherche de vecteurs de test. De meme, la validation fonctionnelle de ce circuit sera invoquee en resolvant les principaux problemes de coherence entre les masques dessines et la liste des interconnexions.

rawabstract:
Cette th{\`e}se d{\'e}veloppe deux aspects de la conception des circuits integr{\'e}s: (1) le premier aspect correspond {\`a} la m{\'e}thodologie d'implantation du processeur de calcul en virgule flottante d{\'e}velopp{\'e} au laboratoire MASI par l'{\'e}quipe de Cao \& VLSI de l'Universit{\'e} Pierre et Marie Curie, (2) le deuxi{\'e}me aspect pr{\'e}sente les travaux concernant une m{\'e}thodologie de test {\`a} la conception conduisant aussi bien {\`a} la validation fonctionnelle et {\'e}lectrique au cours de la conception qu'{\`a} la testabilit{\'e} apr{\`e}s fabrication. Le premier aspect a des implications {\`a} diff{\'e}rents niveaux: (1) au niveau assemblage par l'introduction d'une m{\'e}thodologie de conception sp{\'e}cifique au circuit, (2) au niveau {\'e}lectrique pour le choix et la conception d'une biblioth{\`e}que de cellules standards qui tient compte des caract{\'e}ristiques dynamiques des signaux sur chaque nud du circuit. Le deuxi{\`e}me aspect a pour r{\'e}sultat l'introduction d'une technique originale de recherche de vecteurs de test. De m{\^e}me, la validation fonctionnelle de ce circuit sera invoqu{\^e}e en r{\^e}solvant les principaux probl{\`e}mes de coh{\'e}rence entre les masques d{\'e}ssin{\'e}s et la liste des interconnexions.

rawtitle:
Processeur 32 Bits en Virgule Flottante: Techniques de Validation Fonctionnelle, {{\'E}}lectrique et Test {\`a} la Conception. ({French}) [32-bit Floating-Point Processor: Techniques of Functional and Electrical Validation and Test in the Design]

entry:
@PhdThesis{MangaEbongue:1990:PBV,
  author =       "Charles {Manga Ebongue}",
  title =        "Processeur 32 Bits en Virgule Flottante: Techniques de
                 Validation Fonctionnelle, {{\'E}}lectrique et Test
                 {\`a} la Conception. ({French}) [32-bit Floating-Point
                 Processor: Techniques of Functional and Electrical
                 Validation and Test in the Design]",
  type =         "Th{\`e}se Doctoral",
  school =       "Sciences Appliqu{\'e}es, Universit{\'e} Paris 6",
  address =      "Paris, France",
  year =         "1990",
  bibdate =      "Thu May 09 10:03:41 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Sous la direction de Alain Greiner.",
  abstract =     "Cette th{\`e}se d{\'e}veloppe deux aspects de la
                 conception des circuits integr{\'e}s: (1) le premier
                 aspect correspond {\`a} la m{\'e}thodologie
                 d'implantation du processeur de calcul en virgule
                 flottante d{\'e}velopp{\'e} au laboratoire MASI par
                 l'{\'e}quipe de Cao \& VLSI de l'Universit{\'e} Pierre
                 et Marie Curie, (2) le deuxi{\'e}me aspect pr{\'e}sente
                 les travaux concernant une m{\'e}thodologie de test
                 {\`a} la conception conduisant aussi bien {\`a} la
                 validation fonctionnelle et {\'e}lectrique au cours de
                 la conception qu'{\`a} la testabilit{\'e} apr{\`e}s
                 fabrication. Le premier aspect a des implications {\`a}
                 diff{\'e}rents niveaux: (1) au niveau assemblage par
                 l'introduction d'une m{\'e}thodologie de conception
                 sp{\'e}cifique au circuit, (2) au niveau {\'e}lectrique
                 pour le choix et la conception d'une biblioth{\`e}que
                 de cellules standards qui tient compte des
                 caract{\'e}ristiques dynamiques des signaux sur chaque
                 nud du circuit. Le deuxi{\`e}me aspect a pour
                 r{\'e}sultat l'introduction d'une technique originale
                 de recherche de vecteurs de test. De m{\^e}me, la
                 validation fonctionnelle de ce circuit sera
                 invoqu{\^e}e en r{\^e}solvant les principaux
                 probl{\`e}mes de coh{\'e}rence entre les masques
                 d{\'e}ssin{\'e}s et la liste des interconnexions.",
  acknowledgement = ack-nhfb,
  language =     "French",
}


bibtype: book
filename: fparith.bib
label: Mar:1990:DSP
editor: Amy Mar
title: Digital signal processing applications using the ADSP-2100 family
publisher: pub-PH
address: pub-PH:adr
pages: xvi + 611
year: 1990
ISBN: 0-13-212978-7 OR 0132129787
ISBN13: 978-0-13-212978-7 OR 9780132129787
LCCN: TK5102.5 .D44824 1990
bibdate: Sat Jan 15 05:58:58 MST 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2005.01.15 05:58:58 MST
remark: System requirements for computer disks: IBM PC; PC-DOS 3.0.
subject: Signal processing; Digital techniques; Microprocessors
acknowledgement: ack-nhfb
raweditor: Amy Mar
rawtitle: Digital signal processing applications using the {ADSP-2100} family
entry:
@Book{Mar:1990:DSP,
  editor =       "Amy Mar",
  title =        "Digital signal processing applications using the
                 {ADSP-2100} family",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xvi + 611",
  year =         "1990",
  ISBN =         "0-13-212978-7",
  ISBN-13 =      "978-0-13-212978-7",
  LCCN =         "TK5102.5 .D44824 1990",
  bibdate =      "Sat Jan 15 05:58:58 MST 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  acknowledgement = ack-nhfb,
  remark =       "System requirements for computer disks: IBM PC; PC-DOS
                 3.0.",
  subject =      "Signal processing; Digital techniques;
                 Microprocessors",
}


bibtype: article
filename: fparith.bib
label: Margulis:1990:IMI
author: N. Margulis
title: i860 microprocessor internal architecture
journal: j-MICROPROC-MICROSYS
volume: 14
number: 2
pages: 89--96
month: mar
monthnumber: 3
year: 1990
CODEN: MIMID5
ISSN: 0141-9331 (print), 1872-9436 (electronic) OR 01419331 (print), 18729436 (electronic)
ISSNL: 0141-9331 OR 01419331
bibdate: Wed Sep 7 22:32:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:42 ???
fjournal: Microprocessors and Microsystems
acknowledgement: ack-nj
rawauthor: N. Margulis
rawtitle: i860 microprocessor internal architecture
entry:
@Article{Margulis:1990:IMI,
  author =       "N. Margulis",
  title =        "i860 microprocessor internal architecture",
  journal =      j-MICROPROC-MICROSYS,
  volume =       "14",
  number =       "2",
  pages =        "89--96",
  month =        mar,
  year =         "1990",
  CODEN =        "MIMID5",
  ISSN =         "0141-9331 (print), 1872-9436 (electronic)",
  ISSN-L =       "0141-9331",
  bibdate =      "Wed Sep 7 22:32:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Microprocessors and Microsystems",
}


bibtype: article
filename: fparith.bib
label: Markstein:1990:CEF
author: P. W. Markstein
title: Computation of elementary functions on the IBM RISC System / 6000 processor
journal: j-IBM-JRD
volume: 34
number: 1
pages: 111--119
month: jan
monthnumber: 1
year: 1990
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
MRclass: 65-04 (65D20)
MRnumber: 1 057 659
bibdate: Sat Jan 11 17:44:01 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.01.11 17:44:01 MST
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: IBM Res. Div., Austin, TX, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
thesaurus: Digital arithmetic; IBM computers; Reduced instruction set computing
rawauthor: P. W. Markstein
rawtitle: Computation of elementary functions on the {IBM RISC System\slash 6000} processor
abstract:
The additional speed and precision of the IBM RISC System / 6000 floating-point unit have motivated reexamination of algorithms to perform division, square root, and the elementary functions. New results are obtained which avoid the necessity of doing special testing to get the last bit rounded correctly in accordance with all of the IEEE rounding modes in the case of division and square root. For the elementary function library, a technique is described for always getting the last bit rounded correctly in the selected IEEE rounding mode.

keywords:
correct rounding; Division; Elementary functions; Floating-point unit; IBM RISC System / 6000 processor; IEEE rounding modes; IEEE rounding modes, IBM RISC System/6000 processor; Square root

rawabstract:
The additional speed and precision of the IBM RISC System\slash 6000 floating-point unit have motivated reexamination of algorithms to perform division, square root, and the elementary functions. New results are obtained which avoid the necessity of doing special testing to get the last bit rounded correctly in accordance with all of the IEEE rounding modes in the case of division and square root. For the elementary function library, a technique is described for always getting the last bit rounded correctly in the selected IEEE rounding mode.

entry:
@Article{Markstein:1990:CEF,
  author =       "P. W. Markstein",
  title =        "Computation of elementary functions on the {IBM RISC
                 System\slash 6000} processor",
  journal =      j-IBM-JRD,
  volume =       "34",
  number =       "1",
  pages =        "111--119",
  month =        jan,
  year =         "1990",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  MRclass =      "65-04 (65D20)",
  MRnumber =     "1 057 659",
  bibdate =      "Sat Jan 11 17:44:01 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The additional speed and precision of the IBM RISC
                 System\slash 6000 floating-point unit have motivated
                 reexamination of algorithms to perform division, square
                 root, and the elementary functions. New results are
                 obtained which avoid the necessity of doing special
                 testing to get the last bit rounded correctly in
                 accordance with all of the IEEE rounding modes in the
                 case of division and square root. For the elementary
                 function library, a technique is described for always
                 getting the last bit rounded correctly in the selected
                 IEEE rounding mode.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Res. Div., Austin, TX, USA",
  classification = "C5230 (Digital arithmetic methods)",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "correct rounding; Division; Elementary functions;
                 Floating-point unit; IBM RISC System\slash 6000
                 processor; IEEE rounding modes; IEEE rounding modes,
                 IBM RISC System/6000 processor; Square root",
  thesaurus =    "Digital arithmetic; IBM computers; Reduced instruction
                 set computing",
}


bibtype: inproceedings
filename: fparith.bib
label: Matula:1990:HPD
author: D. Matula
title: Highly parallel divide and square root algorithms for a new generation floating point processor
crossref: Ullrich:1990:CCA
pages: ??--??
year: 1990
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
acknowledgement: ack-sfo
rawauthor: D. Matula
rawtitle: Highly parallel divide and square root algorithms for a new generation floating point processor
entry:
@InProceedings{Matula:1990:HPD,
  author =       "D. Matula",
  title =        "Highly parallel divide and square root algorithms for
                 a new generation floating point processor",
  crossref =     "Ullrich:1990:CCA",
  pages =        "??--??",
  year =         "1990",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: McCloud:1990:FPU
author: S. McCloud and D. Anderson and C. DeWitt and C. Hinds and Y. W. Ho and D. Marquette and E. Quintana
title: A Floating Point Unit for the 68040
crossref: IEEE:1990:PII
pages: 187--190
year: 1990
bibdate: Wed Sep 7 22:32:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:42 ???
acknowledgement: ack-nj
rawauthor: S. McCloud and D. Anderson and C. DeWitt and C. Hinds and Y. W. Ho and D. Marquette and E. Quintana
rawtitle: A Floating Point Unit for the 68040
entry:
@InProceedings{McCloud:1990:FPU,
  author =       "S. McCloud and D. Anderson and C. DeWitt and C. Hinds
                 and Y. W. Ho and D. Marquette and E. Quintana",
  title =        "A Floating Point Unit for the 68040",
  crossref =     "IEEE:1990:PII",
  pages =        "187--190",
  year =         "1990",
  bibdate =      "Wed Sep 7 22:32:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: mastersthesis
filename: fparith.bib
label: Mills:1990:DIH
author: Karl Scott Mills
type: Thesis (M.S.E.E.)
school: University of Washington
address: Seattle, WA, USA
pages: v + 60 + 3
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Computer graphics.; Image processing --- Digital techniques.
acknowledgement: ack-nhfb
rawauthor: Karl Scott Mills
title:
The design and implementation of a high performance floating-point image processing and graphics subsystem for the NeXT computer

rawtitle:
The design and implementation of a high performance floating-point image processing and graphics subsystem for the {NeXT} computer

entry:
@MastersThesis{Mills:1990:DIH,
  author =       "Karl Scott Mills",
  title =        "The design and implementation of a high performance
                 floating-point image processing and graphics subsystem
                 for the {NeXT} computer",
  type =         "Thesis ({M.S.E.E.})",
  school =       "University of Washington",
  address =      "Seattle, WA, USA",
  pages =        "v + 60 + 3",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer graphics.; Image processing --- Digital
                 techniques.",
}


bibtype: article
filename: fparith.bib
label: Montoye:1990:DIR
author: R. K. Montoye and E. Hokenek and S. L. Runyon
title: Design of the IBM RISC System / 6000 floating-point execution unit
journal: j-IBM-JRD
volume: 34
number: 1
pages: 59--70
month: jan
monthnumber: 1
year: 1990
CODEN: IBMJAE
DOI: https://doi.org/10.1147/rd.341.0059
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Tue Mar 25 14:26:59 MST 1997
bibtimestamp: 1997.03.25 14:26:59 MST
URL: http://www.research.ibm.com/journal/rd/341/ibmrd3401G.pdf
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
corpsource: IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
thesaurus: Circuit layout CAD; Digital arithmetic; IBM computers; Logic CAD; Reduced instruction set computing
treatment: P Practical
rawauthor: R. K. Montoye and E. Hokenek and S. L. Runyon
rawtitle: Design of the {IBM RISC System\slash 6000} floating-point execution unit
abstract:
The IBM RISC System / 6000 (RS / 6000) floating-point unit (FPU) exemplifies a second-generation RISC CPU architecture and an implementation which greatly increases floating-point performance and accuracy. The key feature of the FPU is a unified floating-point multiply-add-fused unit (MAF) which performs the accumulate operation (A*B)+C as an indivisible operation. The paper first discusses the motivation for MAF, explaining in some detail why it is an appropriate addition to the floating-point architecture in VLSI. A summary of floating-point operations is then given, with a discussion to demonstrate the parallelism that is possible when the multiply and add are fused. This is followed by a description of the two-stage pipeline used for the version of IEEE double-precision floating-point arithmetic used in the RS / 6000 processor, with delays consistent with its over-all superscalar second-generation RISC architecture. Then the paper describes the interaction of logical and physical design required to incorporate several advances in VLSI arithmetic while accommodating required delay and technological (physical) constraints. The results are then summarized.

keywords:
Accumulate operation; accumulate operation; arithmetic; CAD; circuit layout CAD; digital arithmetic; floating-point architecture; Floating-point architecture; generation RISC CPU architecture; IBM computers; IBM RISC System/6000 floating-point execution unit; IBM RISC System / 6000 floating-point execution unit; IEEE double-precision floating-point; IEEE double-precision floating-point arithmetic; indivisible; Indivisible operation; logic; multiply-add-fused unit; operation; Parallelism; parallelism; reduced instruction set computing; second-; Second-generation RISC CPU architecture; stage pipeline; Superscalar second-generation RISC architecture; superscalar second-generation RISC architecture; two-; Two-stage pipeline; unified floating-point; Unified floating-point multiply-add-fused unit; VLSI arithmetic; VLSI arithmetic, IBM RISC System/6000 floating-point execution unit

classcodes:
B1265B (Logic circuits); B1130B (Computer-aided circuit analysis and design); B1265F (Microprocessors and microcomputers); C5230 (Digital arithmetic methods); C5220 (Computer architecture); C5210B (Computer-aided logic design)C7410D (Electronic engineering)

rawabstract:
The IBM RISC System\slash 6000 (RS\slash 6000) floating-point unit (FPU) exemplifies a second-generation RISC CPU architecture and an implementation which greatly increases floating-point performance and accuracy. The key feature of the FPU is a unified floating-point multiply-add-fused unit (MAF) which performs the accumulate operation (A*B)+C as an indivisible operation. The paper first discusses the motivation for MAF, explaining in some detail why it is an appropriate addition to the floating-point architecture in VLSI. A summary of floating-point operations is then given, with a discussion to demonstrate the parallelism that is possible when the multiply and add are fused. This is followed by a description of the two-stage pipeline used for the version of IEEE double-precision floating-point arithmetic used in the RS\slash 6000 processor, with delays consistent with its over-all superscalar second-generation RISC architecture. Then the paper describes the interaction of logical and physical design required to incorporate several advances in VLSI arithmetic while accommodating required delay and technological (physical) constraints. The results are then summarized.

entry:
@Article{Montoye:1990:DIR,
  author =       "R. K. Montoye and E. Hokenek and S. L. Runyon",
  title =        "Design of the {IBM RISC System\slash 6000}
                 floating-point execution unit",
  journal =      j-IBM-JRD,
  volume =       "34",
  number =       "1",
  pages =        "59--70",
  month =        jan,
  year =         "1990",
  CODEN =        "IBMJAE",
  DOI =          "https://doi.org/10.1147/rd.341.0059",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Mar 25 14:26:59 MST 1997",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ibmjrd.bib",
  URL =          "http://www.research.ibm.com/journal/rd/341/ibmrd3401G.pdf",
  abstract =     "The IBM RISC System\slash 6000 (RS\slash 6000)
                 floating-point unit (FPU) exemplifies a
                 second-generation RISC CPU architecture and an
                 implementation which greatly increases floating-point
                 performance and accuracy. The key feature of the FPU is
                 a unified floating-point multiply-add-fused unit (MAF)
                 which performs the accumulate operation (A*B)+C as an
                 indivisible operation. The paper first discusses the
                 motivation for MAF, explaining in some detail why it is
                 an appropriate addition to the floating-point
                 architecture in VLSI. A summary of floating-point
                 operations is then given, with a discussion to
                 demonstrate the parallelism that is possible when the
                 multiply and add are fused. This is followed by a
                 description of the two-stage pipeline used for the
                 version of IEEE double-precision floating-point
                 arithmetic used in the RS\slash 6000 processor, with
                 delays consistent with its over-all superscalar
                 second-generation RISC architecture. Then the paper
                 describes the interaction of logical and physical
                 design required to incorporate several advances in VLSI
                 arithmetic while accommodating required delay and
                 technological (physical) constraints. The results are
                 then summarized.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Res. Div., Thomas J. Watson Res. Center, Yorktown
                 Heights, NY, USA",
  classcodes =   "B1265B (Logic circuits); B1130B (Computer-aided
                 circuit analysis and design); B1265F (Microprocessors
                 and microcomputers); C5230 (Digital arithmetic
                 methods); C5220 (Computer architecture); C5210B
                 (Computer-aided logic design)C7410D (Electronic
                 engineering)",
  classification = "B1130B (Computer-aided circuit analysis and design);
                 B1265B (Logic circuits); B1265F (Microprocessors and
                 microcomputers); C5210B (Computer-aided logic design);
                 C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods); C7410D (Electronic engineering)",
  corpsource =   "IBM Res. Div., Thomas J. Watson Res. Center, Yorktown
                 Heights, NY, USA",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "Accumulate operation; accumulate operation;
                 arithmetic; CAD; circuit layout CAD; digital
                 arithmetic; floating-point architecture; Floating-point
                 architecture; generation RISC CPU architecture; IBM
                 computers; IBM RISC System/6000 floating-point
                 execution unit; IBM RISC System\slash 6000
                 floating-point execution unit; IEEE double-precision
                 floating-point; IEEE double-precision floating-point
                 arithmetic; indivisible; Indivisible operation; logic;
                 multiply-add-fused unit; operation; Parallelism;
                 parallelism; reduced instruction set computing;
                 second-; Second-generation RISC CPU architecture; stage
                 pipeline; Superscalar second-generation RISC
                 architecture; superscalar second-generation RISC
                 architecture; two-; Two-stage pipeline; unified
                 floating-point; Unified floating-point
                 multiply-add-fused unit; VLSI arithmetic; VLSI
                 arithmetic, IBM RISC System/6000 floating-point
                 execution unit",
  thesaurus =    "Circuit layout CAD; Digital arithmetic; IBM computers;
                 Logic CAD; Reduced instruction set computing",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Montuschi:1990:SSR
author: P. Montuschi and P. M. Mezzalama
title: Survey of square rooting algorithms
journal: j-IEE-PROC-COMPUT-DIGIT-TECH
volume: 137
number: 1
pages: 31--40
month: jan
monthnumber: 1
year: 1990
CODEN: ICDTEA
ISSN: 1350-2387 (print), 1359-7027 (electronic) OR 13502387 (print), 13597027 (electronic)
ISSNL: 1350-2387 OR 13502387
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
fjournal: IEE Proceedings. Computers and Digital Techniques
acknowledgement: ack-nhfb
rawauthor: P. Montuschi and P. M. Mezzalama
rawtitle: Survey of square rooting algorithms
entry:
@Article{Montuschi:1990:SSR,
  author =       "P. Montuschi and P. M. Mezzalama",
  title =        "Survey of square rooting algorithms",
  journal =      j-IEE-PROC-COMPUT-DIGIT-TECH,
  volume =       "137",
  number =       "1",
  pages =        "31--40",
  month =        jan,
  year =         "1990",
  CODEN =        "ICDTEA",
  ISSN =         "1350-2387 (print), 1359-7027 (electronic)",
  ISSN-L =       "1350-2387",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEE Proceedings. Computers and Digital Techniques",
  summary =      "The paper reviews the algorithms for the computation
                 of square roots for binary machines. After an initial
                 classification, the algorithms are analysed in detail
                 by considering their specific peculiarities and
                 properties. Finally, some comments are \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Morita:1990:FMM
author: Hikaru Morita
title: A Fast Modular-Multiplication Algorithm Based on a Higher Radix
journal: j-LECT-NOTES-COMP-SCI
volume: 435
pages: 387--??
year: 1990
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Mon Feb 4 12:01:59 MST 2002
bibtimestamp: 2002.02.04 12:01:59 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Hikaru Morita
rawtitle: A Fast Modular-Multiplication Algorithm Based on a Higher Radix
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t0435.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/0435/04350387.htm; http://link.springer-ny.com/link/service/series/0558/papers/0435/04350387.pdf

entry:
@Article{Morita:1990:FMM,
  author =       "Hikaru Morita",
  title =        "A Fast Modular-Multiplication Algorithm Based on a
                 Higher Radix",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "435",
  pages =        "387--??",
  year =         "1990",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Mon Feb 4 12:01:59 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t0435.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/0435/04350387.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/0435/04350387.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: mastersthesis
filename: fparith.bib
label: Mueller:1990:HCA
author: Volker Muller
type: Diplomarbeit
school: Institut fur angewandte Mathematik, Universitat Karlsruhe
month: dec
monthnumber: 12
year: 1990
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
acknowledgement: ack-nj
rawauthor: Volker M{\"u}ller
title:
Hochgenaue CORDIC-Algorithmen fur reelle Standardfunktionen mittels dynamischer Defektberechnung toenglish High-accuracy CORDIC Algorithms for Real Elementary Functions by Means of Dynamic Error Computation endtoenglish 

rawtitle:
{Hochgenaue CORDIC-Algorithmen f{\"u}r reelle Standardfunktionen mittels dynamischer Defektberechnung} \toenglish {High-accuracy CORDIC Algorithms for Real Elementary Functions by Means of Dynamic Error Computation} \endtoenglish

entry:
@MastersThesis{Mueller:1990:HCA,
  author =       "Volker M{\"u}ller",
  title =        "{Hochgenaue CORDIC-Algorithmen f{\"u}r reelle
                 Standardfunktionen mittels dynamischer
                 Defektberechnung} \toenglish {High-accuracy CORDIC
                 Algorithms for Real Elementary Functions by Means of
                 Dynamic Error Computation} \endtoenglish",
  type =         "{Diplomarbeit}",
  school =       "Institut f{\"u}r angewandte Mathematik,
                 Universit{\"a}t Karlsruhe",
  pages =        "??",
  month =        dec,
  year =         "1990",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Murthy:1990:MPA
author: Narayan Murthy and Allen Stix
title: Multiple precision arithmetic: a programming assignment in CS2 applying linked lists
journal: j-SIGCSE
volume: 22
number: 1
pages: 129--133
month: feb
monthnumber: 2
year: 1990
CODEN: SIGSD3
DOI: https://doi.org/10.1145/319059.323431
ISSN: 0097-8418 (print), 2331-3927 (electronic) OR 00978418 (print), 23313927 (electronic)
ISSNL: 0097-8418 OR 00978418
bibdate: Sat Nov 17 18:57:12 MST 2012
bibtimestamp: 2012.11.17 18:57:12 MST
fjournal: SIGCSE Bulletin (ACM Special Interest Group on Computer Science Education)
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J688
rawauthor: Narayan Murthy and Allen Stix
rawtitle: Multiple precision arithmetic: a programming assignment in {CS2} applying linked lists
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigcse1990.bib

entry:
@Article{Murthy:1990:MPA,
  author =       "Narayan Murthy and Allen Stix",
  title =        "Multiple precision arithmetic: a programming
                 assignment in {CS2} applying linked lists",
  journal =      j-SIGCSE,
  volume =       "22",
  number =       "1",
  pages =        "129--133",
  month =        feb,
  year =         "1990",
  CODEN =        "SIGSD3",
  DOI =          "https://doi.org/10.1145/319059.323431",
  ISSN =         "0097-8418 (print), 2331-3927 (electronic)",
  ISSN-L =       "0097-8418",
  bibdate =      "Sat Nov 17 18:57:12 MST 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigcse1990.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIGCSE Bulletin (ACM Special Interest Group on
                 Computer Science Education)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J688",
}


bibtype: article
filename: fparith.bib
label: Ohtomo:1990:FPD
author: Hiroyasu Ohtomo and Hisao Ishizuka and Masahiko Kashimura and Akio Nakajima and Tetsuhiro Hira
title: A 32-bit Floating Point Digital Signal Processor for Graphics Application
journal: j-NEC-RES-DEV
number: 99
pages: 47--??
month: oct
monthnumber: 10
year: 1990
CODEN: NECRAU
ISSN: 0048-0436 OR 00480436
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Nippon Electric Company research and development
acknowledgement: ack-nhfb
rawauthor: Hiroyasu Ohtomo and Hisao Ishizuka and Masahiko Kashimura and Akio Nakajima and Tetsuhiro Hira
rawtitle: A 32-bit Floating Point Digital Signal Processor for Graphics Application
entry:
@Article{Ohtomo:1990:FPD,
  author =       "Hiroyasu Ohtomo and Hisao Ishizuka and Masahiko
                 Kashimura and Akio Nakajima and Tetsuhiro Hira",
  title =        "A 32-bit Floating Point Digital Signal Processor for
                 Graphics Application",
  journal =      j-NEC-RES-DEV,
  volume =       "??",
  number =       "99",
  pages =        "47--??",
  month =        oct,
  year =         "1990",
  CODEN =        "NECRAU",
  ISSN =         "0048-0436",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Nippon Electric Company research and development",
}


bibtype: inproceedings
filename: fparith.bib
label: Olson:1990:FAA
author: T. Olson and B. Stewart
title: Floating-point architecture of the Am29050
crossref: Wescon:1990:WCR
pages: 214--217
year: 1990
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Adv. Micro Devices, Austin, TX, USA
thesaurus: Computer architecture; Digital arithmetic; Microprocessor chips; Reduced instruction set computing
rawauthor: T. Olson and B. Stewart
rawtitle: Floating-point architecture of the Am29050
abstract:
The Am29050 is the newest member of Advanced Micro Devices' 29K family of RISC microprocessors. It is both binary and pin compatible with the Am29000, and also incorporates a high-performance floating-point unit (FPU) on chip. The FPU, which complies with the IEEE 754 standard, consists of parallel add, multiply, and divide/square-root units, operating on single-precision and double-precision values. In addition to the standard operations, the FPU implements two types of multiply-add functions, which take three operands and produce one result. A single register file, which is shared between the integer and floating-point units, can supply two 64-bit operands and write back both a 32-bit integer result and a 64-bit floating-point result in a single cycle.

keywords:
29K family; 64 Bit; Advanced Micro Devices; Am29050; Double-precision; Floating point architecture; Floating point arithmetic; Floating-point unit; FPU; IEEE 754 standard; Multiply-add functions; Parallel add; RISC microprocessors; Single-precision

rawabstract:
The Am29050 is the newest member of Advanced Micro Devices' 29K family of RISC microprocessors. It is both binary and pin compatible with the Am29000, and also incorporates a high-performance floating-point unit (FPU) on chip. The FPU, which complies with the IEEE 754 standard, consists of parallel add, multiply, and divide/square-root units, operating on single-precision and double-precision values. In addition to the standard operations, the FPU implements two types of multiply-add functions, which take three operands and produce one result. A single register file, which is shared between the integer and floating-point units, can supply two 64-bit operands and write back both a 32-bit integer result and a 64-bit floating-point result in a single cycle.

entry:
@InProceedings{Olson:1990:FAA,
  author =       "T. Olson and B. Stewart",
  title =        "Floating-point architecture of the Am29050",
  crossref =     "Wescon:1990:WCR",
  pages =        "214--217",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Am29050 is the newest member of Advanced Micro
                 Devices' 29K family of RISC microprocessors. It is both
                 binary and pin compatible with the Am29000, and also
                 incorporates a high-performance floating-point unit
                 (FPU) on chip. The FPU, which complies with the IEEE
                 754 standard, consists of parallel add, multiply, and
                 divide/square-root units, operating on single-precision
                 and double-precision values. In addition to the
                 standard operations, the FPU implements two types of
                 multiply-add functions, which take three operands and
                 produce one result. A single register file, which is
                 shared between the integer and floating-point units,
                 can supply two 64-bit operands and write back both a
                 32-bit integer result and a 64-bit floating-point
                 result in a single cycle.",
  acknowledgement = ack-nhfb,
  affiliation =  "Adv. Micro Devices, Austin, TX, USA",
  availability = "Western Periodicals Co., 13000 Rayner Street, North
                 Hollywood, CA 91605, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C5230 (Digital arithmetic methods)",
  keywords =     "29K family; 64 Bit; Advanced Micro Devices; Am29050;
                 Double-precision; Floating point architecture; Floating
                 point arithmetic; Floating-point unit; FPU; IEEE 754
                 standard; Multiply-add functions; Parallel add; RISC
                 microprocessors; Single-precision",
  numericalindex = "Word length 6.4E+01 bit",
  thesaurus =    "Computer architecture; Digital arithmetic;
                 Microprocessor chips; Reduced instruction set
                 computing",
}


bibtype: article
filename: fparith.bib
label: Owens:1990:BSM
author: R. M. Owens and M. J. Irwin
title: Being stingy with multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 6
pages: 809--818
month: jun
monthnumber: 6
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.53602
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:02 MDT 2011
bibtimestamp: 2011.07.07 14:20:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=53602
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. M. Owens and M. J. Irwin
rawtitle: Being stingy with multipliers
entry:
@Article{Owens:1990:BSM,
  author =       "R. M. Owens and M. J. Irwin",
  title =        "Being stingy with multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "6",
  pages =        "809--818",
  month =        jun,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.53602",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=53602",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Palmore:1990:CAC
author: J. Palmore and C. Herring
title: Computer arithmetic, chaos and fractals
journal: j-PHYSICA-D
volume: 42
number: 1-3
pages: 99--110
month: jun
monthnumber: 6
year: 1990
CODEN: PDNPDT
ISSN: 0167-2789 (print), 1872-8022 (electronic) OR 01672789 (print), 18728022 (electronic)
ISSNL: 0167-2789 OR 01672789
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: Physica. D, Nonlinear phenomena
acknowledgement: ack-nhfb
affiliation: Department of Math., Illinois University, Urbana, IL, USA
journalURL: http://www.sciencedirect.com/science/journal/01672789
thesaurus: Chaos; Digital arithmetic; Fractals; Random number generation; Roundoff errors
rawauthor: J. Palmore and C. Herring
rawtitle: Computer arithmetic, chaos and fractals
note:
Ninth Annual International Conference of the Center for Nonlinear Studies on Self-Organizing, Collective and Cooperative Phenomena in Natural and Artificial Networks

abstract:
The authors explore aspects of computer arithmetic from the viewpoint of dynamical systems. They demonstrate the effects of finite precision arithmetic in three uniformly hyperbolic chaotic dynamical systems: Bernoulli shifts, cat maps, and pseudorandom number generators. They show that elementary floating-point operations in binary computer arithmetic possess an inherently fractal structure. Each of these dynamical systems allows us to compare the exact results in integer arithmetic with those obtained by using floating-point arithmetic.

keywords:
Bernoulli shifts; Binary computer arithmetic; Cat maps; Chaos; Computer arithmetic; Dynamical systems; Elementary floating-point operations; Finite precision arithmetic; Floating-point arithmetic; Fractal structure; Integer arithmetic; Pseudorandom number generators; Self-similar structure; Uniformly hyperbolic chaotic dynamical systems

rawabstract:
The authors explore aspects of computer arithmetic from the viewpoint of dynamical systems. They demonstrate the effects of finite precision arithmetic in three uniformly hyperbolic chaotic dynamical systems: Bernoulli shifts, cat maps, and pseudorandom number generators. They show that elementary floating-point operations in binary computer arithmetic possess an inherently fractal structure. Each of these dynamical systems allows us to compare the exact results in integer arithmetic with those obtained by using floating-point arithmetic.

rawnote:
Ninth Annual International Conference of the Center for Nonlinear Studies on Self-Organizing, Collective and Cooperative Phenomena in Natural and Artificial Networks

entry:
@Article{Palmore:1990:CAC,
  author =       "J. Palmore and C. Herring",
  title =        "Computer arithmetic, chaos and fractals",
  journal =      j-PHYSICA-D,
  volume =       "42",
  number =       "1-3",
  pages =        "99--110",
  month =        jun,
  year =         "1990",
  CODEN =        "PDNPDT",
  ISSN =         "0167-2789 (print), 1872-8022 (electronic)",
  ISSN-L =       "0167-2789",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Ninth Annual International Conference of the Center
                 for Nonlinear Studies on Self-Organizing, Collective
                 and Cooperative Phenomena in Natural and Artificial
                 Networks",
  abstract =     "The authors explore aspects of computer arithmetic
                 from the viewpoint of dynamical systems. They
                 demonstrate the effects of finite precision arithmetic
                 in three uniformly hyperbolic chaotic dynamical
                 systems: Bernoulli shifts, cat maps, and pseudorandom
                 number generators. They show that elementary
                 floating-point operations in binary computer arithmetic
                 possess an inherently fractal structure. Each of these
                 dynamical systems allows us to compare the exact
                 results in integer arithmetic with those obtained by
                 using floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Math., Illinois University, Urbana, IL,
                 USA",
  classification = "C1160 (Combinatorial mathematics); C5230 (Digital
                 arithmetic methods)",
  confdate =     "22-26 May 1989",
  conflocation = "Los Alamos, NM, USA",
  fjournal =     "Physica. D, Nonlinear phenomena",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01672789",
  keywords =     "Bernoulli shifts; Binary computer arithmetic; Cat
                 maps; Chaos; Computer arithmetic; Dynamical systems;
                 Elementary floating-point operations; Finite precision
                 arithmetic; Floating-point arithmetic; Fractal
                 structure; Integer arithmetic; Pseudorandom number
                 generators; Self-similar structure; Uniformly
                 hyperbolic chaotic dynamical systems",
  pubcountry =   "Netherlands",
  thesaurus =    "Chaos; Digital arithmetic; Fractals; Random number
                 generation; Roundoff errors",
}


bibtype: inproceedings
filename: fparith.bib
label: Pan:1990:FSI
author: J. Pan and K. N. Levitz
crossref: Chen:1990:CRT
pages: 505--510
year: 1990
bibdate: Wed Dec 13 18:41:54 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.13 18:41:54 ???
acknowledgement: ack-nhfb
affiliation: Div. of Computer Science, California University, Berkeley, CA, USA
thesaurus: Digital arithmetic; Formal specification; Microprocessor chips; Satellite computers; Standards
rawauthor: J. Pan and K. N. Levitz
title:
A Formal Specification of the IEEE Floating-Point Standard with Application to the Verification of Floating-Point Coprocessors

abstract:
A description is given of work in progress on verifying a floating-point coprocessor based on the MC68881/82, with respect to the IEEE standard floating-point arithmetic (ANSI-IEEE Std 754-1985). A complete formalization of the IEEE floating-point standard using the HOL (high-order-logic) specification and verification system is presented. The specification of floating-point numbers, floating-point arithmetic functions, rounding schemes and post-normalization is described. In order for the specification to be adaptable to different implementation, several model parameters are used in specifying all the functions. The floating-point coprocessor is specified as a hierarchy of interpreters. The communication with the CPU is modeled as standard interprocessor communication. A technique for verifying hierarchies of communicating hardware interpreters is described. (11 Refs.)

keywords:
ANSI-IEEE Std 754-1985; Communicating hardware interpreters; CPU communication; Floating-point coprocessors; Higher order logic specification; HOL; IEEE standard floating-point arithmetic; Interpreter hierarchy; Interprocessor communication; MC68881/82; Post-normalization; Rounding schemes; Standard formalization; Verification system

rawabstract:
A description is given of work in progress on verifying a floating-point coprocessor based on the MC68881/82, with respect to the IEEE standard floating-point arithmetic (ANSI-IEEE Std 754-1985). A complete formalization of the IEEE floating-point standard using the HOL (high-order-logic) specification and verification system is presented. The specification of floating-point numbers, floating-point arithmetic functions, rounding schemes and post-normalization is described. In order for the specification to be adaptable to different implementation, several model parameters are used in specifying all the functions. The floating-point coprocessor is specified as a hierarchy of interpreters. The communication with the CPU is modeled as standard interprocessor communication. A technique for verifying hierarchies of communicating hardware interpreters is described. (11 Refs.)

rawtitle:
A Formal Specification of the {IEEE Floating-Point Standard} with Application to the Verification of Floating-Point Coprocessors

entry:
@InProceedings{Pan:1990:FSI,
  author =       "J. Pan and K. N. Levitz",
  title =        "A Formal Specification of the {IEEE Floating-Point
                 Standard} with Application to the Verification of
                 Floating-Point Coprocessors",
  crossref =     "Chen:1990:CRT",
  pages =        "505--510",
  year =         "1990",
  bibdate =      "Wed Dec 13 18:41:54 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A description is given of work in progress on
                 verifying a floating-point coprocessor based on the
                 MC68881/82, with respect to the IEEE standard
                 floating-point arithmetic (ANSI-IEEE Std 754-1985). A
                 complete formalization of the IEEE floating-point
                 standard using the HOL (high-order-logic) specification
                 and verification system is presented. The specification
                 of floating-point numbers, floating-point arithmetic
                 functions, rounding schemes and post-normalization is
                 described. In order for the specification to be
                 adaptable to different implementation, several model
                 parameters are used in specifying all the functions.
                 The floating-point coprocessor is specified as a
                 hierarchy of interpreters. The communication with the
                 CPU is modeled as standard interprocessor
                 communication. A technique for verifying hierarchies of
                 communicating hardware interpreters is described. (11
                 Refs.)",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Div. of Computer Science, California University,
                 Berkeley, CA, USA",
  availability = "IEEE Computer Society Press, Los Alamitos, CA, USA",
  classification = "C5130 (Microprocessor chips); C5230 (Digital
                 arithmetic methods)",
  keywords =     "ANSI-IEEE Std 754-1985; Communicating hardware
                 interpreters; CPU communication; Floating-point
                 coprocessors; Higher order logic specification; HOL;
                 IEEE standard floating-point arithmetic; Interpreter
                 hierarchy; Interprocessor communication; MC68881/82;
                 Post-normalization; Rounding schemes; Standard
                 formalization; Verification system",
  thesaurus =    "Digital arithmetic; Formal specification;
                 Microprocessor chips; Satellite computers; Standards",
}


bibtype: article
filename: fparith.bib
label: Parhami:1990:GSD
author: Behrooz Parhami
title: Generalized Signed-Digit Number Systems: a Unifying Framework for Redundant Number Representations
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 1
pages: 89--98
month: jan
monthnumber: 1
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.46283
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Feb 15 15:47:08 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.02.15 15:47:08 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Behrooz Parhami
rawtitle: Generalized Signed-Digit Number Systems: a Unifying Framework for Redundant Number Representations
abstract:
Signed-digit (SD) number representation systems have been defined for any radix r ?? 3 with digit values ranging over the set $ ( - alpha , ldots , - 1, 0, 1, ldots , alpha ) $, where $ alpha $ is an arbitrary integer in the range $ 1 / 2 r > alpha > r $. Such number representation systems possess sufficient redundancy to allow for the annihilation of carry or borrow chains and hence result in fast propagation-free addition and subtraction. The author refers to the above as ordinary SD number systems and defines generalized SD number systems which contain them as a special symmetric subclass. It is shown that the generalization not only provides a unified view of all redundant number systems which have proven useful in practice (including stored-carry and stored-borrowed systems), but also leads to new number systems not examined before. Examples of such new number systems are stored-carry-or-borrow systems, stored-double-carry systems, and certain redundant decimal representations.

rawabstract:
Signed-digit (SD) number representation systems have been defined for any radix r ?? 3 with digit values ranging over the set $ ( - \alpha, \ldots {}, - 1, 0, 1, \ldots {}, \alpha) $, where $ \alpha $ is an arbitrary integer in the range $ 1 / 2 r > \alpha > r $. Such number representation systems possess sufficient redundancy to allow for the annihilation of carry or borrow chains and hence result in fast propagation-free addition and subtraction. The author refers to the above as ordinary SD number systems and defines generalized SD number systems which contain them as a special symmetric subclass. It is shown that the generalization not only provides a unified view of all redundant number systems which have proven useful in practice (including stored-carry and stored-borrowed systems), but also leads to new number systems not examined before. Examples of such new number systems are stored-carry-or-borrow systems, stored-double-carry systems, and certain redundant decimal representations.

entry:
@Article{Parhami:1990:GSD,
  author =       "Behrooz Parhami",
  title =        "Generalized Signed-Digit Number Systems: a Unifying
                 Framework for Redundant Number Representations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "1",
  pages =        "89--98",
  month =        jan,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.46283",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Feb 15 15:47:08 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Signed-digit (SD) number representation systems have
                 been defined for any radix r ?? 3 with digit values
                 ranging over the set $ ( - \alpha, \ldots {}, - 1, 0,
                 1, \ldots {}, \alpha) $, where $ \alpha $ is an
                 arbitrary integer in the range $ 1 / 2 r > \alpha > r
                 $. Such number representation systems possess
                 sufficient redundancy to allow for the annihilation of
                 carry or borrow chains and hence result in fast
                 propagation-free addition and subtraction. The author
                 refers to the above as ordinary SD number systems and
                 defines generalized SD number systems which contain
                 them as a special symmetric subclass. It is shown that
                 the generalization not only provides a unified view of
                 all redundant number systems which have proven useful
                 in practice (including stored-carry and stored-borrowed
                 systems), but also leads to new number systems not
                 examined before. Examples of such new number systems
                 are stored-carry-or-borrow systems, stored-double-carry
                 systems, and certain redundant decimal
                 representations.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Payne:1990:PLCa
author: M. Payne and C. Schaffert and B. Wichmann
title: Proposal for a language compatible arithmetic standard
journal: j-SIGNUM
volume: 25
number: 1
pages: 2--43
month: jan
monthnumber: 1
year: 1990
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: ACM SIGNUM Newsletter
acknowledgement: ack-nhfb
affiliation: Digital Equipment Corp, Maynard, MA, USA
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J690
thesaurus: Digital arithmetic; Mathematics computing; Standards
rawauthor: M. Payne and C. Schaffert and B. Wichmann
rawtitle: Proposal for a language compatible arithmetic standard
abstract:
Describes the proposal for an arithmetic standard which has been submitted to the American National Standards Institute and the International Organization for Standardization. It is being processed by the ANSI X3T2 committee and the ISO/IEC JTC1/SC22/WG11 working group. The specifications cover both integer and floating point arithmetic.

keywords:
American National Standards Institute; ANSI X3T2 committee; Floating point arithmetic; Integer arithmetic; International Organization for Standardization; Language compatible arithmetic standard

rawabstract:
Describes the proposal for an arithmetic standard which has been submitted to the American National Standards Institute and the International Organization for Standardization. It is being processed by the ANSI X3T2 committee and the ISO/IEC JTC1/SC22/WG11 working group. The specifications cover both integer and floating point arithmetic.

entry:
@Article{Payne:1990:PLCa,
  author =       "M. Payne and C. Schaffert and B. Wichmann",
  title =        "Proposal for a language compatible arithmetic
                 standard",
  journal =      j-SIGNUM,
  volume =       "25",
  number =       "1",
  pages =        "2--43",
  month =        jan,
  year =         "1990",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Describes the proposal for an arithmetic standard
                 which has been submitted to the American National
                 Standards Institute and the International Organization
                 for Standardization. It is being processed by the ANSI
                 X3T2 committee and the ISO/IEC JTC1/SC22/WG11 working
                 group. The specifications cover both integer and
                 floating point arithmetic.",
  acknowledgement = ack-nhfb,
  affiliation =  "Digital Equipment Corp, Maynard, MA, USA",
  classification = "C7310 (Mathematics)",
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J690",
  keywords =     "American National Standards Institute; ANSI X3T2
                 committee; Floating point arithmetic; Integer
                 arithmetic; International Organization for
                 Standardization; Language compatible arithmetic
                 standard",
  thesaurus =    "Digital arithmetic; Mathematics computing; Standards",
}


bibtype: article
filename: fparith.bib
label: Payne:1990:PLCb
author: M. Payne and C. Schaffert and B. Wichmann
title: Proposal for a language compatible arithmetic standard
journal: j-SIGPLAN
volume: 25
number: 1
pages: 59--86
month: jan
monthnumber: 1
year: 1990
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:15:49 MST 2003
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:15:49 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Digital Equipment Corp., Maynard, MA, USA
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
thesaurus: Digital arithmetic; High level languages; Standards
rawauthor: M. Payne and C. Schaffert and B. Wichmann
rawtitle: Proposal for a language compatible arithmetic standard
abstract:
The proposal for an arithmetic standard has been submitted to the American National Standard Institute and the International Organization for Standardization. The proposal covers both integer and floating point arithmetic. The underlying goal is to expedite the production of robust numerical software which is portable among the diverse arithmetic implementations currently in wide-spread use. The proposal requires that a complying system provide error detection capabilities beyond those currently required by many language standards. The proposal requires that a conforming system makes the values of certain parameters known to users, although the method for doing so is not specified. It also required a number of useful operations, beyond those usually implemented. It is acceptable to implement them by subroutine calls.

keywords:
American National Standard Institute; Error detection capabilities; Floating point arithmetic; International Organization for Standardization; Language compatible arithmetic standard; Robust numerical software; Subroutine calls

rawabstract:
The proposal for an arithmetic standard has been submitted to the American National Standard Institute and the International Organization for Standardization. The proposal covers both integer and floating point arithmetic. The underlying goal is to expedite the production of robust numerical software which is portable among the diverse arithmetic implementations currently in wide-spread use. The proposal requires that a complying system provide error detection capabilities beyond those currently required by many language standards. The proposal requires that a conforming system makes the values of certain parameters known to users, although the method for doing so is not specified. It also required a number of useful operations, beyond those usually implemented. It is acceptable to implement them by subroutine calls.

entry:
@Article{Payne:1990:PLCb,
  author =       "M. Payne and C. Schaffert and B. Wichmann",
  title =        "Proposal for a language compatible arithmetic
                 standard",
  journal =      j-SIGPLAN,
  volume =       "25",
  number =       "1",
  pages =        "59--86",
  month =        jan,
  year =         "1990",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:15:49 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The proposal for an arithmetic standard has been
                 submitted to the American National Standard Institute
                 and the International Organization for Standardization.
                 The proposal covers both integer and floating point
                 arithmetic. The underlying goal is to expedite the
                 production of robust numerical software which is
                 portable among the diverse arithmetic implementations
                 currently in wide-spread use. The proposal requires
                 that a complying system provide error detection
                 capabilities beyond those currently required by many
                 language standards. The proposal requires that a
                 conforming system makes the values of certain
                 parameters known to users, although the method for
                 doing so is not specified. It also required a number of
                 useful operations, beyond those usually implemented. It
                 is acceptable to implement them by subroutine calls.",
  acknowledgement = ack-nhfb,
  affiliation =  "Digital Equipment Corp., Maynard, MA, USA",
  classification = "C5230 (Digital arithmetic methods); C6140D (High
                 level languages)",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "American National Standard Institute; Error detection
                 capabilities; Floating point arithmetic; International
                 Organization for Standardization; Language compatible
                 arithmetic standard; Robust numerical software;
                 Subroutine calls",
  thesaurus =    "Digital arithmetic; High level languages; Standards",
}


bibtype: article
filename: fparith.bib
label: Peter:1990:PZW
author: O. Peter
title: Prozessor zieht Wurzeln toenglish Processor Extracts Roots endtoenglish
journal: j-CT
volume: 1
pages: 300--306
year: 1990
ISSN: 0724-8679 OR 07248679
bibdate: Fri Sep 16 16:30:41 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:41 ???
fjournal: C T: Magazin fur Computer Technik (Hannover)
acknowledgement: ack-nj
rawauthor: O. Peter
rawtitle: {Prozessor zieht Wurzeln} \toenglish {Processor Extracts Roots} \endtoenglish
entry:
@Article{Peter:1990:PZW,
  author =       "O. Peter",
  title =        "{Prozessor zieht Wurzeln} \toenglish {Processor
                 Extracts Roots} \endtoenglish",
  journal =      j-CT,
  volume =       "1",
  pages =        "300--306",
  year =         "1990",
  ISSN =         "0724-8679",
  bibdate =      "Fri Sep 16 16:30:41 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "C T: Magazin f{\"u}r Computer Technik (Hannover)",
}


bibtype: article
filename: fparith.bib
label: Piestrak:1990:DHS
author: S. J. Piestrak
title: Design of high-speed and cost-effective self-testing checkers for low-cost arithmetic codes
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 3
pages: 360--374
month: mar
monthnumber: 3
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.48866
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:00 MDT 2011
bibtimestamp: 2011.07.07 14:20:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=48866
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. J. Piestrak
rawtitle: Design of high-speed and cost-effective self-testing checkers for low-cost arithmetic codes
entry:
@Article{Piestrak:1990:DHS,
  author =       "S. J. Piestrak",
  title =        "Design of high-speed and cost-effective self-testing
                 checkers for low-cost arithmetic codes",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "3",
  pages =        "360--374",
  month =        mar,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.48866",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=48866",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Popov:1990:AFA
author: Wladimir Popov
journal: IMACS Ann. Comput. Appl. Math.
volume: 7
publisher: pub-BALTZER
address: pub-BALTZER:adr
pages: 55--66
year: 1990
MRclass: 03B70 (65G05)
MRnumber: 93g:03024
bibdate: Fri Dec 08 12:21:25 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 12:21:25 ???
acknowledgement: ack-nhfb
rawauthor: Wladimir Popov
title:
On the axiomatizations of floating-point arithmetics. Contributions to computer arithmetic and self-validating numerical methods (Basel, 1989)

rawtitle:
On the axiomatizations of floating-point arithmetics. Contributions to computer arithmetic and self-validating numerical methods ({Basel, 1989})

entry:
@Article{Popov:1990:AFA,
  author =       "Wladimir Popov",
  title =        "On the axiomatizations of floating-point arithmetics.
                 Contributions to computer arithmetic and
                 self-validating numerical methods ({Basel, 1989})",
  journal =      "IMACS Ann. Comput. Appl. Math.",
  volume =       "7",
  publisher =    pub-BALTZER,
  address =      pub-BALTZER:adr,
  pages =        "55--66",
  year =         "1990",
  MRclass =      "03B70 (65G05)",
  MRnumber =     "93g:03024",
  bibdate =      "Fri Dec 08 12:21:25 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Preparata:1990:PCD
author: F. P. Preparata and J. E. Vuillemin
title: Practical cellular dividers
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 5
pages: 605--614
month: may
monthnumber: 5
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.53574
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:01 MDT 2011
bibtimestamp: 2011.07.07 14:20:01 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=53574
fjournal: IEEE Transactions on Computers
language: English
acknowledgement: ack-nhfb
affiliation: Ecole Normale Superieure, Paris, France
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
thesaurus: Digital arithmetic; Dividing circuits; Parallel algorithms
rawauthor: F. P. Preparata and J. E. Vuillemin
rawtitle: Practical cellular dividers
abstract:
A discussion is presented of parallel division algorithms that can be classified among modified higher radix nonrestoring online division methods, where redundant representations are extensively utilized to speed up the operation. The network realizations of these algorithms are cellular, or even systolic with exclusively local control; they have both size (area) and time of $ O(n) $, where $n$ is the length of the dividend representation. The same structures can also be used as a signed, digit-serial multiplier. When suitably equipped with some control and a few registers, the divider / multiplier brings remarkable performance to large modular arithmetic, RSA cryptography, and greatest common divisor computations. They are also of interest for the design of floating-point units and signal processing applications.

keywords:
Digit-serial multiplier; Divider/multiplier; Floating-point units; Greatest common divisor computations; Modular arithmetic; Nonrestoring online division methods; Parallel division algorithms; Redundant representations; RSA cryptography; Signal processing; Signed; Systolic

rawabstract:
A discussion is presented of parallel division algorithms that can be classified among modified higher radix nonrestoring online division methods, where redundant representations are extensively utilized to speed up the operation. The network realizations of these algorithms are cellular, or even systolic with exclusively local control; they have both size (area) and time of $ O(n) $, where $n$ is the length of the dividend representation. The same structures can also be used as a signed, digit-serial multiplier. When suitably equipped with some control and a few registers, the divider\slash multiplier brings remarkable performance to large modular arithmetic, RSA cryptography, and greatest common divisor computations. They are also of interest for the design of floating-point units and signal processing applications.

entry:
@Article{Preparata:1990:PCD,
  author =       "F. P. Preparata and J. E. Vuillemin",
  title =        "Practical cellular dividers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "5",
  pages =        "605--614",
  month =        may,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.53574",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:01 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=53574",
  abstract =     "A discussion is presented of parallel division
                 algorithms that can be classified among modified higher
                 radix nonrestoring online division methods, where
                 redundant representations are extensively utilized to
                 speed up the operation. The network realizations of
                 these algorithms are cellular, or even systolic with
                 exclusively local control; they have both size (area)
                 and time of $ O(n) $, where $n$ is the length of the
                 dividend representation. The same structures can also
                 be used as a signed, digit-serial multiplier. When
                 suitably equipped with some control and a few
                 registers, the divider\slash multiplier brings
                 remarkable performance to large modular arithmetic, RSA
                 cryptography, and greatest common divisor computations.
                 They are also of interest for the design of
                 floating-point units and signal processing
                 applications.",
  acknowledgement = ack-nhfb,
  affiliation =  "Ecole Normale Superieure, Paris, France",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Digit-serial multiplier; Divider/multiplier;
                 Floating-point units; Greatest common divisor
                 computations; Modular arithmetic; Nonrestoring online
                 division methods; Parallel division algorithms;
                 Redundant representations; RSA cryptography; Signal
                 processing; Signed; Systolic",
  language =     "English",
  pubcountry =   "USA",
  thesaurus =    "Digital arithmetic; Dividing circuits; Parallel
                 algorithms",
}


