NAS Parallel Benchmarks Update
	       ------------------------------

NOTES:
-----

1) The data in these tables either replaces or supplements data in 

     RNR Technical Report RNR-93-016:
     "NAS Parallel Benchmark Results 10-93", 
     D.H. Bailey, E. Barszcz, L. Dagum, and H.D. Simon

   and entirely supercedes any previously released "NPB Update Tables".

2) These data are for general release.  The technical report and these
   supplemental tables are available electronically through 
   World Wide Web (WWW) accessible via mosaic at URL address:

   http://www.nas.nasa.gov/RNR/Parallel/NPB/*

   or via internet by sending an email request to leo@nas.nasa.gov

3) Some results for the EP benchmark are based on a reduced precision
   table lookup implementation rather than the direct intrinsic function 
   evaluation expected for this benchmark.  Results based on reduced
   precision table lookup have been marked by an asterisk.  This method
   will be disallowed in the future.

4) An unfortunate inconsistency has developed in the specification of 
   the class A size CG benchmark.  The original benchmark description 
   (as written in RNR Technical Report RNR-91-002) specified 15 iterations, 
   however subsequent publications (specifically NASA Tech Memorandum 103863) 
   specify 25 iterations.  For historical consistency we continue to report
   timings for 15 iterations, and results we have received based on 25
   iterations have been scaled by 15/25 and marked by an asterisk.  (The
   benchmark time scales linearly with number of iterations.)

5) The IBM Cluster consists of 9 IBM RS6000-320H workstations with 25 MHz
   clock rate, 16 MB memory and a token ring interconnect capable of
   16 Mbits/sec.  Timings are reported for benchmark implementations
   using Parasoft Express v. 3.2.5.  For further details on the implementations
   and results for PVM 2.x, PVM 3.x, p4, and C/Linda, see the report:
   "Efficiency Evaluation of Some Parallelization Tools on a Workstation
   Cluster Using the NAS Parallel Benchmarks", by Florian Sekup, Computing
   Center, Vienna University of Technology (fs@eacpc4.tuwien.ac.at), and 
   Josef Fritscher, Centro Svizzero di Calcolo Scientifico.

6) ADENART is a 256 node parallel system developed by Kyoto University and
   and Matsushita Electric Industrial Co. of Japan.  Each node consists
   of a 34 MHz RISC microprocessor with 8 MB of memory connected through
   a HyperCross interconnection network.  Hardware and software details may 
   be found in: 

	H. Kadota, K. Kaneko, Y. Tanikawa, and T. Nogi,
	"VLSI Parallel Computer with Data Transfer Network: ADENA",
	proceedings of 1989 International Conference on Parallel Processing,
	pp. I319-322, 1989.

	T. Nogi, "Parallel Computation on ADENA", in Parallel
   	Computing '91, D.J. Evans, G.R. Joubert, and H. Liddell (Editors),
   	pp. 619-626, 1992.