#!Paragon-XPS150 ##PROBLEM SIZE T42L16 (SMALL), ##OPTIMISATION LEVEL 1, ##Dr Patrick H. Worley, ##Oak Ridge National Laboratory, # #Performance calculated using time (/s) / 14339 (MFlop) for 216 timesteps # #System Description #------------------ # #11/17/95 # XPS150 # if77/Paragon Paragon Version R5.2 # if77 flags: -O4 -Mnodepchk -Knoieee # Paragon Software Release R1.3.3 # mpich 1.0.11 (arch=paragon device=nx) # #Timing Tables #------------- #make MACH=paragon COMM=mpich WORKSPACE=6700000 # #T42L16 # optimization level 1 #proc perf MFLOP/s 2 14.6535 #978.54s 4 28.9268 #495.70s 8 49.3258 #290.70s 16 98.8897 #145.00s 32 195.0884 #73.50s 64 373.6060 #38.38s 128 667.2406 #21.49s 256 1026.4137 #13.97s # # #Notes: #1) Mapped logical processor mesh to physcial processor mesh for all # processor numbers up to 512 (see -sz specifications). For 1024, # can map 32x32 logical mesh directly onto 16x64 physical processor # mesh. Results are provided both for the default mapping and for a # specific nearest neighbor "preserving" map for level 0 optimization. # Level 1 optimization for 1024 processors also uses the improved # mapping. #2) Missing optimization level 1 values denote problem sizes in which # options better than the default have not yet been identified.